JP2009545837A5 - - Google Patents

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Publication number
JP2009545837A5
JP2009545837A5 JP2009523029A JP2009523029A JP2009545837A5 JP 2009545837 A5 JP2009545837 A5 JP 2009545837A5 JP 2009523029 A JP2009523029 A JP 2009523029A JP 2009523029 A JP2009523029 A JP 2009523029A JP 2009545837 A5 JP2009545837 A5 JP 2009545837A5
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JP
Japan
Prior art keywords
mode
bus
lines
array
bit line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2009523029A
Other languages
English (en)
Japanese (ja)
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JP2009545837A (ja
JP5201143B2 (ja
Filing date
Publication date
Priority claimed from US11/461,369 external-priority patent/US7499366B2/en
Priority claimed from US11/461,352 external-priority patent/US7486587B2/en
Application filed filed Critical
Priority claimed from PCT/US2007/074901 external-priority patent/WO2008016948A2/en
Publication of JP2009545837A publication Critical patent/JP2009545837A/ja
Publication of JP2009545837A5 publication Critical patent/JP2009545837A5/ja
Application granted granted Critical
Publication of JP5201143B2 publication Critical patent/JP5201143B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2009523029A 2006-07-31 2007-07-31 読出／書込回路をメモリアレイに結合させるためのデュアルデータ依存型バスのための方法および装置 Active JP5201143B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11/461,369 2006-07-31
US11/461,369 US7499366B2 (en) 2006-07-31 2006-07-31 Method for using dual data-dependent busses for coupling read/write circuits to a memory array
US11/461,352 US7486587B2 (en) 2006-07-31 2006-07-31 Dual data-dependent busses for coupling read/write circuits to a memory array
US11/461,352 2006-07-31
PCT/US2007/074901 WO2008016948A2 (en) 2006-07-31 2007-07-31 Dual data-dependent busses for coupling read/write circuits to a memory array

Publications (3)

Publication Number Publication Date
JP2009545837A JP2009545837A (ja) 2009-12-24
JP2009545837A5 true JP2009545837A5 (de) 2010-09-16
JP5201143B2 JP5201143B2 (ja) 2013-06-05

Family

ID=38997822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009523029A Active JP5201143B2 (ja) 2006-07-31 2007-07-31 読出／書込回路をメモリアレイに結合させるためのデュアルデータ依存型バスのための方法および装置

Country Status (6)

Country Link
EP (1) EP2062263B1 (de)
JP (1) JP5201143B2 (de)
KR (1) KR101465557B1 (de)
AT (1) ATE556411T1 (de)
TW (1) TWI345790B (de)
WO (1) WO2008016948A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8279704B2 (en) * 2006-07-31 2012-10-02 Sandisk 3D Llc Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same
US8958230B2 (en) 2012-08-31 2015-02-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
GB2545264B (en) * 2015-12-11 2020-01-15 Advanced Risc Mach Ltd A storage array

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6229845B1 (en) * 1999-02-25 2001-05-08 Qlogic Corporation Bus driver with data dependent drive strength control logic
US6856572B2 (en) * 2000-04-28 2005-02-15 Matrix Semiconductor, Inc. Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device
JP4322645B2 (ja) * 2003-11-28 2009-09-02 株式会社日立製作所 半導体集積回路装置
CN1977337A (zh) * 2004-05-03 2007-06-06 统一半导体公司 非易失性可编程存储器
US7286439B2 (en) * 2004-12-30 2007-10-23 Sandisk 3D Llc Apparatus and method for hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders
US7054219B1 (en) * 2005-03-31 2006-05-30 Matrix Semiconductor, Inc. Transistor layout configuration for tight-pitched memory array lines

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