JP2009524169A - 予め飽和させる固定小数点乗算器 - Google Patents
予め飽和させる固定小数点乗算器 Download PDFInfo
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- JP2009524169A JP2009524169A JP2008551565A JP2008551565A JP2009524169A JP 2009524169 A JP2009524169 A JP 2009524169A JP 2008551565 A JP2008551565 A JP 2008551565A JP 2008551565 A JP2008551565 A JP 2008551565A JP 2009524169 A JP2009524169 A JP 2009524169A
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- 229920006395 saturated elastomer Polymers 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 claims description 14
- 238000001514 detection method Methods 0.000 claims description 11
- 238000009738 saturating Methods 0.000 claims description 7
- 230000000295 complement effect Effects 0.000 description 25
- 230000002411 adverse Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000079 presaturation Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49905—Exception handling
- G06F7/4991—Overflow or underflow
- G06F7/49921—Saturation, i.e. clipping the result to a minimum or maximum value
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
- G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
- G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
- G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
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- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Data Mining & Analysis (AREA)
- Databases & Information Systems (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Complex Calculations (AREA)
- Executing Machine-Instructions (AREA)
- Processing Of Color Television Signals (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Picture Signal Circuits (AREA)
Abstract
Description
・0は全てゼロで被乗数ビットを置換する;
・x1は該被乗数ビットを直接パスする(passes);
・x2は該被乗数ビットを1ビット位置、左シフトする(left-shifts);
・否定は該被乗数、シフトされた被乗数、またはゼロ値に関してビット単位の反転(bit-wise invert)(1の補数)を実行する。
Claims (15)
- 乗数および被乗数を備える、オペランドの少なくとも1つの既知のセットが、飽和を必要とするオーバフローを生じさせる、固定小数点の飽和させる乗算演算を実行する方法であって、
任意の乗算演算を実行する前に、オーバフローを生じさせる前記オペランドを検出すること、および
前記オペランドを乗算せずに飽和した結果を出力すること
を備える方法。 - オーバフローを生じさせる前記オペランドは、前記オペランドのビットフィールドにおいて表されることができる最大の負の数である、請求項1に記載の方法。
- 乗算演算が前記飽和した結果を生成するように、前記オペランドから得られた1つまたはそれより多くのパラメータを調整すること、および
前記調整されたパラメータを用いて乗算演算を実行することをさらに備える、請求項1に記載の方法。 - 前記オペランドから得られた1つまたはそれより多くのパラメータを調整することは、前記乗数から得られた1つまたはそれより多くのブースリコードされたビットグループを変更することを備える、請求項3に記載の方法。
- ブースリコードされたビットグループは、ブースリコードされたビットグループの選択をゼロから負のゼロに変更すること、および被乗数から得られた部分積への値1の加算を抑制することを備える、請求項4に記載の方法。
- 前記オペランドから得られた1つまたはそれより多くのパラメータを調整することが、前記オペランドから得られた部分積に値負の1を加算することを備える、請求項3に記載の方法。
- 前記飽和した結果を出力することは、乗算演算の積にかかわらず、乗算演算の該出力を強制的に飽和した結果にすることを備える、請求項1に記載の方法。
- 乗算演算の前記出力を強制的に飽和した結果にすることは、オーバフローを生じさせる前記オペランドを検出することに応答して、前記乗算演算の出力と前記飽和した結果との間で選択することを備える、請求項7に記載の方法。
- 乗数および被乗数を備える2つのオペランドを乗算し、それらの積を出力するように動作可能な乗算器回路、および
前記乗算器回路においてオーバフローを生じさせるオペランドを検出するように動作可能なオーバフローを予め検出する回路
を備える予め飽和させる乗算器。 - 前記オーバフローを予め検出する回路が、前記オペランドのビットフィールドにおいて表されることができる最大の負の値を検出する、請求項9に記載の乗算器。
- 前記乗算器回路は、前記乗数を複数のビットグループにリコードするように動作可能なブースリコーダを備え、各ビットグループは部分積として前記被乗数の正または負の倍数を選択し、前記ブースリコーダは、前記オーバフローを予め検出する回路に応答して、前記乗数において飽和した結果を生成するために1つまたはそれより多くのビットグループを変更するようにさらに動作可能である、請求項9に記載の乗算器。
- 前記ブースリコーダは、前記オーバフローを予め検出する回路に応答して、最下位のリコードされたビットグループに、負のゼロを強制的に選択させるように動作可能である、請求項11に記載の乗算器。
- 前記部分積を加算し、前記ブースリコードされたビットグループによって選択された負の部分積のために前記値1を加算するように動作可能な並列加算器をさらに備え、前記並列加算器が、前記オーバフローを予め検出する回路に応答して負のゼロのための前記値1の前記加算を抑制するようにさらに動作可能である、請求項11に記載の乗算器。
- 前記乗算器回路は、前記オーバフローを予め検出する回路に応答して前記積から前記値1を減算するように動作可能である、請求項9に記載の乗算器。
- 前記オーバフローを予め検出する回路に応答して前記乗算器回路からの前記積かまたは予め決められた飽和した結果のどちらかを出力するように動作可能な出力選択器をさらに備える、請求項9に記載の乗算器。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/336,358 US8082287B2 (en) | 2006-01-20 | 2006-01-20 | Pre-saturating fixed-point multiplier |
US11/336,358 | 2006-01-20 | ||
PCT/US2007/060816 WO2007085012A2 (en) | 2006-01-20 | 2007-01-22 | Pre-saturating fixed-point multiplier |
Related Child Applications (1)
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JP2011128153A Division JP5086466B2 (ja) | 2006-01-20 | 2011-06-08 | 予め飽和させる固定小数点乗算器 |
Publications (2)
Publication Number | Publication Date |
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JP2009524169A true JP2009524169A (ja) | 2009-06-25 |
JP5203972B2 JP5203972B2 (ja) | 2013-06-05 |
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JP2008551565A Active JP5203972B2 (ja) | 2006-01-20 | 2007-01-22 | 予め飽和させる固定小数点乗算器 |
JP2011128153A Active JP5086466B2 (ja) | 2006-01-20 | 2011-06-08 | 予め飽和させる固定小数点乗算器 |
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JP2011128153A Active JP5086466B2 (ja) | 2006-01-20 | 2011-06-08 | 予め飽和させる固定小数点乗算器 |
Country Status (10)
Country | Link |
---|---|
US (1) | US8082287B2 (ja) |
EP (1) | EP1974253A2 (ja) |
JP (2) | JP5203972B2 (ja) |
KR (1) | KR100958224B1 (ja) |
CN (1) | CN101371221B (ja) |
BR (1) | BRPI0707147A2 (ja) |
CA (1) | CA2635119C (ja) |
RU (1) | RU2408057C2 (ja) |
TW (1) | TWI396130B (ja) |
WO (1) | WO2007085012A2 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8316071B2 (en) * | 2009-05-27 | 2012-11-20 | Advanced Micro Devices, Inc. | Arithmetic processing unit that performs multiply and multiply-add operations with saturation and method therefor |
US8892621B2 (en) * | 2011-12-19 | 2014-11-18 | Lsi Corporation | Implementation of negation in a multiplication operation without post-incrementation |
KR20130111721A (ko) * | 2012-04-02 | 2013-10-11 | 삼성전자주식회사 | 부분 곱 생성기의 부스코드 생성방법, 컴퓨터 시스템 및 그 매체와 디지털 신호프로세서 |
US9323498B2 (en) * | 2013-03-13 | 2016-04-26 | Wisconsin Alumni Research Foundation | Multiplier circuit with dynamic energy consumption adjustment |
US9747074B2 (en) | 2014-02-25 | 2017-08-29 | Kabushiki Kaisha Toshiba | Division circuit and microprocessor |
KR101644039B1 (ko) * | 2015-06-11 | 2016-07-29 | 에스케이텔레콤 주식회사 | 고정소수점 연산 방법 및 고정소수점 연산 장치 |
US11327718B2 (en) * | 2020-03-19 | 2022-05-10 | Kabushiki Kaisha Toshiba | Arithmetic circuitry for power-efficient multiply-add operations |
JP7381426B2 (ja) | 2020-03-19 | 2023-11-15 | 株式会社東芝 | 演算回路 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01267728A (ja) * | 1988-04-19 | 1989-10-25 | Ricoh Co Ltd | 乗算器 |
JPH10149277A (ja) * | 1996-11-20 | 1998-06-02 | Ricoh Co Ltd | 乗算装置 |
JPH11126157A (ja) * | 1997-10-24 | 1999-05-11 | Matsushita Electric Ind Co Ltd | 乗算方法および乗算回路 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS6162937A (ja) * | 1984-09-04 | 1986-03-31 | Toshiba Corp | 乗算器 |
US5220525A (en) | 1991-11-04 | 1993-06-15 | Motorola, Inc. | Recoded iterative multiplier |
US5793315A (en) * | 1996-05-31 | 1998-08-11 | Motorola, Inc. | Bit-serial digital expandor |
EP0992885B1 (en) | 1998-10-06 | 2005-12-28 | Texas Instruments Incorporated | Multiplier accumulator circuits |
EP0992916A1 (en) * | 1998-10-06 | 2000-04-12 | Texas Instruments Inc. | Digital signal processor |
JP3530418B2 (ja) | 1999-05-13 | 2004-05-24 | Necエレクトロニクス株式会社 | 乗算装置 |
US6574651B1 (en) | 1999-10-01 | 2003-06-03 | Hitachi, Ltd. | Method and apparatus for arithmetic operation on vectored data |
US7058830B2 (en) | 2003-03-19 | 2006-06-06 | International Business Machines Corporation | Power saving in a floating point unit using a multiplier and aligner bypass |
US7689641B2 (en) | 2003-06-30 | 2010-03-30 | Intel Corporation | SIMD integer multiply high with round and shift |
US20080098057A1 (en) * | 2004-08-26 | 2008-04-24 | Daisuke Takeuchi | Multiplication Apparatus |
-
2006
- 2006-01-20 US US11/336,358 patent/US8082287B2/en active Active
-
2007
- 2007-01-22 TW TW096102331A patent/TWI396130B/zh active
- 2007-01-22 BR BRPI0707147-7A patent/BRPI0707147A2/pt not_active Application Discontinuation
- 2007-01-22 CN CN2007800026442A patent/CN101371221B/zh active Active
- 2007-01-22 WO PCT/US2007/060816 patent/WO2007085012A2/en active Application Filing
- 2007-01-22 EP EP07710246A patent/EP1974253A2/en not_active Ceased
- 2007-01-22 RU RU2008134127/08A patent/RU2408057C2/ru active
- 2007-01-22 CA CA2635119A patent/CA2635119C/en active Active
- 2007-01-22 KR KR1020087020038A patent/KR100958224B1/ko active IP Right Grant
- 2007-01-22 JP JP2008551565A patent/JP5203972B2/ja active Active
-
2011
- 2011-06-08 JP JP2011128153A patent/JP5086466B2/ja active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01267728A (ja) * | 1988-04-19 | 1989-10-25 | Ricoh Co Ltd | 乗算器 |
JPH10149277A (ja) * | 1996-11-20 | 1998-06-02 | Ricoh Co Ltd | 乗算装置 |
JPH11126157A (ja) * | 1997-10-24 | 1999-05-11 | Matsushita Electric Ind Co Ltd | 乗算方法および乗算回路 |
Also Published As
Publication number | Publication date |
---|---|
TW200736989A (en) | 2007-10-01 |
RU2008134127A (ru) | 2010-02-27 |
WO2007085012A2 (en) | 2007-07-26 |
US20070174379A1 (en) | 2007-07-26 |
JP5086466B2 (ja) | 2012-11-28 |
JP5203972B2 (ja) | 2013-06-05 |
CA2635119A1 (en) | 2007-07-26 |
RU2408057C2 (ru) | 2010-12-27 |
US8082287B2 (en) | 2011-12-20 |
CA2635119C (en) | 2013-07-30 |
TWI396130B (zh) | 2013-05-11 |
BRPI0707147A2 (pt) | 2011-04-19 |
JP2011248904A (ja) | 2011-12-08 |
KR100958224B1 (ko) | 2010-05-17 |
WO2007085012A3 (en) | 2008-01-24 |
KR20080089640A (ko) | 2008-10-07 |
CN101371221A (zh) | 2009-02-18 |
EP1974253A2 (en) | 2008-10-01 |
CN101371221B (zh) | 2012-05-30 |
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|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |