MX2008009315A - Pre-saturating fixed-point multiplier - Google Patents

Abstract

A pre-saturating multiplier inspects the operands to a multiply operation prior to performing any multiplication. If the operands will cause an overflow requiring saturation, the multiplier outputs the saturated value without multiplying the original operands. In one embodiment, parameters derived from the operands are altered such that when the multiply operation is performed on the altered parameters, the multiplier produces the saturated result. This may comprise altering a Booth recoded bit group to select a negative zero instead of a zero as a partial product, and suppressing the addition of the value one to the partial products (thus effectively subtracting the value one). In another embodiment, when the operands that will cause an overflow are detected, the output of the multiplier is forced to a predetermined saturation value.

Description

FIXED POINT MULTIPLIER OF PREVIOUS SATURATION FIELD OF THE INVENTION The present disclosure generally refers to the field of digital circuits and in particular to a fixed saturation point multiplier prior.

BACKGROUND OF THE INVENTION Fixed-point multiplication is a fundamental arithmetic operation executed by digital computational circuits, such as processors. Most of the processor instruction set architectures include a variety of fixed-point multiplication instructions. A known risk of fixed point multiplication is that under some conditions (as will be described in more detail below), a product can exceed the numerical value that can be represented in the available width, a condition known as overflow. In this case, to avoid a net misrepresentation of the product, a multiplication instruction will specify a "saturated" output, which is the largest numerical value that can be represented in the available field, in effect, the closest approximation possible to the real product. This is known as a saturation fixed point multiplication instruction. These instructions usually specify a bit width for the product that is twice the bit width of the operands. Both integer and fractional values can be represented in fixed point digital form, depending on the convention used. Commonly, all modem processors use the complement format of two to represent positive and negative integers in fixed-width digital representations. The complement format of two is common. In the complement representation of two, the integers are "signed". That is, if an integer is positive or negative it can be determined by inspection of the Most Significant Bit (MSB), or the "signature bit". Additionally, in the complement representation of two, binary arithmetic operations on signed integers produce the complement results of two correct ones. The complement numbers of two positives are represented in a simple binary form with a zero signature bit. Consequently, the largest positive number that can be represented in the complement format of two is 2n_1-l, where n is the width of bit of the digital representation. The complement numbers of two negatives are represented as the binary number that when they are added to a positive number of the same magnitude are equal to zero. The complement numbers of two negatives have a signature bit of one. Because the complement representation of two of negative numbers can use the n bits of the digital representation, the largest negative number that can be represented in the complement format of two is 2n_1, which is one greater in magnitude than the positive number of two more positive. Therefore, for example, the range of signed integer values that can be represented in a 32-bit field is -231 (0x8000 0000) to + 231-1 (0x7FFF FFFF). The negation of any complement number of two can be formed by inverting at the bit level the number (producing the complement of one), and adding one. Therefore, one way to calculate the complement representation of two of a negative number is to invert the binary representation of the corresponding positive number (which is the complement form of one of that positive number) and add one. The only exception to this algorithm for negation is the largest negative number that can be represented. The realization of a negation of complement of two in that number results in the same number, which is an overflow error. Note also that the negation of the complement of zero of two produces zero, the inversion of all the bits produces all ones, and the addition of one produces zero (when the execution is discarded). Fractional values can be represented in fixed-width digital form using the so-called notation in Q format. In the notation in Qn.x format, the bits of a value are interpreted as: a signature bit, n integer bits and x fraction bits. A common Q format for digital signal processing is QO.x (or simply Q.x) indicating that there is a signature bit, no integer bit, and x fraction bits. A number in the notation Q.31 would be expressed in 32 bits and would have values that range from -1 (0x8000 0000) to 1-2"31 (ox7FFF FFFF). When multiplying the numbers in Q format, it is important to consider the point For example, multiplying a Q.15 times a Q.15 will produce a result in Q2.30 However, it is desirable to keep the value in the Qx format To handle this, multiplication operations include a multiplication by a factor of 2, which is equivalent to a left shift operation, to produce a result Q.31. The multiplication of two values of n-bits together will always produce a value that can be represented in 2n bits. The dubbing of this product will produce a value that can be represented in 2n bits in all but one case: the maximum negative value. The maximum negative value in complement of two is a signature bit (MSB) of one with all the other zero bits. Changing this value to the left results in an overflow. An example is the following multiplication of two 16-bit operands to generate a 32-bit product. Each of the operands is negative (signature bit of one), and its product should be a positive number. 0x8000 x 0x8000 = 0x4000 0000 Multiplication 0x4000 0000 x 0x2 = 0x8000 0000 Dubbing (incorrect result, should be positive) 0x8000 0000 - 1 = 0x7FFF FFFF Result Saturated (largest positive value) In this example, the two operands are each the largest negative number that can be represented in 16 bits in the complement format of two. Your product should produce a large positive value. However, the actual result of the dubbing of the multiplication instruction is the largest negative value. Therefore, a 1 'must be subtracted from this value to obtain the saturation value of 0x7FFFFFFF, a zero signature bit with all the ones in the other bit positions. Conventional saturation multipliers detect an overflow condition only after the multiplication was made, and then they must take the steps to correct the overflow condition by saturating the output. In some executions, this may require stopping the processor, such as causing an exception. This adversely impacts processor performance and results in increased power consumption. Even in situations where overflow is saturated in hardware, doing this after the multiplication is complete has an adverse impact on performance.

SUMMARY OF THE INVENTION According to one or more modalities, a previous saturation multiplier inspects the operands for a multiplication operation prior to the execution of any multiplication. If the operands will cause an overflow that requires saturation, the multiplier emits the saturated value without multiplying the operands. In one modality, parameters derived from the operands are altered so that when the multiplication operation is performed on the altered parameters, the multiplier produces the saturated result. This may involve altering a group of bits registered in the booth to select a negative zero instead of a zero as a partial product, and suppressing the addition of the value one to the partial products (effectively subtracting the value of one). ). In another embodiment, when the operands that will cause an overflow are detected, the output of the multiplier is forced to a predetermined saturation value. One embodiment refers to a method for executing a fixed-point saturation multiplication operation for which a known set of operands, comprising a multiplier and a multiplier, will cause an overflow that requires saturation. The operands that will cause an overflow are detected prior to the execution of any multiplication operation, and a saturated result is issued without multiplying the operands. Another modality refers to the previous saturation multiplier that includes a multiplier circuit that operates to multiply two operands, comprising a multiplier and a multiplicand, and to emit its product. The previous saturation multiplier also it includes an overflow pre-detection circuit that operates to detect operands that will cause an overflow in the multiplier circuit.

BRIEF DESCRIPTION OF THE FIGURES Fig. 1 is a functional block diagram of a previous saturation multiplier according to one embodiment. Figure 2 is a functional block diagram of a previous saturation multiplier according to another embodiment. Figure 3 is a flow chart of a method for executing a pre-saturation multiplication operation.

DETAILED DESCRIPTION OF THE INVENTION A multiplier detects operands for a multiplication operation that will result in an overflow condition in case multiplication is performed. In response to this detection, the multiplier emits a saturated value. In one modality, the multiplier emits a saturated value by altering the operands so that the multiplication operation will result in the saturated value as the product. Figure 1 shows a previous saturation multiplier 40 according to this embodiment. A GPR record 42 contains the operands of the multiplier (MR) and multiplier (MD). The multiplier is entered into a cabin recorder circuit 44. The cabin register (sometimes referred to as a modified cabin register) is a technique to reduce the number of partial products that will be added in the execution of a multiplication operation. Instead of considering each bit in the multiplier and generating a corresponding changed partial product comprising either the multiplicand or zero, the bits of the multiplier are considered in groups, and the changed partial products comprising +/- multiples of the multiplier are added. This technique reduces the number of partial products that are going to be added. For example, in the radix-4 Cabinet Register, the bits of the multiplier are considered in groups of two, together with the MSB of the previous group (with a zero appended to the first group). The partial products are then generated based on the value of the groups of bits, according to the following table. Group of Partial Product Bits 000 0 001 1 x multiplying 010 1 x multiplying 011 2 x multiplying 100 -2 x multiplying 101 -1 x multiplying 110 -1 x multiplying 111 0 Table 1: Radix-4 Cabinet Record For each group of registered bits of Cabin in the multiplier, the multiplicand is multiplied by the indicated factor, and the resulting partial product is changed to the position of the group of bits within the multiplier. The partial products are then added together to produce the product. When you multiply signed values, the Radix-4 Cab record can reduce the number of partial products by up to half. In this embodiment, the outputs of the Cab recorder 44 select the partial products for the Wallace Tree 50 (or other adders) through the Cabine 48 multiplexers. The Cabine 48 multiplexers select the appropriately modified multiplier from the logic of change / inversion 49, and each multiplexer 48 is aligned to the position of the group of bits registered in the multiplier. The logic of change / inversion 49 generates the modified multiplicands specified in Table 1 in the following way: • 0 replaces all zeros for multiplying bits; · Xl passes the multiplicand bits directly; • x2 changes the bits on the left by multiplying a bit position; and • a negation makes an inversion at the bit level (complement of one) in the multiplying, multiplying changed, or zero value. It can be seen that the negation is not a complement until a? 1 'in the LSB is added to the partial products within the Wallace Tree 50 (by the complement rule of two for the negation: complement of one + 1). The Wallace Tree 50 adds the partial products, issuing a sum and holder, which are added in a carry propagation adder 52, and the product is secured at 54. Those skilled in the art will recognize that the output of the logger and the outputs of the Cabine 48 multiplexers (or the multiplicand value) can be secured to allow channeling. An overflow detection circuit 56 monitors the multiplier and multiplying at the start of each multiplication operation, detecting values of the operands that will result in an overflow that requires saturation. When a pending overflow is detected, the overflow detection circuit 56 signals the Cabinet recorder 44 to alter the register of the multiplier bits, and indicates to the Tree 50 link to alter the sum of partial products, such that the multiplication operation will result in a value saturated for the product. This is feasible because a limited number of operands will cause an overflow, and these operations are known in advance. In particular, in one modality, only the case of the multiplier and the multiplier, both comprising the largest negative value, will cause an overflow that requires saturation. When this condition is detected, the overflow detection circuit 56 sends a signal to the Cabinet recorder 44 to alter the Cabinet register. In response, Cabinet Recorder 44 modifies the least significant group of registered cabin bits (which, having a value of 000, would normally select a zero) to select a negative zero. The change / inversion logic 49 provides the zero complement of one (ie, all ones), and instructs the Wallace Tree 50 to add a? 1 'to the partial products. The overflow detection circuit 56 additionally directs a suppression signal to the Wallace Tree 50 to suppress the addition of the '1' associated with the negation of zero (note that in a pipelined run, the signal "suppress +1" would be ensured ). Therefore, the complement of zeros of one of extended signature (OxFFFF FFFF) is added as a partial product, but the corresponding? 1 'is not efficiently subtracted from the result. For example: OxBOOO x 0x8000 = 0x40000000 Multiplication of two more negative values 0x40000000 x 0x2 0x80000000 Dubbing 0x80000000 + OxFFFFFFFF = 0x7 FFFFFFF Result Saturated (effectively subtract? ') This saturated result is emitted by the carrier propagation adder 52, and secured as the product by 54. According to this mode, the timing of the saturation multiplication operation is the same as that for operands that do not cause an overflow and therefore require saturation. In particular, a delay is not added to the output of multiplier 40. Therefore, this modality may find a particular application in the situation where the timing of the multiplication operation is critical, and where an additional delay can not be tolerated at the output of the multiplier 40. Figure 2 shows another embodiment of a previous saturation multiplier 40, wherein corresponding components are numbered accordingly. In this mode, the overflow detection circuit 56 monitors the multiplier and the multiplier, detecting the known operands that will result in an overflow that requires saturation. When these operands are detected, the overflow detection circuit 56 outputs a signal that replaces a saturated result for the product output of the multiplier 40. For example, the overflow detection circuit 56 can output a multiplexer selection signal that orders the multiplexer 60 select a predetermined saturation output instead of the output of the carrier propagation adder 52. The predetermined saturation output may comprise a hard-wired value (i.e., bit compositions attached to high or low voltage rails) , or alternatively may comprise the output of a storage location such as a register. In a mode wherein a plurality of operands may cause overflows that require different values of saturation, the overflow detection circuit 56 can output a multiplexer selection signal of multiple bits, which chooses between a plurality of predetermined saturation values and the output of the adder 52. The output of the overflow detection circuit 56 can be secure in a channeled run. In this embodiment, the multiplication operation may be suppressed (i.e., Cabinet Recorder 44, logical block 49, Wallace Tree 50, carrier propagation adder 52, and other multiplier circuits may be disabled) to reduce power consumption . Alternatively, the multiplication of the operands may be allowed to advance through the multiplier 40, and the result is simply discarded since the saturated result is secured at 54 instead. In this embodiment, the delay of the multiplexer 60 is added to each multiplication operation executed by the multiplier 40, although this delay can be mitigated by using an unused BIFURCATION of an existing multiplexer, using an insurance-mux, or through other known techniques in the matter. The overflow condition is determined very early, and the decision to select a saturated value is not part of the critical path. Figure 3 shows a method for executing a fixed-point saturation multiplication operation for which at least one set of known operands will cause an overflow that requires saturation. Initially (ie, prior to the execution of any multiplication), the operands are inspected (block 70). The operands are compared with known values that will cause an overflow (block 72). For example, in some cases, if both operands comprise the largest negative value that can be represented within the operand bit field, an overflow will result. If the multiplication of the operated ones will not cause an overflow (block 72), the multiplication is carried out and the results are emitted (block 74). If the multiplication of the operands will result in an overflow that requires saturation (block 72), then according to one or more modes, the saturated result is issued without multiplying the original operands (block 76). In one embodiment, this involves altering the parameters generated from the operands so that the execution of the multiplication operation in the altered parameters will result in the value saturated as the product of the multiplication operation. In another embodiment, the output of the saturated result comprises selecting a predetermined saturation value as the output in place of the product from the multiplication operation. In both modes (ie, those shown in Figures 1 and 2), the operands that will cause an overflow are detected in advance, and the multiplier 40 outputs a saturated result directly. This represents a significant performance improvement and power savings over the conventional methodology that consists of detecting only the overflow by inspection of the product, and later substituting a saturated value for the product. The multiplier 40, according to one or more embodiments described herein, is particularly convenient for high-speed processors and / or processors where low power consumption is a critical factor, such as for battery-powered portable electronic devices. Although the present inventive concepts have been described here with respect to particular characteristics, aspects and modalities thereof, it will be apparent that various variations, modifications and other modalities within the broad scope are possible. scope of the present teachings. The present embodiments will then be construed in all respects as illustrative and not restrictive and all changes arising within the meaning and range of equivalence of the appended claims are intended to include them.

Claims (15)

NOVELTY OF THE INVENTION Having described the present invention, it is considered as a novelty and, therefore, the content of the following is claimed as property: CLAIMS

1. - A method for executing a fixed point saturation multiplication operation for which at least one set of known operands, comprising a multiplier and a multiplier, will cause an overflow that requires saturation, comprising: detecting the operands that will cause a overflow before carrying out any multiplication operation; and emit a saturated result without multiplying the operands.

2. - The method according to claim 1, characterized in that the operands that will cause an overflow are the largest negative numbers that can be represented in the operand bit field. 3.- The method of compliance with the claim 1, further comprising: adjusting one or more parameters derived from the operands so that a multiplication operation will generate the saturated result; and execute a multiplication operation with the adjusted parameters. 4. - The method according to claim 3, characterized in that the adjustment of one or more parameters derived from the operands comprises altering one or more of the groups of registered cabin bits derived from the multiplier. 5. - The method according to claim 4, characterized in that the alteration of a group of registered cabin bits comprises changing the selection of a group of registered cabin bits from zero to negative zero and suppressing the addition of the value one to products partial derivatives of the multiplying. 6. - The method according to claim 3, characterized in that the adjustment of one or more parameters derived from the operands comprises adding the negative value one to partial products derived from the operands. 7. - The method according to claim 1, characterized in that the emission of the saturated result comprises forcing the output of a multiplication operation to a saturated result without considering the product of the multiplication operation. 8. - The method according to claim 7, characterized in that the forced output of a multiplication operation to a saturated result comprises selecting between the output of the multiplication operation and the saturated result in response to the detection of the operated that will cause an overflow. 9. - A prior saturation multiplier, comprising: a multiplier circuit that operates to multiply two operands, comprising a multiplier and a multiplicand, and to emit its product; and an overflow pre-detection circuit that operates to detect operands that will cause an overflow in the multiplier circuit. 10. - The multiplier according to claim 9, characterized in that the overflow pre-detection circuit detects the largest negative values that can be represented in the operand bit fields. 11. - The multiplier according to claim 9, characterized in that the multiplier circuit comprises a cabin recorder that operates to register the multiplier in groups of bits, each group of bits selects a positive or negative multiple of the multiplying as a partial product, the cabinetary recorder also operates to alter one or more groups of bits in order to produce a saturated result in the multiplier, in response to the previous overflow detection circuit. 12. - The multiplier according to claim 11, characterized in that the logger operates to force the least significant recorded group of bits to select the negative zero in response to the previous overflow detection circuit. 1

3. - The multiplier according to claim 11, which further comprises a parallel adder that operates to add the partial products and to add the value one for negative partial products selected by the groups of registered bits of Cabin, the parallel adder also operates to suppress the addition of the value one for a negative zero in response to the previous overfill detection circuit. 1

4. - The multiplier according to claim 9, characterized in that the multiplier circuit operates to subtract the value one from the product in response to the pre-detection circuit of overflow. 1

5. The multiplier according to claim 9, fer comprising an output selector that operates to output either the product from the multiplier circuit or a predetermined saturated result in response to the previous overflow detection circuit.