JP2009282285A - Image display device and mounting inspection method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a determination technique based on quantitative data using measured resistance values instead of appearance as a mounting inspection method of COG mounting. <P>SOLUTION: This liquid crystal display device has an image display panel having a TFT array substrate, a driver IC COG-mounted on the image display panel, and a FPC which is mounted on the image display panel and supplies signals and electric power to the driver IC. The driver IC has one or more sets of dummy terminal pads mutually connected within a combination of at least two of the pads. The TFT array substrate has one or more sets of COG connecting terminal pads which are arranged so as to be ACF-connected to the dummy pads and insulated mutually. A lead wire is drawn from the COG connecting pads to one set of inspection terminal pads arranged on the FPC via an FPC mounting terminal region. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit for driving an image display panel, an image display device provided with a flexible printed wiring board, and an inspection method when the semiconductor integrated circuit is mounted, and is particularly driven on a TFT array substrate such as a liquid crystal display device. This is suitable for a connection inspection method after mounting an image display panel on which a circuit is mounted by COG.

  COG for mounting electronic components such as a semiconductor integrated circuit (hereinafter referred to as IC) by thermocompression bonding through an anisotropic conductive film (hereinafter referred to as ACF) containing conductive particles on a connection terminal pad of a transparent mounting substrate (Chip On Glass: Technology for directly mounting an IC on a glass substrate) A mounting method is widely used. In this COG mounting method, as one method for confirming the mounting / connection state between a COG connection terminal pad of an electronic component and the connection terminal pad, the connection terminal pad of the glass substrate as the mounting substrate is used. A method of observing a raised state (= indentation: pressed trace) of a press-bonded portion with a microscope through a transparent glass substrate is well known. (Patent Document 1)

  As another method, two COG connection terminal pads short-circuited in the IC mounted on the mounting substrate are pulled out and wired to at least two inspection terminals prepared on the mounting substrate. A method of confirming the COG mounting state of the mounted IC by measuring the resistance value between the inspection terminals is well known. (Patent Document 2)

  However, as a method for confirming the connection state of the above COG mounting, even if the appearance is visually confirmed by a microscope, the degree of indentation is insufficient by the appearance alone, the necessary continuity is taken, the variation in the standard and the appearance by the viewer There is a problem that it is difficult to judge depending on the degree.

  In addition, providing inspection terminals on the mounting board occupies a limited part of the peripheral area, which causes restrictions on other signal wirings and increases the wiring resistance value. As a result, there is a problem in that the display quality is deteriorated or the frame of the panel is widened to prevent it. In addition, when measuring the resistance value by contacting an inspection terminal on a glass substrate with an inspection probe, the inspection terminal may be scratched or needle marks may remain, causing quality defects such as terminal corrosion. There is also a risk of occurrence.

JP 2003-269934 A JP 2004-258131 A

  The present invention has been made to solve the above-described problems. As a mounting inspection method for COG mounting, the resistance of the connection wiring via the driver IC inside and the ACF connection portion is not the appearance but the test terminal on the FPC. It is an object of the present invention to provide a simple pass / fail judgment method based on numerical data based on the measured resistance value without affecting the display panel unit by measuring the value. Furthermore, it aims at shortening working time and improving working efficiency by measuring the said resistance value in the same process as the lighting test after an FPC mounting process.

The liquid crystal display device according to the present invention includes an image display panel having a TFT array substrate, a driver IC mounted on the image display panel, and an FPC that is mounted on the image display panel and supplies signals and power to the driver IC. The driver IC has at least two sets of dummy terminal pads connected to each other in the set, and the TFT array substrate further includes the dummy array pad. One or more sets of COG connection terminal pads are arranged so as to be ACF-connected to the terminal pads and insulated from each other, and a set of inspections arranged on the FPC from the COG connection terminal pads The lead-out wiring is led out through the FPC mounting terminal region to the terminal pad.
The mounting inspection method according to the present invention is characterized in that a COG mounting state is inspected by measuring a resistance value between inspection pads of the set of inspection terminal pads.

A liquid crystal display device capable of determining pass / fail based on quantitative data based on the measured resistance value without affecting the display panel unit by measuring the resistance value of the set of inspection terminal pads, and a mounting inspection method thereof Can provide.
In addition, since it is not necessary to contact the resistance measurement probe with the terminals on the array substrate, a highly reliable liquid crystal display device can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in order to avoid redundant description, elements having the same or corresponding functions in each drawing are denoted by the same reference numerals. Moreover, when the same structure is repeated in the same drawing, the attachment of a code | symbol may be abbreviate | omitted.

Embodiment 1 FIG.
FIG. 1 shows a schematic configuration of a liquid crystal display device according to Embodiment 1. In FIG. 1, one substrate of a liquid crystal panel 1 in which liquid crystal is held between a pair of transparent insulating glass substrates. Three driver ICs 2 are COG mounted on a glass substrate 5 (hereinafter referred to as a TFT array substrate). The driver IC 2 is supplied with a control signal, a video signal, a power source, and the like necessary for driving and controlling the driver IC 2 from a flexible printed circuit board (hereinafter referred to as FPC) 3 via the TFT array substrate 5. The signals and power are supplied from the FPC 3 that is ACF-mounted at the end of the TFT array substrate 5.

  2 is a cross-sectional view taken along the line III-III including the periphery of the driver IC 2 of the liquid crystal display device shown in FIG. The driver IC 2 is disposed on one TFT array substrate 5 and disposed outside (the frame region 50) of the other glass substrate 4 (that is, the opposite substrate) facing the TFT array substrate 5, and is mounted via the ACF 7. Yes. The liquid crystal panel 1 and the FPC 3 are ACF-connected in an FPC mounting terminal region 6 formed at the edge of the TFT array substrate 5 on the driver IC 2 side.

FIG. 3 shows an enlarged plan view of the terminal portions of the driver IC 2 and the FPC 3. On the driver IC 2, a plurality of drive output terminal pad groups 51 for driving the liquid crystal panel 1, and input terminal pad groups 52 such as control signals, video signals, and power supplies necessary for driving and controlling the driver IC 2 are arranged. (Hereinafter, “terminal pad” is referred to as “pad”).
Further, dummy pads 11a and 11b that are not related to the drive circuit built in the driver IC 2 are disposed at the end of the pad group 52 (the lower right end of the driver IC 2). The dummy pads 11a and 11b are connected by a short-circuit wiring (not shown) inside the driver IC2.
In the frame region 50 on the TFT array substrate 5, two COG connection pads 54 are also arranged corresponding to the dummy pads 11 a and 11 b of the driver IC 2. Here, the COG connection pads 54 themselves are independent terminal pads and are insulated from each other. Further, two array lead wires 8 are arranged on the TFT substrate 5 so as to be connected to the COG connection pads 54 and are led out to the FPC mounting terminal region 6. The array lead-out wiring 8 is connected to the FPC connection pad 53 on the TFT array substrate 5.

  In the FPC 3, FPC connection pads 21 a and 21 b are disposed in the FPC mounting terminal area 6 so as to face the two FPC connection pads 53, and two FPC lead wires 9 are provided from the FPC connection pads 21 a and 21 b. Are pulled out and connected to test terminals 31a and 31b arranged at appropriate positions on the FPC 3, respectively. (Hereinafter, the array lead wiring 8 and the FPC lead wiring 9 are collectively referred to as a lead wiring.)

  As is clear from the above description, when the connection from the test terminals 31a to 31b is traced, “test terminal 31a → FPC lead wiring 9 → FPC connection pad 21a → ACF7 → FPC connection pad 53 → array lead wiring 8”. → COG connection pad 54 → ACF 7 → dummy pad 11a → connection wiring of driver IC 2 → dummy pad 11b → ACF 7 → COG connection pad 54 → array lead wiring 8 → FPC connection pad 53 → ACF 7 → FPC connection pad 21b → FPC The lead wires 9 are connected in the order of “test terminal 31a”.

  As described above, the connection from the test terminals 31a to 31b is in a state of being connected through the ACF connection of the FPC-panel connection portion and the ACF connection between the COG-panels, and the resistance values of the test terminals 31a and 31b are set. By measuring, the ACF mounting state at the two locations can be confirmed. That is, when the two ACF connections are not performed well, the measured resistance value is relatively higher than the resistance value when the ACF connection is normally performed. Thus, the state of ACF mounting can be easily confirmed by measuring the resistance values of the test terminals 31a and 31b.

Then, with respect to the liquid crystal display device mounted with COG and FPC, the resistance value between the test pads 31a and 31b is measured by a predetermined quantity, and the liquid crystal display device has no problem in display characteristics and has an appearance on the ACF mounting portion. The indentation state of the conductive particles is good, that is, the numerical distribution represented by the average value and the standard deviation σ of the resistance value of the liquid crystal display device that is normally ACF-connected is quantitatively grasped, and a predetermined value is determined based on the result. The determination of OK / NG in the mounted state is facilitated by providing the determination criterion.
For example, the range of the average value ± 3σ is set to the OK range as the predetermined determination criterion, and if the resistance value between the test terminals 31a and 31b is between the above ranges, it is accepted, and if it is outside the range, it is rejected. As a result, the time required for the inspection of the ACF mounting state can be shortened, the working efficiency is improved, and automation is also easy. In addition, the pass / fail judgment is not performed based on the artificial visual judgment, and the pass / fail judgment is made based on the measured numerical value, so that there is little variation in the pass / fail criteria, and a high-quality liquid crystal display device can be manufactured at low cost.

  Also, by measuring the resistance value checking inspection probe electrically connected to the test terminals 31a and 31b on the FPC 3, the area of the terminal can be reduced compared with the case where the inspection terminal is provided on the TFT array substrate 5. Easy to measure because it can be taken widely. Moreover, even if scratches or marks remain on the test pad on the FPC 3 by the above-described inspection probe, the surface of the test pad can be made a relatively stable metal by applying Au, Ni plating, etc. Less.

As is apparent from FIG. 3, the dummy pads 12a and 12b located at the lower left end of the driver IC 2 are connected to the ACF 7, the COG connection pad 54, the array lead-out wiring 8, and the FPC connection, as between the dummy pads 11a and 11b described above. The pads 53, ACF7, FPC connection pads 22a and 22b, and the FPC lead wiring 9 are connected to the test terminals 32a and 32b, respectively.
The connection wiring from the dummy pads 12a and 12b to the test terminals 32a and 32b is symmetrical with respect to the driver IC 2 so as to face the connection wiring from the dummy pads 11a and 11b to the test terminals 31a and 31b. The detailed description is omitted here.
Further, other dummy pad pairs at the four corners of the driver IC 2 in FIG. 3, 12a and 12b, 13a and 13b, and 14a and 14b are also connected by short-circuit wiring (not shown) inside the IC. Accordingly, as in the case between the dummy pads 11a and 11b described above, the wiring to the remaining dummy pads 13a and 13b, 14a and 14b is led out to the FPC 3 (not shown), and the resistance value is measured as described above to thereby determine the driver IC. You can also check the variation in the mounting state on the mounting surface.

Embodiment 2. FIG.
In the second embodiment, the dummy pads 11a and 11b and 12a and 12b shown in FIG. 3 are short-circuited inside the driver IC 2 as in the first embodiment. Further, in the second embodiment, the dummy pads 11b and 12a respectively disposed at the right end portion and the left end portion of the driver IC 2 are short-circuited by the thin film wiring 15 (shown in FIG. 4) on the TFT array substrate 5. Then, wirings are drawn from the dummy pads 11a and 12b to the test terminals 31a and 32b on the FPC 3 via the FPC connection pads 21a and 22b, respectively, and the resistance value between the test terminals 31a and 32b is measured. As a result, the mounting state of the driver IC 2 in the long side direction can be confirmed with the minimum number of drawers. Since other configurations are the same as those of the first embodiment, detailed description thereof is omitted here.
FIG. 4 is a configuration diagram in which wiring is drawn out from the three driver ICs 2 to the test terminals 31b and 32a on the FPC 3, respectively. With this configuration, wiring is drawn from the TFT array substrate 5 to the FPC 3 in accordance with the short circuit state between the dummy pads in the driver IC 2, and the COG mounting state of the driver IC 2 is determined by measuring the resistance value between the test terminals. It can be easily confirmed.
In the present embodiment, the thin film wiring 15 for connecting the dummy pads of the driver IC 2 is exemplified as the connection wiring disposed on the TFT array substrate 5, but the present embodiment also applies to the connection wiring inside the driver IC 2. The same effect as in the second mode can be obtained.
In the present embodiment, three driver ICs are mounted in the frame region 50. However, the number of driver ICs to be mounted is not particularly limited, and may be one or more.

Embodiment 3 FIG.
FIG. 5 shows an enlarged plan view showing the connection between the driver IC 2 and the FPC 3 in the third embodiment. In the figure, the array lead-out wiring 8 on the TFT array substrate 5 from the dummy pad 11b to the FPC connection pad 21b branches in the middle of the circuit and is a COG connection pad 54 corresponding to the FPC connection pad 21c adjacent to the FPC connection pad 21b. Has been pulled out. The COG connection pad 54 and the FPC connection pad 21c are ACF connected (not shown). Further, the FPC connection pad 21 c is led out to the test terminal 31 c on the FPC 3 by the FPC lead wiring 9. Since other configurations are the same as those of the first embodiment, detailed description thereof is omitted here.

Here, since the array lead-out wiring 8 and the FPC lead-out wiring 9 are formed mainly of a low-resistance metal material such as Cu, most of the resistance values between the test terminals 31b and 31c are the FPC connection pads 21b and This is considered to be a mounting resistance value by ACF connection (not shown) between 21c and two FPC connection pads 53 corresponding thereto.
Here, the FPC connection pad 21a is adjacent to the FPC connection pad 21b, and the mounting resistance value by the ACF connection may be considered to be equivalent to the FPC connection pads 21b and 21c. Therefore, the numerical value obtained by subtracting the resistance value measured between the test terminals 31b and 31c from the resistance value measured between the test terminals 31a and 31b can be regarded as the mounting resistance value due to the ACF mounting of the dummy pads 11a and 11b of the driver IC2. That is, it is possible to confirm the connection state narrowed down to the mounting state of the driver IC 2 mounted with COG. Here, the FPC connection pad 21c may theoretically be in the vicinity of the FPC connection pad 21b or another place if there is no difference in pad size or the like, but the variation in the ACG mounting state depending on the position of the FPC connection pad, TFT Considering the ease of routing the thin film wiring on the array substrate 5, it is desirable that the terminal pads are adjacent as shown in the present embodiment.

Embodiment 4 FIG.
FIG. 6 shows a schematic configuration of the liquid crystal display device according to the fourth embodiment. In FIG. 6, the FPC lead wires 9 arranged between the driver ICs 2 are connected to a chip resistor (0Ω jumper) 51 mounted on the FPC 3, and the array between the driver ICs 2 is provided by the chip resistor 51. The lead wiring 8 and the FPC lead wiring 9 are short-circuited. Regarding the COG connection configuration of the driver IC 2 on the TFT array substrate 5, the thin film wiring connecting the dummy pads at the left and right ends of the driver IC 2, and the connection from the dummy pad to the FPC lead wiring 9, the above-described embodiment Since it is the same as 2, the description is omitted here.

As is apparent from the above description and FIG. 6, the test terminals 41 and 42 are connected via the FPC lead wiring, the array lead wiring, the thin film wiring on the TFT substrate, and the ACF connection. Accordingly, the mounting state of the three driver ICs 2 mounted on the liquid crystal display device is confirmed once by measuring the resistance value between the leftmost test terminal 41 and the rightmost test terminal 42 in the frame region 50. This is possible with resistance measurement.
Furthermore, if the measured resistance value between the test terminals 41 and 42 is high and it is necessary to confirm the mounting state individually in detail, the chip resistor 51 is temporarily removed and the mounting pad used for it is removed. As a resistance value measuring pad, it is possible to grasp the mounting state of the individual driver IC 2 as in the second embodiment.

In the present embodiment, the thin film wiring for connecting the dummy pads of the driver IC 2 is exemplified as the connection wiring disposed on the TFT array substrate 5, but the present embodiment also applies to the connection wiring inside the driver IC 2. 4 can be obtained.
In the present embodiment, there are three driver ICs mounted in the frame region 50. However, the number of driver ICs to be mounted is not particularly limited, and may be two or more.

Embodiment 5 FIG.
FIG. 7 shows a schematic configuration of the liquid crystal display device according to the fifth embodiment. In FIG. 7, the FPC lead wires 9 arranged between the driver ICs 2 are connected to a chip resistor (0Ω jumper) 51 mounted on the FPC 3, and the array between the driver ICs 2 is provided by the chip resistor 51. The lead wiring 8 and the FPC lead wiring 9 are short-circuited. Regarding the COG connection configuration of the driver IC 2 on the TFT array substrate 5, the thin film wiring connecting the dummy pads at the left and right ends of the driver IC 2, and the connection from the dummy pad to the FPC lead wiring 9, the above-described embodiment Since it is the same as 2, the description is omitted here.

  In the fifth embodiment, as shown in FIG. 7, test wiring is drawn from the test terminals 41 and 42 to the input terminal portion 10 of the FPC 3. When inspecting the display state of the liquid crystal display device, a lighting inspection jig is connected to the input terminal portion 10 of the FPC 3, and the liquid crystal display device is actually turned on to perform a desired lighting inspection. If the test wiring drawn out to the input terminal portion 10 in the same process as this process is used to connect to the lighting inspection jig and the resistance value between the test wirings is measured and displayed, the test terminals 41 and 42 are connected. This eliminates the trouble of measuring the resistance value by bringing the probe into contact with the measuring probe, shortening the inspection process time and improving the work efficiency. Further, since it is not necessary to contact the resistance measurement probe with the TFT array substrate of the liquid crystal display device, the influence on the quality is eliminated.

  In the first to fifth embodiments described above, an example of a liquid crystal display device has been described as an image display device. However, the display device is particularly limited to a liquid crystal display device as long as the driver IC is COG mounted on a glass substrate. However, the present invention can be similarly applied to, for example, an EL display device or a PDP display device.

It is a schematic block diagram of the liquid crystal display device in Embodiment 1 and 3 which concerns on this invention. It is sectional drawing of the liquid crystal display device shown in FIG. It is an enlarged plan view showing the connection between driver IC and FPC in Embodiment 1 which concerns on this invention. It is a schematic block diagram of the liquid crystal display device in Embodiment 2 which concerns on this invention. It is an enlarged plan view showing the connection between driver IC and FPC in Embodiment 3 which concerns on this invention. It is a schematic block diagram of the liquid crystal display device in Embodiment 4 which concerns on this invention. It is a schematic block diagram of the liquid crystal display device in Embodiment 5 which concerns on this invention.

Explanation of symbols

2 Driver IC
3 FPC
4 Counter substrate 5 TFT array substrate 6 FPC mounting terminal region 7 ACF (anisotropic conductive film)
8 Array lead wiring 9 FPC lead wiring 10 Input terminal portions 11a, 11b, 12a, 12b, 13a, 13b, 14a, 14b Dummy terminal pad 15 Thin film wiring 21a, 21b, 21c, 22a, 22b FPC connection terminal pads 31a, 31b, 31c, 32a, 32b, 41, 42 Test terminal 51 Chip resistor (0Ω jumper)
52 Input Terminal Pad Group 53 FPC Connection Pad 54 COG Connection Pad

Claims (6)

In an image display device having an image display panel having a TFT array substrate, a driver IC mounted on the image display panel by COG, and an FPC mounted on the image display panel and supplying signals and power to the driver IC,
The driver IC has at least two dummy terminal pads that are connected to each other in at least two as a set,
The TFT array substrate has one or more sets of terminal pads for COG connection disposed so as to be ACF connected to the dummy terminal pads and insulated from each other,
An image display device, wherein a lead-out wiring is led out from the COG connection terminal pad to a set of inspection terminal pads arranged on the FPC through an FPC mounting terminal region. 2. The image display device according to claim 1, wherein a plurality of the driver ICs are mounted on the image display panel, and one set of the dummy terminal pads of the driver IC is arranged on each of left and right ends of the driver IC. Branching out the lead wiring arranged on the TFT array substrate,
2. The image display device according to claim 1, wherein a lead-out wiring is led out through an FPC mounting terminal area to one test terminal pad insulated from the set of test terminal pads. The image display device according to claim 1, wherein the lead-out wiring on the FPC is led to an input terminal portion. The image display device according to any one of claims 1 to 3,
A mounting inspection method for an image display device, wherein a resistance value between the terminal pads of the set of inspection terminal pads is measured to inspect a COG mounting state. The image display device according to claim 4,
A mounting inspection method for an image display device, wherein a lighting inspection jig is connected to the input terminal portion, and a mounting inspection is performed in addition to the lighting inspection of the image display panel.

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