CN113589135A - Method for detecting bonding electrical property of FPC and PCB - Google Patents
Method for detecting bonding electrical property of FPC and PCB Download PDFInfo
- Publication number
- CN113589135A CN113589135A CN202110707487.7A CN202110707487A CN113589135A CN 113589135 A CN113589135 A CN 113589135A CN 202110707487 A CN202110707487 A CN 202110707487A CN 113589135 A CN113589135 A CN 113589135A
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- pin
- bonding
- fpc
- pcb
- test
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Links
- 238000000034 method Methods 0.000 title claims abstract description 13
- 238000012360 testing method Methods 0.000 claims abstract description 42
- 239000000523 sample Substances 0.000 claims abstract description 6
- 239000011521 glass Substances 0.000 claims abstract description 4
- 238000001514 detection method Methods 0.000 claims description 20
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000003292 glue Substances 0.000 claims 1
- 239000002245 particle Substances 0.000 description 3
- 230000000007 visual effect Effects 0.000 description 3
- 238000005422 blasting Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000013102 re-test Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2812—Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2818—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors
Abstract
The invention discloses a method for detecting the bonding electrical property of an FPC and a PCB, which comprises the following steps: establishing an engineering drawing for bonding the PIN by the FPC, and designing a first golden finger corresponding to the PIN according to the specification of the glass; arranging a plurality of impedance test bonding PIN loops with non-display functions in the first golden fingers, wherein the PIN loops electrically connect two adjacent first golden fingers; establishing a PCB bonding PIN engineering drawing, wherein second golden fingers of the PCB bonding PIN correspond to first golden fingers of the FPC bonding PIN in a one-to-one mode, and two ends, corresponding to each impedance test bonding PIN loop, of the second golden fingers are respectively provided with a test pad; bonding the designed and produced FPC and PCB together; applying voltage to a test bonding pad at one end of each impedance test bonding PIN loop by using a probe jig, and testing loop current I of the test bonding pad at the other end; calculating the resistance value R ═ V ÷ I ÷ 2 of a single binding PIN; and judging whether the single bonding PIN is qualified or not according to the calculation result.
Description
Technical Field
The invention relates to the technical field of display screen production and detection, in particular to a method for detecting bonding electrical property of an FPC (flexible printed circuit) and a PCB (printed circuit board).
Background
In the existing liquid crystal display and touch screen industries, the bonding effect of the FPC and the PCB is confirmed by using an AOI (automated Optical inspection) automatic Optical detector and then manually and visually checking the number of gold ball particles on each PIN and the blasting state of the gold ball particles. The bonding PIN number of a general product is about 300PIN, the visual judgment mode has the limitations of large workload and easy misjudgment, and the conduction electrical property of the FPC and PCB bonding cannot be accurately detected.
Therefore, a simple and accurate method for detecting the electrical properties of the FPC and PCB bonding is required to solve the above problems in the prior art.
Disclosure of Invention
Aiming at the problems in the prior art, the invention mainly aims to provide a method for detecting the bonding electrical property of an FPC and a PCB, which realizes simple, convenient and accurate bonding electrical property detection, reduces misjudgment and workload and improves the working efficiency.
The technical scheme of the invention is as follows: the invention provides a method for detecting the bonding electrical property of an FPC and a PCB, which comprises the following steps:
establishing an engineering drawing for bonding the PIN by the FPC, and designing a first golden finger corresponding to the PIN according to the specification of the glass; arranging a plurality of impedance test bonding PIN loops with non-display functions in the first golden fingers, wherein the PIN loops electrically connect two adjacent first golden fingers;
establishing a PCB bonding PIN engineering drawing, wherein a second golden finger of the PCB bonding PIN corresponds to a first golden finger of the FPC bonding PIN in a one-to-one mode, and two ends, corresponding to each PIN loop, of the second golden finger are respectively provided with a test pad;
bonding the designed and produced FPC and PCB together;
applying voltage to the test bonding pad at one end of each PIN loop by using a probe jig, and testing the loop current I of the test bonding pad at the other end;
calculating the resistance value R ═ V ÷ I ÷ 2 of a single binding PIN;
and judging whether the single bonding PIN is qualified or not according to the calculation result.
Further, each PIN loop connects two adjacent first golden fingers together through a metal wire.
Further, the rule for setting a plurality of non-display function impedance test bonding PIN loops comprises: the PIN number is set in 100 or more groups respectively at two ends and in the middle of the FPC; setting a group at two ends of the FPC within 200PIN, and setting 3 groups in the middle; setting a group at two ends of the FPC respectively within 300PIN, and setting 5 groups in the middle; PIN number is above 300PIN, and two groups are respectively arranged at two ends of FPC, and 6-10 groups are arranged in the middle.
And further, judging whether the single bonding PIN is qualified according to the calculation result, wherein if R is less than or equal to 5 ohms, the single bonding PIN is judged to be qualified, and if not, the single bonding PIN is judged to be unqualified.
Furthermore, the FPC and the PCB are bonded together in an ACF (anisotropic conductive film) bonding mode.
Further, the voltage value is controlled below 5V.
And further, establishing an engineering drawing of the FPC bonding PIN and an engineering drawing of the PCB bonding PIN through EDA software.
Further, the method also comprises the step of manually rechecking the single bonding PIN which is not qualified in detection.
By adopting the scheme, the invention provides a method for detecting the bonding electrical property of the FPC and the PCB, which has the following beneficial effects:
(1) by utilizing the electrical property detection method, the PIN loops are arranged on the FPC, the two test pads are arranged on the PCB corresponding to the two ends of each PIN loop, and the resistance value of a single bonding PIN is detected through the two test pads after bonding, so that the detection is convenient and the accuracy is high. The PIN loop and the test pad are simple in formation and only play a detection role, and do not affect functions of the FPC and the PCB.
(2) By adopting the electrical property detection method, the working efficiency is greatly improved, the process of manual visual examination and verification is omitted, and the workload is reduced.
Drawings
FIG. 1 is a schematic diagram of the FPC and PCB of the present invention before bonding.
FIG. 2 is a schematic diagram of the FPC and the PCB after bonding.
Fig. 3 is an enlarged schematic view at M in fig. 1.
Fig. 4 is an enlarged schematic view of fig. 2 at N.
FIG. 5 is a schematic flow chart of the electrical property detection method for FPC and PCB bonding according to the present invention.
Detailed Description
The invention is described in detail below with reference to the accompanying figures 1-5 and specific examples.
The invention provides a method for detecting the bonding electrical property of an FPC and a PCB, which comprises the following steps:
step 1, establishing an engineering drawing for bonding the PIN through the FPC, designing a first golden finger corresponding to the PIN according to the specification of the glass, and establishing the engineering drawing through EDA software in the embodiment. A plurality of impedance test bonding PIN loops with non-display functions are arranged in the first golden fingers, the two adjacent first golden fingers are electrically connected through the PIN loops, and each PIN loop connects the two adjacent first golden fingers together through a metal wire f. The metal wire f can be a copper foil, is only used for connecting and conducting between two first gold fingers, is small in length and has negligible resistance. As shown in fig. 1, A, B, C, D, E, F total of 6 bonding PIN loops are provided in the first gold finger on the FPC. In general, the rules for setting a plurality of non-display function impedance test bonding PIN loops include: the PIN number is within 100, and two groups are respectively arranged at the two ends and the middle of the FPC; the number of PIN is within 200PIN, two ends of the FPC are respectively provided with one group, and the middle of the FPC is provided with 3 groups; the number of PIN is within 300PIN, two ends of the FPC are respectively provided with one group, and the middle of the FPC is provided with 5 groups; the number of PIN is above 300PIN, two groups are respectively arranged at two ends of FPC, and 6-10 groups are arranged in the middle. More groups of bonding PIN loops can be designed according to requirements so as to obtain more accurate bonding electrical property detection results.
And 2, establishing a PCB binding PIN engineering drawing, wherein the engineering drawing is established through EDA software in the embodiment. And the second golden finger of the PCB bonding PIN corresponds to the first golden finger of the FPC bonding PIN in a one-to-one mode. And two ends of the second golden finger corresponding to each PIN loop are respectively provided with a test pad for communicating with external electrical property detection equipment, such as a test probe and the like. As shown in the enlarged view of fig. 3, a1 and a2 are test pads corresponding to two ends of the bonding PIN loop a, B1 and B2 are test pads corresponding to two ends of the bonding PIN loop B, C1 and C2 are test pads corresponding to two ends of the bonding PIN loop C, D1 and D2 are test pads corresponding to two ends of the bonding PIN loop D, E1 and E2 are test pads corresponding to two ends of the bonding PIN loop E, and F1 and F2 are test pads corresponding to two ends of the bonding PIN loop F.
And 3, bonding the designed and produced FPC and PCB together, and bonding the FPC and PCB together by using an ACF (anisotropic conductive film) adhesive bonding mode frequently adopted in the prior art. After the two are bonded, the second gold finger on the PCB and the two test pads are both electrically connected to the bonding PIN loop designed on the FPC, as shown in the enlarged view of fig. 4. Namely: after FPC and PCB bonding, A1 and A2 are respectively through two second golden fingers electric connection to the both ends of bonding PIN return circuit A, B1 and B2 are respectively through two second golden fingers electric connection to the both ends of bonding PIN return circuit B, C1 and C2 are respectively through two second golden fingers electric connection to the both ends of bonding PIN return circuit C, D1 and D2 are respectively through two second golden fingers electric connection to the both ends of bonding PIN return circuit D, E1 and E2 are respectively through two second golden fingers electric connection to the both ends of bonding PIN return circuit E, F1 and F2 are respectively through two second golden fingers electric connection to the both ends of bonding PIN return circuit F.
And 4, applying voltage to the test bonding pad at one end of each impedance test bonding PIN loop by using the probe jig, and testing the loop current I of the test bonding pad at the other end. The voltage is controlled below 5 volts to prevent damage to the bonding PIN circuit due to excessive voltage. That is, the current value I1 at a2 was tested by applying a voltage to a1 using a probe jig, and according to this test method, current values I2, I3, I4, I5, and I6 were measured at B2, C2, D2, E2, and F2 in this order.
Step 5, calculating the resistance value of a single binding PIN according to the formula R ═ V ÷ I ÷ 2, namely: the resistance value R1 of a single bonding PIN on the bonding PIN loop A, the resistance value R2 of the single bonding PIN on the bonding PIN loop B, the resistance value R3 of the single bonding PIN on the bonding PIN loop C, the resistance value R4 of the single bonding PIN on the bonding PIN loop D, the resistance value R5 of the single bonding PIN on the bonding PIN loop E and the resistance value R6 of the single bonding PIN on the bonding PIN loop F are obtained through calculation.
And 6, judging whether the single bonding PIN is qualified or not according to the calculation result, wherein the standard for judging whether the single bonding PIN is qualified or not according to the calculation result is that if R is less than or equal to 5 ohms (set according to the impedance capacity borne by the single PIN of the drive IC), the single bonding PIN is judged to be qualified, and if not, the single bonding PIN is judged to be unqualified.
And 7, manually re-testing the single bonding PIN which is unqualified in detection, for example, using a universal meter or a high-precision resistance tester to perform corresponding one-to-one re-testing to find the problem existing at the unqualified part of the single bonding PIN so as to improve subsequent production.
In summary, the invention designs a plurality of bonding PIN loops on the FPC, designs the test pads corresponding to two ends of each bonding PIN loop on the PCB, and after the FPC is bonded with the PCB, the current detection is performed on each bonding PIN loop through the test pads, so as to accurately obtain the resistance value of a single bonding PIN on the bonding PIN loop, thereby realizing the detection of the bonding electrical performance of the FPC and the PCB. By utilizing the electrical property detection method, the work that the number and the blasting state of gold ball particles on each PIN need to be checked by manual visual checking is omitted, the working intensity is greatly reduced, the working efficiency is improved, the accuracy rate of electrical property detection of the PIN loop is high, and the method is worthy of wide popularization and use.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A method for detecting the electrical property of FPC and PCB bonding is characterized by comprising the following steps:
establishing an engineering drawing for bonding the PIN by the FPC, and designing a first golden finger corresponding to the PIN according to the specification of the glass; arranging a plurality of impedance test bonding PIN loops with non-display functions in the first golden fingers, wherein the PIN loops electrically connect two adjacent first golden fingers;
establishing a PCB bonding PIN engineering drawing, wherein a second golden finger of the PCB bonding PIN corresponds to a first golden finger of the FPC bonding PIN in a one-to-one mode, and two ends, corresponding to each PIN loop, of the second golden finger are respectively provided with a test pad;
bonding the designed and produced FPC and PCB together;
applying voltage to the test bonding pad at one end of each PIN loop by using a probe jig, and testing the loop current I of the test bonding pad at the other end;
calculating the resistance value R ═ V ÷ I ÷ 2 of a single binding PIN;
and judging whether the single bonding PIN is qualified or not according to the calculation result.
2. The electrical performance testing method of claim 1, wherein each PIN loop connects two adjacent first gold fingers together by a metal wire.
3. The electrical performance detection method of claim 1, wherein the rule for setting a plurality of non-display function impedance test bonding PIN loops comprises: the PIN number is set in 100 or more groups respectively at two ends and in the middle of the FPC; setting a group at two ends of the FPC within 200PIN, and setting 3 groups in the middle; setting a group at two ends of the FPC respectively within 300PIN, and setting 5 groups in the middle; PIN number is above 300PIN, and two groups are respectively arranged at two ends of FPC, and 6-10 groups are arranged in the middle.
4. The electrical property detection method of claim 1, wherein the criterion for determining whether a single bonding PIN is acceptable according to the calculation result is that the single bonding PIN is acceptable if R is less than or equal to 5 ohms, and is not acceptable if R is less than or equal to 5 ohms.
5. The electrical property detection method of claim 1, wherein the FPC and PCB are bonded together by means of ACF glue.
6. The electrical property detection method of claim 4, wherein the voltage value is controlled to be below 5V.
7. The electrical property detection method of any one of claims 1 to 6, wherein the engineering drawings of FPC bonding PIN and PCB bonding PIN are established by EDA software.
8. The electrical property testing method of claim 7, further comprising manually reviewing individual bonded PINs that fail the test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110707487.7A CN113589135A (en) | 2021-06-24 | 2021-06-24 | Method for detecting bonding electrical property of FPC and PCB |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110707487.7A CN113589135A (en) | 2021-06-24 | 2021-06-24 | Method for detecting bonding electrical property of FPC and PCB |
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| Publication Number | Publication Date |
|---|---|
| CN113589135A true CN113589135A (en) | 2021-11-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202110707487.7A Pending CN113589135A (en) | 2021-06-24 | 2021-06-24 | Method for detecting bonding electrical property of FPC and PCB |
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070216846A1 (en) * | 2006-03-15 | 2007-09-20 | Au Optronics Corp. | Display circuits |
| JP2009282285A (en) * | 2008-05-22 | 2009-12-03 | Mitsubishi Electric Corp | Image display device and mounting inspection method thereof |
| US20130077005A1 (en) * | 2011-09-22 | 2013-03-28 | Hun-Bae Kim | Liquid crystal display apparatus |
| US20140015563A1 (en) * | 2012-07-13 | 2014-01-16 | Hannstar Display Corp | Trace structure for the touch panel and electrical testing method |
| US20140187088A1 (en) * | 2012-12-27 | 2014-07-03 | Lg Display Co., Ltd. | Display device being possible to detect bonding defect |
| KR20150083572A (en) * | 2014-01-10 | 2015-07-20 | 삼성디스플레이 주식회사 | Driving integrated circuit and method of inspecting mount state of the same |
| US20170083133A1 (en) * | 2015-09-17 | 2017-03-23 | Lg Display Co., Ltd. | Display device and method of measuring contact resistance thereof |
| CN206311727U (en) * | 2016-12-27 | 2017-07-07 | 信利（惠州）智能显示有限公司 | Contactor control device |
| CN207675337U (en) * | 2017-11-29 | 2018-07-31 | 北海星沅电子科技有限公司 | A kind of FPC and PCB pressings test structure |
| CN108594017A (en) * | 2018-07-02 | 2018-09-28 | 京东方科技集团股份有限公司 | A kind of bonding impedance detection system and method |
| US20190116672A1 (en) * | 2017-10-17 | 2019-04-18 | Boe Technology Group Co., Ltd. | Display panel, detection method thereof, flexible printed circuit and display device |
-
2021
- 2021-06-24 CN CN202110707487.7A patent/CN113589135A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070216846A1 (en) * | 2006-03-15 | 2007-09-20 | Au Optronics Corp. | Display circuits |
| JP2009282285A (en) * | 2008-05-22 | 2009-12-03 | Mitsubishi Electric Corp | Image display device and mounting inspection method thereof |
| US20130077005A1 (en) * | 2011-09-22 | 2013-03-28 | Hun-Bae Kim | Liquid crystal display apparatus |
| US20140015563A1 (en) * | 2012-07-13 | 2014-01-16 | Hannstar Display Corp | Trace structure for the touch panel and electrical testing method |
| US20140187088A1 (en) * | 2012-12-27 | 2014-07-03 | Lg Display Co., Ltd. | Display device being possible to detect bonding defect |
| KR20150083572A (en) * | 2014-01-10 | 2015-07-20 | 삼성디스플레이 주식회사 | Driving integrated circuit and method of inspecting mount state of the same |
| US20170083133A1 (en) * | 2015-09-17 | 2017-03-23 | Lg Display Co., Ltd. | Display device and method of measuring contact resistance thereof |
| CN206311727U (en) * | 2016-12-27 | 2017-07-07 | 信利（惠州）智能显示有限公司 | Contactor control device |
| US20190116672A1 (en) * | 2017-10-17 | 2019-04-18 | Boe Technology Group Co., Ltd. | Display panel, detection method thereof, flexible printed circuit and display device |
| CN207675337U (en) * | 2017-11-29 | 2018-07-31 | 北海星沅电子科技有限公司 | A kind of FPC and PCB pressings test structure |
| CN108594017A (en) * | 2018-07-02 | 2018-09-28 | 京东方科技集团股份有限公司 | A kind of bonding impedance detection system and method |
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