CN220252004U - Display panel binding resistance testing device for PIN reduction - Google Patents
Display panel binding resistance testing device for PIN reduction Download PDFInfo
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- CN220252004U CN220252004U CN202321519723.3U CN202321519723U CN220252004U CN 220252004 U CN220252004 U CN 220252004U CN 202321519723 U CN202321519723 U CN 202321519723U CN 220252004 U CN220252004 U CN 220252004U
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- 239000000523 sample Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
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Abstract
The utility model provides a display panel binding resistance testing device for reducing PIN, which comprises a COG binding area component, a FOG binding area component, an FPC test point component, a binding resistance measuring circuit and a resistance measuring meter, wherein the binding resistance measuring circuit is connected with the COG binding area component; the FOG binding area assembly comprises a first resistor, a second resistor and a third resistor, the first end of the COG binding area assembly is connected with one end of the first resistor, the second end of the COG binding area assembly is connected with one ends of the second resistor and the third resistor, the other ends of the first resistor, the second resistor and the third resistor are connected with the FPC test point assembly, the FPC test point assembly is connected with a binding resistance measuring circuit, and the binding resistance measuring circuit is connected with a resistance measuring meter; the binding resistance measuring circuit is configured to reduce errors in actual testing of the display panel. In addition, the design scheme for reducing the PIN of the display panel reserves more space, but has the problems of influencing the FOG and COG binding resistance test of the panel and further influencing the yield of products.
Description
Technical Field
The utility model relates to the technical field of display panel binding resistance test, in particular to a display panel binding resistance test device for reducing PIN.
Background
FOG (FPC on Glass) binding and COG (Chip on Glass) binding are gate-on processes of LCM display screen, FOG is that FPC is directly bound on LCD through ACF (anisotropic conductive film anisotropic conductive film), COG is that IC is directly bound on LCD through ACF (anisotropic conductive film anisotropic conductive film); the binding resistance test value affects the product yield. As the development of ICs is increasingly advanced to small pitch and small gap, the LCM display screen on the market has a design trend of sinking, narrow frame and low cost, so that the formed requirements on COG equipment and COG technology are higher and higher, and more designs for reducing PIN of the display panel are presented, so that a space is reserved for the design of the precision panel, and the production yield can be improved.
Other problems caused by the method are exposed, so that higher requirements are also put on the COG process technology. And simultaneously, higher requirements are also provided for the control and detection method of the COG binding resistance. The design scheme for reducing the PIN of the display panel on the market reserves more space, but after reducing the PIN of the display panel, PINs for binding resistance tests of FOG and COG are correspondingly reduced, so that the binding resistance tests of the FOG and the COG of the panel are affected, and the yield of products is further affected.
In view of this, the present application is presented.
Disclosure of Invention
The utility model discloses a display panel binding resistance testing device for reducing PIN, which can effectively solve the problem that the design scheme for reducing the PIN of a display panel in the prior art reserves more space, but after reducing the PIN of the display panel, PINs for FOG and COG binding resistance tests are correspondingly reduced, so that the FOG and COG binding resistance tests of the panel are affected, and further the product yield is affected.
The utility model discloses a display panel binding resistance testing device for reducing PIN, which comprises a COG binding area component, a FOG binding area component, an FPC test point component, a binding resistance measuring circuit and a resistance measuring meter, wherein the binding resistance measuring circuit is connected with the binding resistance measuring circuit;
the FOG binding area assembly comprises a first resistor, a second resistor and a third resistor, wherein the first end of the COG binding area assembly is electrically connected with one end of the first resistor, the second end of the COG binding area assembly is electrically connected with one end of the second resistor and one end of the third resistor, the other end of the first resistor, the other end of the second resistor and the other end of the third resistor are electrically connected with the FPC test point assembly, the FPC test point assembly is electrically connected with the input end of the binding resistance measuring circuit, and the output end of the binding resistance measuring circuit is electrically connected with the resistance measuring meter;
the binding resistance measuring circuit is configured to reduce errors in actual testing of the display panel.
Preferably, the COG binding region assembly includes a fourth resistor and a fifth resistor, wherein one end of the fourth resistor is electrically connected to one end of the fifth resistor, the other end of the fourth resistor is electrically connected to one end of the first resistor, and the other end of the fifth resistor is electrically connected to one end of the second resistor and one end of the third resistor.
Preferably, the FPC test point assembly includes a first test point, a second test point, and a third test point, where the other end of the first resistor is electrically connected to the first test point, the other end of the second resistor is electrically connected to the second test point, the other end of the third resistor is electrically connected to the third test point, and the first test point, the second test point, and the third test point are respectively electrically connected to the input end of the binding resistance measurement circuit.
Preferably, the binding resistance measuring circuit comprises a first measuring circuit and a second measuring circuit, wherein one end of the FPC test point component is electrically connected with the first end of the first measuring circuit and the first end of the second measuring circuit, the second end of the first measuring circuit is electrically connected with the first positive electrode of the resistance measuring meter, the second end of the second measuring circuit is electrically connected with the second positive electrode of the resistance measuring meter, the third end of the first measuring circuit is electrically connected with the first negative electrode of the resistance measuring meter, the third end of the second measuring circuit is electrically connected with the second negative electrode of the resistance measuring meter, and the fourth end of the first measuring circuit and the fourth end of the second measuring circuit are electrically connected with the other end of the FPC test point component.
Preferably, the first measurement circuit includes a sixth resistor and a seventh resistor, wherein one end of the FPC test point assembly is electrically connected with one end of the sixth resistor, the other end of the sixth resistor is electrically connected with the first positive electrode of the resistance measurement meter, the first negative electrode of the resistance measurement meter is electrically connected with one end of the seventh resistor, and the other end of the seventh resistor is electrically connected with the other end of the FPC test point assembly.
Preferably, the second measurement circuit includes an eighth resistor and a ninth resistor, wherein one end of the FPC test point assembly is electrically connected with one end of the eighth resistor, the other end of the eighth resistor is electrically connected with a second positive electrode of the resistance measurement meter, a second negative electrode of the resistance measurement meter is electrically connected with one end of the ninth resistor, and the other end of the ninth resistor is electrically connected with the other end of the FPC test point assembly.
Preferably, the resistance measurement meter is a universal meter.
In summary, the display panel binding resistance testing device for reducing PIN provided in this embodiment calculates a single PAD binding resistance by testing the resistance of the COG/FOG reserved test point, and records and manages the resistance; referring to the binding resistance measuring method, the DUT reserves two ends of a test point for the FOG/COG, and the COG and the FOG separately test and record data. Therefore, the intelligent housekeeping equipment in the prior art is only stopped at the surface function, the function is single, the safety of families cannot be really guaranteed, meanwhile, the intelligent housekeeping equipment on the market is high in cost, the price is generally high, a set of intelligent housekeeping equipment with comprehensive functions is difficult to be equipped in an ordinary family, the crowd used by the intelligent housekeeping equipment is limited, and the popularization of the intelligent housekeeping equipment is blocked.
Drawings
Fig. 1 is a schematic circuit diagram of a PIN-reduced display panel binding resistance testing device according to a first aspect of the present utility model.
Fig. 2 is a schematic circuit diagram of a display panel binding resistance testing device for reducing PIN according to a second aspect of the present utility model.
Fig. 3 is a schematic diagram of a conventional COG and FOG binding region provided by an embodiment of the present utility model.
FIG. 4 is a schematic diagram of conventional probe measurement according to an embodiment of the present utility model.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments. All other embodiments, based on the embodiments of the utility model, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the utility model. Thus, the following detailed description of the embodiments of the utility model, as presented in the figures, is not intended to limit the scope of the utility model, as claimed, but is merely representative of selected embodiments of the utility model. All other embodiments, based on the embodiments of the utility model, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the utility model.
Specific embodiments of the present utility model will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1 to 2, a first embodiment of the present utility model provides a PIN-reduced display panel binding resistance testing device, which includes a COG binding area assembly, a FOG binding area assembly, an FPC test point assembly, a binding resistance measuring circuit, and a resistance measuring table;
the FOG binding area component comprises a first resistor R1, a second resistor R2 and a third resistor R3, wherein a first end of the COG binding area component is electrically connected with one end of the first resistor R1, a second end of the COG binding area component is electrically connected with one end of the second resistor R2 and one end of the third resistor R3, the other end of the first resistor R1, the other end of the second resistor R2 and the other end of the third resistor R3 are electrically connected with the FPC test point component, the FPC test point component is electrically connected with the input end of the binding resistance measuring circuit, and the output end of the binding resistance measuring circuit is electrically connected with the resistance measuring table;
the binding resistance measuring circuit is configured to reduce errors in actual testing of the display panel.
In this embodiment, the COG binding region assembly includes a fourth resistor R4 and a fifth resistor R5, where one end of the fourth resistor R4 is electrically connected to one end of the fifth resistor R5, the other end of the fourth resistor R4 is electrically connected to one end of the first resistor R1, and the other end of the fifth resistor R5 is electrically connected to one end of the second resistor R2 and one end of the third resistor R3.
In this embodiment, the FPC test point assembly includes a first test C1 point, a second test point C2F1, and a third test point F2, where the other end of the first resistor R1 is electrically connected to the first test point C1, the other end of the second resistor R2 is electrically connected to the second test point C2F1, the other end of the third resistor R3 is electrically connected to the third test point F2, and the first test point C1, the second test point C2F1, and the third test point F2 are respectively electrically connected to the input end DUT of the binding resistance measurement circuit.
The design scheme for reducing the PIN of the display panel on the market reserves more space, but after reducing the PIN of the display panel, PINs for binding resistance tests of FOG and COG are correspondingly reduced, so that the binding resistance tests of the FOG and the COG of the panel are affected, and further the product quality is affected.
Specifically, in this embodiment, the conventional COG and FOG binding areas are shown in fig. 3, and the display panel binding resistance testing device for reducing PIN adopts panel COG binding and FOG binding test PAD designs to test the points C1, C2, F1 and F2 respectively; the test point C2 and the test point F1 test PAD to share a test point, namely the second test point C2F1, and each group reduces one PIN design; two or more sets of binding impedance tests PAD for the panel design are shown in fig. 1. The COG binding resistance measures the first test point C1 and the second test point C2F1, and the FOG binding resistance measures the second test point C2F1 and the third test point F2; because of the common PIN, the test resistance error is smaller and more accurate. Wherein, the binding resistance value of the FOG single PAD is approximately equal to (the measured values of the second test point C2F1 and the third test point F2-b)/2, and the binding resistance value of the cog single PAD is approximately equal to (the measured values of the first test point C1 and the second test point C2F 1-b—fog single PAD 2-C)/2. Wherein a is the internal conduction resistance of the chip in FIG. 1, b is the Panel ITO resistance in FIG. 1, c is the FPC wire resistance in FIG. 1, and infinity is near 0 and can be ignored.
In one possible embodiment of the utility model, the resistance measurement meter may be a universal meter.
Specifically, in the present embodiment, the multimeter is also called a multiplex meter, a multimeter, a three-purpose meter, a propagation meter, etc., which is an indispensable measuring meter for the power electronics, etc., and generally has the main purpose of measuring voltage, current, and resistance. The multimeter is divided into a pointer multimeter and a digital multimeter according to a display mode. The multifunctional measuring instrument with multiple measuring ranges is a common universal meter which can measure direct current, direct current voltage, alternating current, alternating voltage, resistance, audio level and the like, and can also measure alternating current, capacitance, inductance, some parameters (such as beta) of a semiconductor and the like. It should be noted that, in other embodiments, other types of resistance meters may be used, and these embodiments are not limited in detail herein, but are within the scope of the present utility model.
In one possible embodiment of the present utility model, the binding resistance measurement circuit includes a first measurement circuit, and a second measurement circuit, where one end of the FPC test point assembly is electrically connected to a first end of the first measurement circuit and a first end of the second measurement circuit, a second end of the first measurement circuit is electrically connected to a first positive electrode s+ of the resistance measurement meter, a second end of the second measurement circuit is electrically connected to a second positive electrode m+ of the resistance measurement meter, a third end of the first measurement circuit is electrically connected to a first negative electrode S-of the resistance measurement meter, a third end of the second measurement circuit is electrically connected to a second negative electrode M-of the resistance measurement meter, and a fourth end of the first measurement circuit and a fourth end of the second measurement circuit are electrically connected to another end of the FPC test point assembly.
In this embodiment, the first measurement circuit includes a sixth resistor R6 and a seventh resistor R7, where one end of the FPC test point assembly is electrically connected to one end of the sixth resistor R6, the other end of the sixth resistor R6 is electrically connected to the first positive electrode s+ of the resistance measurement meter, the first negative electrode S-of the resistance measurement meter is electrically connected to one end of the seventh resistor R7, and the other end of the seventh resistor R7 is electrically connected to the other end of the FPC test point assembly.
In this embodiment, the second measurement circuit includes an eighth resistor R8 and a ninth resistor R9, where one end of the FPC test point assembly is electrically connected to one end of the eighth resistor R8, the other end of the eighth resistor R8 is electrically connected to a second positive electrode m+ of the resistance measurement meter, a second negative electrode M-of the resistance measurement meter is electrically connected to one end of the ninth resistor R9, and the other end of the ninth resistor R9 is electrically connected to the other end of the FPC test point assembly.
Specifically, in this embodiment, since the resistance value of binding the COG binding region element and the FOG binding region element may be smaller, in the measurement of the resistance value smaller, the conventional measurement method is to wire a probe, as shown in fig. 4; the closer the sum of r1 and r2 in fig. 4, i.e. the value of the test wire is to the resistance value of the DUT, i.e. the resistance value actually tested by COG or FOG, the larger the measurement error, so the display panel binding resistance value testing device for reducing PIN adopts a method of punching two wires by a probe. Referring to fig. 2, in which rmeas=v/a=rdut, because im+=im (-0), VMEAS (-VDUT) is not affected by r6+r7 and r8+r9, a method of using a probe to make two lines is adopted to connect the FPC test point components together, i.e. to measure the resistance of COG or FOG for actual test together, so as to reduce test errors.
In summary, the display panel binding resistance testing device for reducing PIN calculates a single PAD binding resistance by testing the resistance of the COG/FOG reserved test point, and records and manages the resistance; referring to the binding resistance measuring method, the DUT reserves two ends of a test point for the FOG/COG, and the COG and the FOG separately test and record data. And (3) accurately testing and controlling the COG/FOG resistance while reserving more space in the pitch-reducing design.
The above is only a preferred embodiment of the present utility model, and the protection scope of the present utility model is not limited to the above examples, and all technical solutions belonging to the concept of the present utility model belong to the protection scope of the present utility model.
Claims (7)
1. The display panel binding resistance testing device for reducing PIN is characterized by comprising a COG binding area component, a FOG binding area component, an FPC test point component, a binding resistance measuring circuit and a resistance measuring meter;
the FOG binding area assembly comprises a first resistor, a second resistor and a third resistor, wherein the first end of the COG binding area assembly is electrically connected with one end of the first resistor, the second end of the COG binding area assembly is electrically connected with one end of the second resistor and one end of the third resistor, the other end of the first resistor, the other end of the second resistor and the other end of the third resistor are electrically connected with the FPC test point assembly, the FPC test point assembly is electrically connected with the input end of the binding resistance measuring circuit, and the output end of the binding resistance measuring circuit is electrically connected with the resistance measuring meter;
the binding resistance measuring circuit is configured to reduce errors in actual testing of the display panel.
2. The PIN-down display panel binding resistance testing device according to claim 1, wherein the COG binding region assembly comprises a fourth resistor and a fifth resistor, wherein one end of the fourth resistor is electrically connected with one end of the fifth resistor, the other end of the fourth resistor is electrically connected with one end of the first resistor, and the other end of the fifth resistor is electrically connected with one end of the second resistor and one end of the third resistor.
3. The PIN-reducing display panel binding resistance testing device according to claim 1, wherein the FPC test point assembly comprises a first test point, a second test point and a third test point, wherein the other end of the first resistor is electrically connected with the first test point, the other end of the second resistor is electrically connected with the second test point, the other end of the third resistor is electrically connected with the third test point, and the first test point, the second test point and the third test point are respectively electrically connected with the input end of the binding resistance measuring circuit.
4. The PIN-down display panel binding resistance testing device according to claim 1, wherein the binding resistance measuring circuit comprises a first measuring circuit and a second measuring circuit, wherein one end of the FPC test point assembly is electrically connected with the first end of the first measuring circuit and the first end of the second measuring circuit, the second end of the first measuring circuit is electrically connected with the first positive electrode of the resistance measuring meter, the second end of the second measuring circuit is electrically connected with the second positive electrode of the resistance measuring meter, the third end of the first measuring circuit is electrically connected with the first negative electrode of the resistance measuring meter, the third end of the second measuring circuit is electrically connected with the second negative electrode of the resistance measuring meter, and the fourth end of the first measuring circuit and the fourth end of the second measuring circuit are electrically connected with the other end of the FPC test point assembly.
5. The PIN-down display panel binding resistance testing device according to claim 4, wherein the first measuring circuit comprises a sixth resistor and a seventh resistor, wherein one end of the FPC test point assembly is electrically connected with one end of the sixth resistor, the other end of the sixth resistor is electrically connected with the first positive electrode of the resistance measuring meter, the first negative electrode of the resistance measuring meter is electrically connected with one end of the seventh resistor, and the other end of the seventh resistor is electrically connected with the other end of the FPC test point assembly.
6. The PIN-down display panel binding resistance testing device according to claim 4, wherein the second measuring circuit comprises an eighth resistor and a ninth resistor, wherein one end of the FPC test point assembly is electrically connected with one end of the eighth resistor, the other end of the eighth resistor is electrically connected with a second positive electrode of the resistance measuring meter, a second negative electrode of the resistance measuring meter is electrically connected with one end of the ninth resistor, and the other end of the ninth resistor is electrically connected with the other end of the FPC test point assembly.
7. The PIN-down display panel binding resistance testing device according to claim 1, wherein the resistance measuring meter is a universal meter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321519723.3U CN220252004U (en) | 2023-06-15 | 2023-06-15 | Display panel binding resistance testing device for PIN reduction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321519723.3U CN220252004U (en) | 2023-06-15 | 2023-06-15 | Display panel binding resistance testing device for PIN reduction |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220252004U true CN220252004U (en) | 2023-12-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321519723.3U Active CN220252004U (en) | 2023-06-15 | 2023-06-15 | Display panel binding resistance testing device for PIN reduction |
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| Country | Link |
|---|---|
| CN (1) | CN220252004U (en) |
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2023
- 2023-06-15 CN CN202321519723.3U patent/CN220252004U/en active Active
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