JP2009279252A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine which can prevent a malfunction in lamp actuation without increasing the control burden of a control apparatus even if the number of lamps to be actuated increases. <P>SOLUTION: A lamp actuation circuit LAMP drives and turns on a total of N*M lamps by outputting N-bits of common data COMi and M-bits of lighting data Pj to lamps. The lamp drive circuit LAMP has a driver Dr which receives a serial signal containing lighting data and common data which a sub control part outputs, an abnormality detection circuit G1 which detects the abnormality of output data when outputting the serial signal received by the driver Dr, and an operation prohibiting circuit G2 which brings the N*M lamps into a non-lighting state by controlling the driver Dr based on the output signal of the abnormality detector G1. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a gaming machine having a computer circuit, and more particularly to a gaming machine that enables powerful lamp effects while suppressing wasteful power consumption.

  A ball and ball game machine such as a pachinko machine has a symbol start port provided on the game board, a symbol display unit for displaying a series of symbol variation modes such as stopping a plurality of display symbols after varying a predetermined time, and an opening / closing plate It is configured with a grand prize opening that opens and closes. When the detection switch provided at the symbol start port detects the passing of the game ball, the game ball is in a winning state and the symbol display unit changes the display symbol for a predetermined time. After that, when the symbol stops in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a profit state advantageous to the player.

  The symbol display unit is usually composed of a liquid crystal display, and executes various symbol effect operations including a reach effect, a notice effect, and a jackpot effect. Reach production is a design production that continues to be a big hit state in one step and excites the player, and notice production is a sudden appearance of some character in the middle of the movement of the design, It is a design effect that warns of a big hit. The jackpot effect is an effect executed in a big hit state, and a more flashy symbol effect is executed in response to the joy of the player.

  At the time of execution of such a symbol effect, an audio effect and a lamp effect are also executed in synchronism with this, and at the time of a reach effect and a big hit effect, a lamp is flashed in response to the symbol effect on the liquid crystal display. Also, after entering the big hit state, a more flashy lamp effect is executed. An LED lamp, an incandescent lamp, or the like is used as an effect lighting lamp. In addition, a dot matrix may be configured by aligning a plurality of lamps vertically and horizontally.

  In any case, when N * M lamps are arranged, these are selectively driven by a lamp driving circuit that outputs N-bit common data and M-bit lighting data. Is customary. In general, a driver IC incorporating a shift register and a latch register is used for the lamp driving circuit. The shift register receives lighting data and common data from the control device as serial signals, and receives the data through the latch register. By outputting, N * M lamps are driven.

  Here, the N-bit common data is data that determines whether or not M lamps are driven to be lit. Only when the common data is at a significant level, the M lamps are M-bit lighting data. It is turned on or off according to the level. When N * M lamps are dynamically lit, only one bit of the N-bit common data is configured to have a significant level.

  By the way, since the gaming machine is in a considerably poor noise environment, the serial signal transmitted to the driver IC is garbled especially when the transmission path of the serial signal is long or the transmission speed of the serial signal is high. There are things to do. In such an abnormal state, even if it is temporary, a meaningless lamp effect that is not intended is executed, which causes distrust to the player.

  Therefore, in order to cope with such a situation, it is conceivable to repeatedly drive N * M lamps at a high speed. For example, in order to draw a dot matrix screen composed of N * M lamps 60 times per second, N bits of common data and M bits are generated at a cycle of 1 / (N * 60) seconds. It is necessary to transmit a serial signal including the lighting data to the driver IC. For example, if N = 8 bits, the data transmission cycle is about 2 mS, and each lamp is driven to the same state 60 cycles per second at a cycle of 2 * N [mS]. Therefore, even if part of the drawing data is garbled, there is no problem as a whole due to the relationship between human vision and the lamp lighting cycle.

  However, since the control device needs to transmit common data and lighting data as serial signals to the driver IC, there is a problem that the transmission processing burden of the control device increases when the number of lamps to be lit is increased. is there. That is, the control device needs to repeatedly execute serial data transmission processing at a cycle of 1 / (N * 60) seconds, and therefore the burden is not light when the number of ramps (= N * M) increases. Although it is possible to increase the transmission speed of serial data, if the transmission speed is increased unnecessarily, noise resistance further deteriorates.

  The present invention has been made in view of the above problems, and provides a gaming machine capable of preventing malfunction of lamp driving without increasing the control burden of the control device even when the number of lamps to be driven increases. The task is to do.

  In order to achieve the above object, according to the first aspect of the present invention, when a predetermined winning state related to the player's movement occurs, a gaming state advantageous to the player is generated based on a winning / raising lottery resulting therefrom. A gaming machine, comprising: a main control unit that comprehensively controls gaming operations including the success / failure lottery; and a sub-control unit that realizes individual control operations based on control commands from the main control unit The main control unit or the sub-control unit outputs a driving unit that drives a total of N * M lamps by outputting M-bit lighting data and N-bit common data to the lamp. A data receiving circuit for receiving a serial signal including the lighting data and the common data, an abnormality detecting circuit for detecting an abnormality in output data when the serial signal received by the data receiving circuit is output, Based on the output signal of the abnormality detecting circuit controls the data receiving circuit and is configured to have, the operation prohibition circuit for the N * M number of lamps in the non-lighting state.

  In the present invention, the drive unit determines whether the serial signal is garbled, and the lamp is not turned on in the event of an abnormality. Therefore, the main control unit and sub-control unit can take a longer transmission cycle of the serial signal, and control accordingly. The burden is reduced. In addition, since the transmission speed of the serial signal can be reduced by the longer transmission period, the noise resistance is increased by that amount. That is, serial data having a wider pulse width has higher resistance to spike noise and the like than a narrow pulse width. If the number of common data is the same, the average brightness of each lamp that is dynamically lit is not related to the transmission cycle.

  The lamp of the present invention is typically an electric lamp such as an LED lamp or an incandescent lamp, but includes a lamp constituting a light emitter such as a dot matrix.

  The abnormality detection circuit of the present invention may detect an abnormality of output data based on the common data output from the data receiving circuit, or output data other than the common data output from the data receiving circuit. Based on the above, an abnormality in the output data may be detected.

  In addition, a signal line connecting the data receiving circuit and the main control unit or the sub control unit, a serial signal including the lighting data and common data, a clock signal synchronized with the output timing of the serial signal, 4 lines for transmitting a latch signal for instructing the data receiving circuit to hold the serial signal in the internal register and a control signal for instructing the data receiving circuit to output the data held in the register It consists of Such a configuration with a small number of wires is preferable in that the occupied space is not large even when the distance to the control unit is long. Although it is easily affected by noise as long as the wiring distance is long, even if garbled bits occur, the operation prohibiting circuit functions in the present invention, so that the player does not feel uncomfortable. In addition, since a situation in which all the lamps are erroneously turned on due to bit corruption does not occur, it is possible to prevent the data receiving circuit from being deteriorated without meaning.

  The data receiving circuit is typically configured by connecting a plurality of ICs each including a shift register and a latch register in series. The anomaly detection circuit preferably operates in response to an output signal from an IC that should output N-bit common data. In this case, the abnormality detection circuit is typically composed of an AND circuit that determines abnormality when a plurality of bits of the N-bit common data are at a level that enables the lamp to be lit. The input / output of the AND circuit may be configured with positive logic or negative logic.

  On the other hand, the operation prohibiting circuit is preferably configured to prohibit the output operation of the IC that should output the N-bit common data, or to prohibit the output operation of the IC that should output the M-bit lighting data. . Note that if the data receiving circuit is configured with an open collector type output circuit or a three-state type output circuit, control for prohibiting the output operation is easy.

  The invention according to claim 11 is a gaming machine that, when a predetermined winning state related to the player's action is generated, generates a gaming state advantageous to the player based on the winning / notting lottery resulting therefrom. A main control unit that comprehensively controls gaming operations including the winning / failing lottery, and a sub-control unit that realizes individual control operations based on control commands from the main control unit, The control unit or sub-control unit is configured to output a serial signal including N-bit common data, M-bit lighting data, and K-bit inspection data set to the first level. By outputting data and N-bit common data to the lamp, a driving unit that drives and drives a total of N * M lamps includes a shift register that receives all the serial signals, and the shift register A latch register that receives the data transfer from and holds the serial signal. When the latch register outputs the held data, all or part of the inspection data is not at the first level. It is configured to determine and grasp the occurrence of communication abnormality.

  According to the present invention described above, even if the number of lamps to be driven increases, it is possible to prevent malfunction of the lamp driving circuit without increasing the control burden of the control device.

  Hereinafter, embodiments of the present invention will be described in detail. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 not from the back side but from the front side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be freely opened and closed. The portion excluding the game board 5 corresponds to the main body frame of the present invention.

  On the outer periphery of the glass door 6, a large number of electric lamps such as LED lamps are arranged in a substantially C shape. An upper plate 8 for storing game balls for launch is mounted on the front plate 7, and a lower plate 9 for storing game balls overflowing from or extracted from the upper plate 8 and a launch handle 10 are mounted at the bottom of the front frame 3. And are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, the game board 5 is provided with a guide rail 13 formed of a metal outer rail and an inner rail in an annular shape, and a liquid crystal color display DISP is provided at the approximate center of the game area 5a inside. Is arranged. In addition, at a suitable place in the game area 5a, a symbol starting port 15, a big winning port 16, a plurality of normal winning ports 17 (four on the right and left sides of the big winning port 16), and a gate 18 serving as two passing ports are arranged. Has been. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The liquid crystal display DISP is a device that variably displays a specific symbol related to a big hit state and displays a background image and various characters in an animated manner. This liquid crystal display DISP has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. And, in the special symbol display parts Da to Dc, a reach effect is executed that expects a big hit state to be invited, or in the special symbol display parts Da to Dc and the surroundings, a notice effect that informs the result of the success / failure is executed. Is done.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time, and the lottery extracted at the time when the game ball passes through the gate 18 is extracted. The stop symbol determined by the random number for use is displayed and stopped.

  For example, the symbol start opening 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws 15a, and when the stop symbol after fluctuation of the normal symbol display unit 19 is a winning symbol, the opening and closing claws are displayed. 15a is released only for a predetermined time or until a predetermined number of game balls are detected.

  When a game ball wins the symbol start port 15, the display symbols of the special symbol display portions Da to Dc change for a predetermined time and are determined based on the lottery result corresponding to the winning timing of the game ball to the symbol start port 15. Stop at the stop symbol. In addition, in special symbol display parts Da-Dc and its circumference, a notice effect may be performed between a series of symbol effects.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward, but when the stop symbol after the symbol change of the special symbol display portions Da to Dc is a big hit symbol such as “777”, the “big hit game” Is started, and the opening / closing plate 16a is opened.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol of the special symbols, a privilege that the game after the end of the special game is in a high probability state is given.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM of the present embodiment. A one-dot broken line arrow in the figure mainly indicates a DC voltage line.

  As shown in the figure, this pachinko machine GM includes a power supply board 20 that receives AC 24V and outputs various DC voltages, a system reset signal SYS, etc., a main control board 21 that plays a central role in game control operations, and a main control board. An effect control board 22 that executes a lamp effect and a sound effect based on the control command CMD received from the control board 21; a liquid crystal control board 23 that drives the liquid crystal display DISP based on the control command CMD ′ received from the effect control board 22; Based on a control command CMD "received from the main control board 21, a payout control board 24 for controlling the payout motor M to pay out the game ball, and a launch control board 25 for firing the game ball in response to the player's operation, , It is structured around.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. Further, the control command CMD ′ output from the effect control board 22 is transmitted to the liquid crystal control board 23 via the effect interface board 27, and the control command CMD ″ output from the main control board 21 is set to the main board relay board 28. Is transmitted to the payout control board 24. The effect interface board 27 and the effect control board 22 are directly connected by a connector without using a cable.

  The main control board 21, the effect control board 22, the liquid crystal control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Accordingly, the circuits mounted on the control boards 21 to 24 and the operations realized by the circuits are collectively referred to as a function. In this specification, the main control unit 21, the effect control unit 22, and the liquid crystal control unit 23 are used. , And the payout control unit 24. All or part of the effect control unit 22, the liquid crystal control unit 23, and the payout control unit 24 is a sub-control unit.

  By the way, the pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member GM1 is the panel side member GM2.

  3, the frame side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, a frame relay board 32, an external terminal board OT, and a ball lending machine UT. Interface board IF, and these circuit boards are respectively fixed at appropriate positions of the front frame 3. On the other hand, on the back of the game board 5, a main control board 21, an effect control board 22, and a liquid crystal control board 23 are fixed together with a liquid crystal display DISP and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors CN1-CN4 concentratedly arranged in one place.

  As shown in FIG. 3, the power supply board 20 is connected to the main board relay board 28 through the connection connector CN2, and is connected to the power supply relay board 30 through the connection connector CN3. The main board relay board 28 outputs the system reset signal SYS, the RAM clear signal, the voltage drop signal, the backup power supply, DC12V, and DC32V received from the power board 20 to the main controller 21 as they are. Similarly, the power supply relay board 30 also outputs the system reset signal SYS received from the power supply board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The production interface board 27 outputs the received system reset signal SYS to the production control unit 22 and the liquid crystal control unit 23 as they are.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and receives the same system reset signal SYS, RAM clear signal, voltage drop signal, backup power supply as the main control unit 21 receives. Directly with other power supply voltages.

  Here, the system reset signal SYS output from the power supply board 20 is a signal indicating that the AC power supply 24V is supplied to the power supply board 20, and the one-chip microcomputer or other IC element of each of the control units 21 to 24 by this signal. The power is reset. The RAM clear signal received from the power supply board 20 by the main control unit 21 and the payout control unit 24 is a signal that determines whether or not to initialize all areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. Thus, it has a value corresponding to the ON / OFF state of the initialization switch operated by the staff.

  The voltage drop signal received from the power supply board 20 by the main control unit 21 and the payout control unit 24 is a signal indicating that the AC power supply 24V has started to drop. By receiving this voltage drop signal, each control unit 21, In 24, a necessary termination process is started prior to a power failure or business termination. The backup power source is a DC 5V DC power source that retains data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power source 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 24 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  On the other hand, the effect control unit 22 and the liquid crystal control unit 23 are not provided with the power supply backup function described above. However, the system reset signal SYS is commonly supplied to the effect control unit 22 and the liquid crystal control unit 23, and the power reset operation is realized at a timing substantially synchronized with the other control units 21 and 24.

  As shown in FIGS. 3 and 4, the effect interface board 27 includes a command relay board 26, a power supply relay board 30, a frame relay board 31, an effect control board 22, a lamp connection board 34, and a liquid crystal control board 23. Are connected to the inverter board 33.

  As shown in FIG. 4, the effect control unit 22 includes a one-chip microcomputer 40 that executes processing such as sound effects, lamp effects, and data transfer, an EPROM 41 that stores a control program for the one-chip microcomputer 40, and the one-chip microcomputer. 40, an audio reproduction LSI 42 that generates an audio signal based on an instruction from 40, an audio memory (phrase ROM) 43 that stores compressed audio data that is the original data of the generated audio signal, and a watchdog timer WDT. Configured.

  The one-chip microcomputer 40 includes a serial communication circuit SIO and a parallel port PIO. In this embodiment, serial data DATA and shift clock CLOCK are output from serial communication circuit SIO, and latch signal LATCH and operation control signal ENABLE are output from parallel port PIO. Further, a control command CMD ′ and a strobe signal STB ′ are also output from the parallel port PIO.

  The watchdog timer WDT is reset by a clear pulse periodically supplied from the one-chip microcomputer 40. When the clear pulse is interrupted due to a program runaway or the like, a reset signal RESET is output. As a result, the one-chip microcomputer 40 is forcibly reset to the initial state, and the program runaway state is solved.

  As shown in FIG. 4, the control command CMD and the strobe signal (interrupt signal) STB output from the main control board 21 are sent to the one-chip microcomputer 40 of the presentation control board 22 via the buffer 48 of the presentation interface board 27. Have been supplied. Then, the effect control unit 22 acquires the control command CMD by the reception interrupt process activated by the strobe signal STB. In addition to (a) error notification and other notification control commands, the control command CMD acquired by the effect control unit 22 includes (b) control for specifying an outline of various effect operations resulting from winning at the symbol start opening. Commands (variation pattern commands) are included. Here, the outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end, and the result of winning or failing in the big hit lottery. In addition to these, the change pattern command including the presence or absence of the reach effect or the notice effect may be specified, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the effect control unit 22 acquires the variation pattern command CMD, the effect lottery is subsequently performed, and the effect outline specified by the acquired variation pattern command is further specified. For example, the specific contents of the reach effect and the notice effect are determined. Then, in accordance with the determined specific game content, a lamp effect by blinking LED lamps or the like and a sound effect preparation operation by a speaker are performed, and an effect operation by a lamp or speaker is performed on the liquid crystal control unit 23. A control command CMD ′ relating to the synchronized symbol effect is output.

  In this case, the effect control unit 22 outputs a control command CMD ′ to the effect interface board 27 together with the strobe signal (interrupt signal) STB ′ for the liquid crystal control unit 23. In addition, when receiving the notification control command or other control command related to the liquid crystal display, the effect control unit 22 outputs the control command as it is to the effect interface board 27 together with the interrupt signal STB ′.

  Corresponding to the configuration of the effect control board 22, the effect interface board 27 is configured to receive an 8-bit control command CMD ′ and a 1-bit interrupt signal STB ′. These data CMD ′ and STB ′ are output to the liquid crystal control board 23 as they are via the buffer circuit 45.

  In addition, the effect interface board 27 receives the lamp driving control signals (DATA, CLOCK, ENABLE, LATCH) output from the effect control unit 22 and outputs them via the buffer circuit 46. The lamp drive control signal output from the effect interface board 27 is supplied to the LED lamp group via the lamp connection board 34. As a result, a lamp effect corresponding to the control command CMD output from the main control unit 21 is realized. The

  FIG. 5 is a circuit diagram showing a connection relationship between the lamp driving circuit LAMP mounted on the lamp connection board 34 and the LED lamp group. The lamp driving circuit LAMP functions by receiving the serial signal DATA, the latch signal LATCH, the serial clock CLOCK, and the operation control signal ENABLE from the one-chip microcomputer 40 of the effect control unit 22.

  The ramp control circuit LAMP includes drivers Dr1 and Dr2 that incorporate shift registers and latch registers, a transistor array ARY that amplifies the output signal of the driver Dr1, and a first gate that detects an abnormality in the output level of the driver Dr1. G1 and a second gate G2 that prohibits the output operation of the drivers Dr1 and Dr2 according to the output of the first gate G1.

  In this embodiment, the transistor array ARY is composed of four transistors Q1 to Q4 and four sets of voltage dividing resistors r1 and r2 that define the base potentials of the transistors Q1 to Q4. Each of the transistors Q1 to Q4 has an emitter terminal connected to the power supply voltage Vcc, and is turned on when the voltage dividing resistor r2 receives a ground level input signal. When the transistors Q1 to Q4 are turned on, a drive current flows from the collector terminal toward the LED lamp group.

  In this embodiment, N * M (= 4 * 10) LED lamps are driven to light using two drivers Dr1 and Dr2. The N * M LED lamps are connected so as to be driven by common data COM1 to COMn in the column direction and lighting data P1 to Pm in the row direction (here, n = 4, m = 10).

  Specifically, the common data COMi in the i-th column is connected in common to the anode terminals of ten LED lamps in the row direction. The cathode terminals of the ten LED lamps are connected to the output terminal (10 bits) of the driver Dr2 via ten current limiting resistors R ... R.

  On the other hand, the other side (right side) of the current limiting resistor R is commonly connected to the cathode terminals of the four LED lamps in the column direction. The anode terminals of the four LED lamps are connected to the output terminal (4 bits) of the driver Dr1 via transistors (current amplification elements) Q1 to Q4.

  FIG. 6 shows an internal circuit of the drivers Dr1 and Dr2. In this embodiment, BD7851FP, which is a 16-bit constant current LED driver manufactured by ROHM, is used. As illustrated, the serial signal DATA received from the one-chip microcomputer 40 of the effect control unit 22 is supplied to the 16-bit shift register via the S_IN terminal, and is shifted in synchronization with the shift clock CLOCK. And the serial signal which passed through the shift register is output from the S_OUT terminal.

  The serial signal DATA input to the shift register is acquired by the 16-bit latch register at the timing when the latch signal LATCH rises to H level. When the latch signal LATCH returns to L level, the acquired value of the latch register Is retained. The acquired value of the latch register is output as it is from the output terminals OUT1 to OUT16 if the operation control signal ENABLE is at L level. However, if the operation control signal ENABLE is at the H level, all of the open collector type output gate arrays are released.

  This IC is provided with a current limiting terminal R_Iref, and the output current value can be limited by an external resistor connected to this terminal R_Iref. Therefore, in this IC, an overcurrent that damages the internal circuit does not flow, but an unintended lamp effect is executed due to a garbled bit of common data or lighting data, or a current exceeding the design value flows. The function cannot prevent it.

  The serial signals DATA are connected in series to the two drivers Dr1 and Dr2 shown in FIG. 5, and the S_OUT terminal of the upstream driver Dr1 and the S_IN terminal of the downstream driver Dr2 are connected. On the other hand, the latch signal LATCH and the serial clock CLOCK are connected in parallel to the two drivers Dr1 and Dr2, and realize operations synchronized with each other.

  Continuing the description of the lamp driving circuit LAMP shown in FIG. 5, the 4-bit output terminals OUT1 to OUT4 of the driver Dr1 are connected to the transistor array ARY. The other output terminals OUT5 to OUT16 are not used. As described above, the output section of the driver is an open collector type. However, if the output data OUTi is at L level, for example, the corresponding transistor Qi is turned on, so that the common data COMi is at H level. When the common data COMi becomes the H level, the ten LED lamps arranged in the i-th column can be turned on.

  On the other hand, the 10-bit outputs OUT1 to OUT10 of the driver Dr2 are supplied in common to the cathode terminals of the four LED lamps as lighting data. Accordingly, the ten LED lamps in the i-th row are turned on or off based on the lighting data P1 to P10 output from the output terminals OUT1 to OUT10 of the driver Dr2. For example, if the lighting data Pj is L level, the LED lamp located in j row i column is turned on, and if the lighting data Pk is H level, the LED lamp located in k row i column is turned off.

  Incidentally, the first gate G1 is a NOR gate that receives the two output data OUT1 and OUT2 of the driver Dr1. When the two output data OUT1 and OUT2 are both at the L level, it functions as an abnormality detection circuit that outputs an H level abnormality signal ER. In other words, this abnormality detection circuit is composed of an AND gate having a negative logic input and a positive logic output.

  On the other hand, the second gate G2 is an OR gate that receives the output of the first gate G1 and the operation control signal ENABLE output from the one-chip microcomputer 40. Therefore, when any of the input signals of the second gate G2 is at H level, the output of the second gate G2 is at H level. Since the H level output of the second gate G2 is supplied to the ENABLE terminal of the driver Dr2, when the output of the second gate G2 is at the H level, all the output gate trains of the driver Dr2 are released. . Therefore, the second gate G2 functions as an operation prohibiting circuit that prohibits the output operation of the driver Dr2. That is, when the output of the second gate becomes H level, all the LED lamps are forcibly turned off.

  FIG. 8A is a flowchart for explaining a lamp driving process executed by the effect control unit 22, and is executed by the one-chip microcomputer 40. The operation of the effect control unit 22 includes a main process (not shown) that is started when the CPU is reset, and a reception interrupt process (not shown) that is started when the control command CMD is received from the main control unit 21. And a timer interrupt process shown in FIG. 8A and a transmission completion interrupt shown in FIG. 8B.

  In this embodiment, the timer interrupt processing (FIG. 8A) is activated every 20 mS and operates the serial communication circuit SIO to transmit a series of serial signals to the lamp driving circuit LAMP. On the other hand, the transmission completion interrupt (FIG. 8B) is activated when the serial communication circuit SIO finishes a series of serial signal transmission processing.

  In this embodiment, the lamp driving process is realized by the timer interrupt process and the transmission completion interrupt process. Since the timer interrupt is started every 20 mS, for example, 4 bits of common data and 10 bits of lighting data are transmitted every 20 mS in order to drive 4 * 10 LED lamps. Each LED lamp is driven every 20 * 4 = 80 mS. Therefore, for example, assuming a dot matrix with 4 * 10 LED lamps, the dot matrix surface is drawn at a frequency of 12.5 times per second.

  As will be described later, in this embodiment, since the lighting operation is prohibited when bit corruption is detected, a considerably slower drawing speed can be adopted as described above compared to the conventional example, and the effect control unit 22 The control burden is greatly reduced. As a result, the production control unit 22 can enrich control operations other than the lamp production, and more advanced production operations are possible.

  Further, in this embodiment, the communication speed of serial communication can be reduced as much as the drawing speed is slow, so that the noise resistance is excellent because the pulse width of serial data is wide. That is, even when serial data with a narrow pulse width is buried in spike noise, there is a possibility that the serial data has a wider pulse width and is saved.

  FIG. 8C shows a lighting pattern table TBL that defines the lighting pattern of the lamp. The lighting pattern table TBL is divided into a plurality of groups. Here, the lighting data P1 corresponds to the common data COM1 to COM4 of (0001) (0010) (0100) (1000) as the lighting patterns of each group. Four sets of P10 are prepared. However, the data of each group does not necessarily need to be four sets corresponding to the common data COM1 to COM4, and may be an integer multiple of 4 according to the repetition period of the lighting pattern. When an irregular lamp effect is executed, it is not always necessary to set an integral multiple of the common data COM1 to COM4.

  In any case, it is determined on the basis of a control command CMD received by the effect control unit 22 from the main control unit 21 which data group belonging to the plurality of groups is to be used.

  As described above, the drivers Dr1 and Dr2 incorporate a 16-bit length shift register and a 16-bit length latch register, so that the lighting pattern table TBL includes 16 * 2 = 32-bit pattern data. Is remembered. In this embodiment, only 4-bit common data COM1 to COM4 and 10-bit lighting data P1 to P10 are used, so that “0” is assigned to unused bits. However, in the embodiment shown in FIG. 5, these unused bit data may not be used by the drivers Dr1 and Dr2, and may be “1”. On the other hand, in the embodiment shown in FIG. 9, since unused bit data (OUT5, etc.) is utilized in the driver Dr1, it must be “0”.

  As shown in FIG. 8C, here, the pattern data of each group includes the common data COM4 to COM1 of (0001), (0010), (0100), and (1000), and the lighting data P10 to P1. There are also 4 sets. Thus, since any one bit of the 4-bit common data COM4 to COM1 is “1”, the LED lamp groups in the first to fourth columns shown in FIG. Only 10 LED lamps in a row are driven to light.

  Based on the above, the lamp driving process will be described. As shown in FIG. 8A, when a timer interrupt occurs, first, 32-bit data to be output from the lighting pattern table TBL is selected (ST1). Which of the plurality of groups the pattern data belonging to has been determined has already been determined based on the control command CMD output from the main control unit 21, so that in the process of step ST1, it belongs to the selected group. Which line of pattern data is to be output is determined. In the case of the illustrated example in which only four rows of pattern data exist in the selected group, the four rows of pattern data are repeatedly output.

  If the process of step ST1 is completed, next, the one-chip microcomputer 40 activates the serial communication circuit SIO in a state where the 32-bit serial data DATA is specified and ends the timer interrupt process (ST2). Since the serial communication circuit SIO transmits serial data every 8 bits, the process of step ST2 is actually quite complicated and the control burden is not light. However, here, for convenience of explanation, a 32-bit serial signal DATA including 10-bit lighting data P1 to P10 and 4-bit common data COM1 to COM4 is sent from the serial communication circuit SIO to the drivers Dr1 and Dr2 ( It is automatically transmitted to the lamp driving circuit LAMP).

  Accordingly, the serial communication circuit SIO transmits the 32-bit serial data DATA instructed from the one-chip microcomputer 40 to the lamp driving circuit LAMP in synchronization with the shift clock CLOCK, and when this transmission process is completed, the one-chip A transmission completion interrupt is generated in the microcomputer 40.

  Then, when a transmission completion interrupt occurs, a transmission completion interrupt process shown in FIG. 8B is executed. Here, the one-chip microcomputer 40 first raises the operation control signal ENABLE to H level (ST3). As a result, in the drivers Dr1 and Dr2 of the lamp driving circuit LAMP, the open collector type output terminals are opened, and all the LED lamps are turned off.

  Next, the one-chip microcomputer 40 outputs a LATCH pulse (ST4). Specifically, the LATCH signal is raised to H level and then returned to L level. As a result, in the drivers Dr1 and Dr2, the data of the built-in 16-bit shift register is transferred to the latch register. However, at this timing, since the operation control signal ENABLE is at the H level, all the LED lamps remain in the non-lighted state.

  Next, the one-chip microcomputer 40 lowers the operation control signal ENABLE to L level, and ends the transmission completion interrupt process (ST5). As a result of the operation, 32-bit data serially transferred from the serial communication circuit SIO to the drivers Dr1 and Dr2 is output toward the LED lamp after the process of step ST2. However, based on the circuit configuration of FIG. 5, only 4-bit common data COM1 to COM4 and 10-bit lighting data P1 to P10 are actually output. Then, the ten LED lamps belonging to the i-th column selected by the L level common data COMi are turned on or off based on the lighting data P1 to P10.

  Under normal operating conditions, it functions as described above. However, the serial signal may be garbled in a bad noise environment. FIG. 5B illustrates the operation at the time of such an abnormality. Among the output signals OUT1 to OUT4 that are alternatively at a significant level, both the output signals OUT1 and OUT2 are L level due to bit corruption. The case is assumed. In such a case, the two LED lamps in the column direction are all in an ON operation enabled state, but the total ON current of the two LED lamps is defined by the power supply voltage Vcc and the current limiting resistor R (Vcc Since −Vf) / R, no particular problem occurs in this sense. Vf is a forward voltage drop of the LED lamp (light emitting diode), and the original ON current [= (Vcc−Vf) / R] of the LED lamp is set to about 100 mA.

  On the other hand, when the outputs OUT1 and OUT2 of the driver Dr1 are both abnormally low, there is a concern that the lighting data P1 to P10 are naturally garbled. Then, if a meaningless lamp effect is executed due to the garbled lighting data Pj, the player is not distrusted.

  Further, for example, when all of OUT1 to OUT4 are at the L level, a collector current of about 100 mA flows through the output transistor (open collector type output unit) of the driver Dr2, respectively. The driver Dr2 is deteriorated to some extent due to a large current. If such an abnormality is repeated at a considerable frequency, not only the player's distrust is raised, but also the deterioration of the driver Dr2 is promoted by meaningless heat generation.

  However, in this embodiment, when the common data COM1 and COM2 are both garbled to the L level, the output of the first gate G1 changes to the H level, so this H level output passes through the second gate G2. Then, it is supplied to the ENABLE terminal of the driver Dr2. When the ENABLE terminal changes to H level, the output transistors (open collector type) of the driver Dr2 are all released, so that the current flowing into the driver Dr2 is blocked and all the LED lamps are turned off. The harmful effects are eliminated at once. The abnormal signal ER at the H level returns to the L level when normal data is output in the next timer interrupt process.

  By the way, the circuit configuration of the first gate G1 is such that all output transistors of the drivers Dr1 and Dr2 are released even when any 3 bits or 2 bits of the 4 bits of common data COM1 to COM4 are garbled. May be changed. That is, instead of a single NOR gate G1, an H level abnormal signal ER is output when any 2 bits or any 3 bits of the 4-bit output terminals OUT1 to OUT4 are at L level. Of course, a logic circuit may be provided.

  FIG. 9A is a circuit diagram showing the lamp driving circuit LAMP of the second embodiment. Here, the abnormality detection circuit G1 is configured by the transistor Q that performs an inverter (NOT) operation and the detection resistor RL. As shown, the output signal of the output terminal OUT5 of the driver Dr1 is supplied to the base terminal of the transistor Q via the resistor r2. Also in the second embodiment, since the lighting pattern table TBL shown in FIG. 8B is used, an H level signal should be output from the output terminal OUT5.

  However, when the common data COM1 to COM4 and the lighting data P1 to P10 are garbled, an L level signal garbled from the output terminal OUT5 may be output. When such an abnormality occurs, the abnormality detection circuit G1 outputs an abnormal signal ER of H level, which is supplied to the ENABLE terminal of the driver Dr2 via the second gate G2, so that the output transistor of the driver Dr2 is in an open state. Thus, the inflow current to the driver Dr2 is blocked and all the LED lamps are turned off.

  In order to avoid a sensitive abnormality detection operation, as shown in the modified circuit example of FIG. 9B, among the output terminals OUT1 to OUT6 of the driver Dr1, for example, common data is output from the output terminals OUT2 to OUT5. While outputting COM1 to COM4, the NOR output of the output signals of the output terminals OUT1 and OUT6 may be used as the abnormal signal ER.

  In this case, since the first and last bits of the series of serial signals output from the output terminal OUT1 to the output terminal OUT6 of the driver Dr1 are garbled, the common data COM1 to COM4 and the lighting data P1 to P10 are displayed. However, all the LED lamps are turned off in anticipation of being fatally bit.

  By the way, although the embodiment in which the two drivers Dr1 and Dr2 are connected in series has been described in FIGS. 5 and 9, it is needless to say that three or more drivers may be connected in series as shown in FIG. In the case of the third embodiment, by increasing the lighting data Pi, it is possible to enrich the effect contents of the lamp effect. In the configuration of FIG. 10, the common data COMj can be increased up to a maximum of 16 bits, so the number of lamps that can be driven is a maximum of 16 * 16 * 3 = 768. Such a configuration is suitable for forming a dot matrix.

  FIG. 11 is a circuit diagram showing a lamp driving circuit LAMP using another driver IC (for example, TC74HC595AP manufactured by TOSHIBA) as the most upstream driver Dr1 that outputs the common data COM1 to COM4. The internal configuration of the driver IC is as shown in FIG. 7, and the serial signal DATA received from the one-chip microcomputer 40 of the effect control unit 22 is supplied to the 8-bit length shift register via the SI terminal. Shift is performed in synchronization with the shift clock SCK. The serial signal that has passed through the shift register is output from the QH ′ terminal.

  The serial signal DATA input to the shift register is acquired by the 8-bit latch register at the timing when the latch clock signal RCK rises to H level, and when the latch clock signal RCK returns to L level, The acquired value is retained. The acquired value of the latch register is output as it is from the output terminals QA to AH if the operation control signal G bar is at L level. However, if the operation control signal G bar is at the H level, all the three-state output gate arrays are in a high impedance state.

  Further, this driver IC is provided with a clear terminal SCLR, and when an L level voltage is applied thereto, all outputs of the 8-bit shift register become L level. The clear data is acquired by the 8-bit latch register at the timing when the latch clock signal RCK rises to the H level. If the operation control signal G bar is at the L level at this timing, the clear data is output as it is. Output from terminals QA to AH.

  As the abnormality detection circuit, here, a NAND gate GT that outputs an L level abnormality signal ER when both the output terminals QA and QB of the driver Dr1 are at the H level is used. Further, four inverter circuits are arranged in the previous stage of the transistor array ARY. The inverter circuit is indicated by a logical symbol. Specifically, for example, a switching circuit using an NPN transistor is employed.

  In any case, in this circuit, if the output terminals QA to QD of the driver Dr1 are at the H level, the transistors Q1 to Q4 are turned on, and conversely if the outputs of the output terminals QA to QD are at the L level. The transistors Q1 to Q4 are turned off. Note that the transistors Q1 to Q4 are in the OFF state even when the output terminals QA to QD of the driver Dr1 are in a high impedance state.

  As described above, in the circuit of FIG. 11, the operation logic is reversed by the inverter circuit corresponding to the internal configuration of the driver Dr1 (see FIG. 7). Therefore, the lighting pattern table TBL of FIG. 12B is the same as the configuration of FIG. 8C except that the common data COM is 8 bits long.

  FIG. 12A is a flowchart for explaining the processing contents of the effect control unit 22 for the lamp driving circuit LAMP of FIG. The processes of steps ST11 to ST12 and steps ST13 to ST15 are substantially the same as the processes of steps ST1 to ST5 in FIG. However, in the fourth embodiment, following the step ST15, the latch clock signal RCK is output again (ST16). Therefore, the contents of the latch registers of the drivers Dr1 to Dr4 are output twice in succession in synchronization with the latch clock signal RCK.

  However, if there is no change in the contents of the latch register between step ST14 and step ST16, no change occurs in the output values from the drivers Dr1 to Dr4. That is, after the operation control signal (G bar output or ENABLE output) is returned from the H level to the L level (ST15) and the internal data is output from the drivers Dr1 to Dr4, the internal circuits of the drivers Dr1 to Dr4 must not change. For example, step ST16 has no meaning.

  However, when the outputs of the output terminals QA and QB of the driver Dr1 are both at the H level due to the influence of noise or the like, the NAND gate GT is at the falling timing of the operation control signal G bar to the L level (ST15). Becomes an L level. Since the output of the NAND gate GT is supplied to the clear terminal SCLR of the driver Dr1, all the data of the shift register built in the driver Dr1 is cleared to the L level at the timing of step ST15.

  Since this clear data is output in synchronization with the next latch clock signal RCK (ST16), abnormal common data COM1 to COM4 are prevented from being output in advance. Also in the circuit of FIG. 12, as shown in FIG. 9, a configuration may be adopted in which an abnormal signal ER is output using unused bits. Since unused bits are inherently L level traps, if an H level signal is output from here, it is in a garbled state, and as such, it is expected that other output terminals will also be garbled. Is as described above.

  As mentioned above, although embodiment of this invention was described concretely, the concrete description content does not specifically limit this invention. For example, it is needless to say that the control command is transmitted through the route from the main control unit 21 to the effect control unit 22, and the effect control unit 22 is not limited to the configuration for controlling the LED lamp group. In particular, when a dot matrix is constituted by a plurality of light emitters, it is preferable to execute a lamp control operation by arranging a dedicated CPU circuit (dot control circuit). In this case, the dot control circuit is typically arranged on the downstream side of the effect control unit.

  In any case, when the configuration in which the dot matrix is driven to be lit is used, the present invention is preferable because the player's attention is higher than the case of a simple decoration lamp. In addition, a complicated and sophisticated lamp effect using a dot matrix is possible without increasing the control burden on the main control unit 21 and the effect control unit 22.

It is a perspective view of the pachinko machine shown in an embodiment. It is the front view which illustrated in detail the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a block diagram which shows the circuit structure of an effect control part, an effect interface part, and a liquid-crystal control part. It is a circuit diagram which shows the connection relation of the lamp drive circuit LAMP and LED lamp group of 1st Example. 2 illustrates an internal configuration of a driver IC. The internal configuration of another driver IC is illustrated. It is a flowchart explaining the operation | movement content of a lamp drive process. It is a circuit diagram which shows the connection relation of the lamp drive circuit LAMP and LED lamp group of 2nd Example. It is a circuit diagram which shows the lamp drive circuit LAMP of 3rd Example. It is a circuit diagram which shows the lamp drive circuit LAMP of 4th Example. It is a flowchart explaining the operation | movement content of the lamp drive process of 4th Example.

Explanation of symbols

21 Main control unit 22 Sub control units COM1 to COM4 Common data P1 to P10 Lighting data LAMP Drive units Dr1 to Dr2 Data reception circuit G1 Abnormality detection circuit G2 Operation prohibition circuit

Claims (11)

A gaming machine that generates a gaming state that is advantageous to a player based on a winning or failing lottery resulting from the occurrence of a predetermined winning state related to the player's action, and controls the gaming operation including the winning or failing lottery A main control unit that automatically controls, and a sub-control unit that realizes an individual control operation based on a control command from the main control unit,
By outputting N-bit common data and M-bit lighting data to the lamp, a driving unit that drives and drives a total of N * M lamps,
A data receiving circuit for receiving a serial signal including the lighting data and the common data output by the main control unit or the sub-control unit;
When outputting the serial signal received by the data receiving circuit, an abnormality detection circuit for detecting an abnormality in output data;
An operation prohibiting circuit for controlling the data receiving circuit based on an output signal of the abnormality detecting circuit to turn off the N * M lamps;
A gaming machine characterized by having a structure.   The gaming machine according to claim 1, wherein the abnormality detection circuit detects an abnormality of output data based on the common data output from the data reception circuit.   The gaming machine according to claim 1, wherein the abnormality detection circuit detects an abnormality in output data based on output data other than the common data and the lighting data output from the data receiving circuit. A signal line connecting the data receiving circuit and the main control unit or the sub control unit is:
A serial signal including the lighting data and common data;
A clock signal synchronized with the output timing of the serial signal;
A latch signal for instructing the data receiving circuit to hold the serial signal in an internal register;
The gaming machine according to any one of claims 1 to 3, comprising four control signals that transmit a control signal that instructs the data receiving circuit to output the data held in the register. The data receiving circuit is configured by connecting a plurality of ICs each including a shift register and a latch register in series,
The gaming machine according to claim 1, wherein the abnormality detection circuit operates in response to an output signal of an IC that should output N-bit common data.   The gaming machine according to claim 5, wherein the abnormality detection circuit is configured by an AND circuit that determines an abnormality when a plurality of bits of the N-bit common data are at a level that enables the lamp to be lit. The data receiving circuit is configured by connecting a plurality of ICs each including a shift register and a latch register in series,
The gaming machine according to claim 1, wherein the operation prohibiting circuit is configured to prohibit an output operation of an IC that should output N-bit common data. The data receiving circuit is configured by connecting a plurality of ICs each including a shift register and a latch register in series,
The gaming machine according to claim 1, wherein the operation prohibiting circuit is configured to prohibit an output operation of an IC that should output M-bit lighting data.   The gaming machine according to any one of claims 1 to 8, wherein the data receiving circuit includes an open collector type output circuit.   The gaming machine according to any one of claims 1 to 8, wherein the data receiving circuit includes a three-state output circuit. A gaming machine that generates a gaming state that is advantageous to a player based on a winning or failing lottery resulting from the occurrence of a predetermined winning state related to the player's action, and controls the gaming operation including the winning or failing lottery A main control unit that automatically controls, and a sub-control unit that realizes an individual control operation based on a control command from the main control unit,
The main control unit or sub-control unit is configured to output a serial signal including N-bit common data, M-bit lighting data, and K-bit inspection data set to the first level,
By driving M-bit lighting data and N-bit common data to the lamp, a driving unit for driving a total of N * M lamps is driven by a shift register that receives all the serial signals, and the shift register A latch register that receives the data transfer and holds the serial signal,
A gaming machine configured to determine that all or a part of the inspection data is not at the first level and grasp the occurrence of a communication abnormality when the latch register outputs retained data.