JP5607313B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP5607313B2
JP5607313B2 JP2009090886A JP2009090886A JP5607313B2 JP 5607313 B2 JP5607313 B2 JP 5607313B2 JP 2009090886 A JP2009090886 A JP 2009090886A JP 2009090886 A JP2009090886 A JP 2009090886A JP 5607313 B2 JP5607313 B2 JP 5607313B2
Authority
JP
Japan
Prior art keywords
display
mode
drive
drive data
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009090886A
Other languages
Japanese (ja)
Other versions
JP2010240091A5 (en
JP2010240091A (en
Inventor
大一 永井
健一 土屋
勇治 荒井
正之 反町
利幸 天野
博史 小川
Original Assignee
ルネサスエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ルネサスエレクトロニクス株式会社 filed Critical ルネサスエレクトロニクス株式会社
Priority to JP2009090886A priority Critical patent/JP5607313B2/en
Publication of JP2010240091A publication Critical patent/JP2010240091A/en
Publication of JP2010240091A5 publication Critical patent/JP2010240091A5/en
Application granted granted Critical
Publication of JP5607313B2 publication Critical patent/JP5607313B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Description

  The present invention relates to a control system for driving and controlling a large number of controlled parts relatively distant from a control part via a serial interface, and further to a semiconductor device used for light emission driving of a display element, for example, a gaming machine such as a pachinko machine or a slot machine The present invention relates to a technology that is effective when applied to illumination control.
In illumination control of gaming machines such as pachinko machines and slot machines, a large number of controlled boards with LEDs and their display drivers are arranged on a relatively large board surface of the gaming machine, and display commands or display commands are sent from the control board to these display drivers. Serial transfer is used to provide display drive data. This is because the wiring between the controlled substrate and the control substrate can be reduced as compared with the parallel transfer. At this time, if display drivers or display drive data are supplied in a shift register format by connecting display drivers of a plurality of control boards in series via a serial bus, the display commands or display drive data for some display drivers can be rewritten. Even if it exists, it must be accompanied by retransfer of the display command or display drive data with respect to the whole display driver. Therefore, in order to improve the transfer efficiency of display commands or display drive data, a technique for serially transferring display commands or display drive data by an addressing method has been adopted. Patent Document 1 describes that an I 2 C method is adopted for inter-substrate wiring. This employs a bus drive system in which the bus master performs open drain drive for serial signal lines. Address information specifying the display driver is added to the display command, and the display driver specified by the address information displays the display. A command format for receiving and processing commands and display drive data is adopted. Patent Document 2 is similar to the above, but adopts a push-pull drive format as a drive format for the serial signal line to improve noise resistance.
JP 2008-220409 A JP 2006-218137 A
The I 2 C method for serial transfer by open drain drive is a method used for wiring in a substrate and is weak against noise. The operation margin on the input side for the signal line driven by open drain is only the threshold voltage of the input transistor. In particular, in the case of an industry subject to the restriction that the wiring route and the number of the board surface of the gaming machine must be made visible from the viewpoint of fraud prevention, even shield wiring cannot be used for inter-board wiring, and noise resistance is reduced. In Patent Document 1 using low serial transfer, there is a high risk of malfunction due to data corruption. On the other hand, since Patent Document 2 adopts a push-pull drive format as a drive format for the serial signal line, noise resistance is improved. However, the data format of serial transfer is based on a bit number different from a byte (8 bits) or a word (16 bits) which is a general data processing unit in microcomputer control. Is not suitable, and it is not suitable for reducing the cost of software as well as hardware for display drive control.
  Also, the command and drive data transmission method by addressing can improve the efficiency of rewriting commands and drive data for some display drivers compared to the transmission by shift register method. When the command is rewritten or when the display drive data of a plurality of display elements is rewritten, the processing time becomes longer in proportion to the number of target display drivers and drive data registers. In addition, in order to facilitate the creation of software for amusement illumination display control, the present inventor has the utility of incorporating a function that can be turned on and off without rewriting display data into the display command. It was found by.
  An object of the present invention is suitable for microcomputer control in that the data format of serial transfer is adapted to a general data processing unit by microcomputer control, and reduces the cost of software as well as hardware for display drive control. Another object of the present invention is to provide a drive control system that can contribute, and a semiconductor device suitable for driving a controlled element in the drive control system.
  Another object of the present invention is to provide a drive control system that can efficiently supply not only a part of drivers and drive data registers but also a large number of drivers and a supply of drive data to a large number of drive data registers, and further its drive An object of the present invention is to provide a semiconductor device suitable for receiving a control command in a control system.
  Still another object of the present invention is to provide a drive control system that can contribute to facilitating the creation of software for control of a large number of controlled elements, and is suitable for driving controlled elements in the drive control system. It is to provide a semiconductor device.
  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
  The following is a brief description of an outline of typical inventions disclosed in the present application.
  (1) When interfacing a plurality of controlled elements having a plurality of display elements and a display driver for driving the display elements to emit light, and a control unit having a microcomputer for driving and controlling the display driver, via a serial bus, The serial bus includes a serial signal line, a clock signal line for transmitting a synchronous clock signal output from the microcomputer, and a strobe signal line for transmitting a strobe signal output from the microcomputer. The microcomputer serially outputs a display control command to the serial signal line in synchronization with the synchronous clock signal, and changes the strobe signal in synchronization with the output start timing. The display driver starts taking in a display control command in response to the change in the strobe signal, and when the address information thereby designates its own address, the display driver is designated by the element designation information acquired from the display control command. Display control specified by the mode information acquired from the display control command is performed on the display element using necessary drive data.
  Since the capture timing of the display control command can be obtained by the strobe signal, it is not necessary to add a start bit or the like to the display control command. In this respect, it is easy to adapt the data format of serial transfer to a data processing unit such as a general byte by microcomputer control.
  (2) Further, an instruction bit for burst mode is added to the control command, and the driver is instructed to write data by sequentially supplying drive data to the drive data registers of the plurality of display elements by designating the burst mode. By adopting the burst mode, it is possible to improve the efficiency of supplying drive data not only to some drive data registers but also to a large number of drive data registers.
  (3) Further, the control command adds address mask information for validating a collective designation in which the lower address bits are common regardless of the state of the predetermined upper plural bits of the address information. By using an address mask, it is possible to efficiently supply control commands not only to some drivers but also to many drivers.
  (4) Furthermore, the display modes that can be instructed by the control command are diversified, and the operation such as light emission by writing drive data, light emission by writing drive data, light emission by existing drive data, light extinction while leaving the existing drive data as it is Can be specified with a command. The diversification of display modes facilitates creation of software for controlling a large number of controlled elements.
  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
  That is, it is suitable for microcomputer control in that the data format of serial transfer is adapted to a general data processing unit by microcomputer control, and can contribute to cost reduction of software as well as hardware for display drive control. .
FIG. 1 is a block diagram showing an LED light emission drive control system as an example of a drive control system according to the present invention. FIG. 2 is a block diagram schematically illustrating the configuration of the microcomputer. FIG. 3 is a block diagram schematically illustrating the configuration of the display driver. FIG. 4 is an explanatory diagram illustrating the data format in the normal mode of the display control command. FIG. 5 is an explanatory diagram illustrating a data format in the burst mode of the display control command. FIG. 6 is an explanatory diagram showing an example of a specific data format of the display control command. FIG. 7 is an explanatory view exemplifying a state in which the board surface of the display area is divided into blocks A, B, C, and D. FIG. 8A is an explanatory diagram illustrating a control mode during normal operation as a display control mode on the board of FIG. FIG. 8B is an explanatory view exemplifying a control mode when a “hit” occurs as a display control mode on the board surface of FIG. 7. FIG. 9 is a timing chart illustrating timing waveforms of the strobe signal SS, serial data TxD1, and serial clock SCK1.
1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.
  [1] A drive control system according to a typical embodiment of the present invention includes a plurality of display elements (23, 24, 25) and a plurality of display drivers (20, 21, 22) for driving the display elements to emit light. Controllable part (3, 4, 5), serial bus (2) to which the display driver of the controlled part is commonly connected, and a microcomputer (10) for driving and controlling the display driver, and the serial And a control unit (1) connected to the bus. The serial bus includes a serial signal line (2A), a clock signal line (2B) for transmitting a synchronous clock signal output from the microcomputer, and a strobe signal line (2C) for transmitting a strobe signal output from the microcomputer. The microcomputer serially outputs a display control command to the serial signal line in synchronization with the synchronous clock signal, and changes the strobe signal in synchronization with the output start timing. The display control command includes address information (A0 to A5) for designating the display driver, mode information (Mdv0, Mdv1) for designating an operation mode, and element designating information (Mbt0, Mdv0, Mdv1) for designating a display element. Mbt1, BITS) and a field for specifying drive data (DUTY, DUTYi) used for driving the display element. The display driver uses the necessary drive data for the display element designated by the element designation information when the address information input according to the change in the strobe signal designates its own address, and mode Perform display control specified by information.
  Since the capture timing of the display control command can be obtained by the strobe signal, it is not necessary to add a start bit or the like to the display control command. In this respect, it is easy to adapt the data format of serial transfer to a data processing unit such as a general byte by microcomputer control.
  [2] In the drive control system according to item 1, the controlled part and the control part are respectively formed on separate wiring boards.
  [3] In the drive control system according to item 2, the control unit pushes and pulls the serial bus.
  [4] In the drive control system according to item 1, the display driver includes drive data registers (DREG1 to DREGn) for storing the drive data of the display element. The control command has a burst mode instruction bit (Mtrs), and the control command for instructing the burst mode is an operation for sequentially writing drive data to drive data registers of a plurality of display elements designated by the element designation information. Instruct the driver.
  By adopting the burst mode, it is possible to improve the efficiency of supplying drive data not only to some drive data registers but also to a large number of drive data registers.
  [5] In the drive control system according to [1], the control command includes address mask information (Amsk) that enables batch designation to share the upper address bits regardless of the state of the predetermined lower plurality of bits of the address information. ).
  By using an address mask, it is possible to efficiently supply control commands not only to some drivers but also to many drivers.
  [6] In the drive control system according to item 1, the display driver includes a drive data register for storing the drive data of the display element. The mode information is a first mode (write + light emission) in which the drive data is written in the drive data register of the display element designated by the bit selection field according to the first state, and the display element emits light using the written drive data. ) To the display driver.
  [7] In the drive control system according to item 6, the mode information is written in the drive data register of the display element designated by the designation information of the display element according to the second state, regardless of the written drive data. The display driver is instructed in a second mode (light-off + writing) in which the designated display element is turned off.
  [8] In the drive control system according to item 7, the mode information is a third mode in which the display element designated by the designation information of the display element emits light using the existing data of the corresponding drive data register according to the third state. (Light emission (data retention)) is instructed to the display driver.
  [9] In the drive control system according to item 8, the mode information is in its fourth state, and the display mode leaves the existing data in the drive data register corresponding to the display element designated by the designation information of the display element. The display driver is instructed to turn off the fourth mode (light off (data retention)).
  The diversification of display modes facilitates creation of software for controlling a large number of controlled elements.
  [10] A drive control system according to another representative embodiment of the present invention includes a plurality of controlled units having a plurality of driven elements and a driver for driving the driven elements, and the controlled units A serial bus to which a driver is commonly connected; and a control unit including a microcomputer for driving and controlling the driver and connected to the serial bus. The serial bus includes a serial signal line, a clock signal line for transmitting a synchronous clock signal output from the microcomputer, and a strobe signal line for transmitting a strobe signal output from the microcomputer. The microcomputer serially outputs a control command to the serial signal line in synchronization with the synchronous clock signal, and changes the strobe signal in synchronization with the output start timing. The control command includes address information for designating the driver, mode information for designating an operation mode, element designation information for designating the driven element, and drive data used for driving the driven element. Each has a field for specifying. When the address information input according to the change in the strobe signal designates its own address, the driver uses the necessary drive data for the driven element designated by the element designation information, and The drive control specified by the information is performed. The controlled object is not limited to display driving, and may be, for example, pulse driving of a stepping motor. In this case as well, the same effect as in item 1 is achieved.
  [11] A semiconductor device according to still another embodiment of the present invention is applied as a display driver suitable for the display control system according to item 1. This semiconductor device (20, 21, 22) has a serial interface circuit (30), a control circuit (32), and a plurality of drive units (DUNT1 to DUNTn) for individually driving a plurality of display elements. The serial interface circuit has a serial terminal (40), a synchronous clock terminal (41), and a strobe terminal (42). In response to a change in the strobe signal input to the strobe terminal, the serial interface circuit converts the synchronous clock signal to the synchronous clock signal. Synchronously input control commands from the serial terminal. The control command specifies address information for designating a semiconductor device, mode information for designating an operation mode, element designation information for designating the display element, and drive data used for driving the display element. Field to do. When the address information input in response to the change in the strobe signal designates its own address, the control circuit uses the necessary drive data for the drive unit of the display element designated by the element designation information. The control specified by the mode information is performed.
  [12] In the semiconductor device of item 11, the drive unit has a drive data register for storing the drive data of the corresponding display element. At this time, when the control command has a burst mode instruction bit and the burst mode is instructed by the control command, the control circuit designates the drive data sequentially received from the control command by the element designation information. Data is sequentially written to the drive data registers of a plurality of display elements. Thereby, the semiconductor device corresponds to the designation of the burst mode.
  [13] In the semiconductor device of item 11, the control command further includes address mask information. At this time, when the address mask is instructed by the address mask information of the control command, the control circuit follows the collective designation to share the upper address bits regardless of the state of the predetermined lower plurality of bits of the address information. It is determined whether its own address is specified.
  [14] In the semiconductor device of [11], the control circuit writes the drive data to the drive data register of the display element specified by the bit selection field by designating the first mode by the mode information. The display element is caused to emit light using the written drive data.
  [15] In the semiconductor device of item 14, the control circuit writes the drive data to the drive data register of the display element designated by the designation information of the display element when the second mode is designated by the mode information. The designated display element is turned off regardless of the written drive data.
  [16] In the semiconductor device of [15], the control circuit causes the display element designated by the designation information of the display element to be transferred to the existing drive data register when the third mode is designated by the mode information. Light is emitted using the data.
  [17] In the semiconductor device of item 16, the control circuit designates the display element designated by the designation information of the display element by designating the fourth mode by the mode information. Turn off the light without changing the data.
  [18] A semiconductor device according to still another embodiment of the present invention is a semiconductor device suitable for the drive control system according to Item 10. This semiconductor device has a serial interface circuit, a control circuit, and a plurality of drive units for individually driving a plurality of driven elements. The serial interface circuit has a serial terminal, a synchronous clock terminal, and a strobe terminal. In response to a change in the strobe signal input to the strobe terminal, a control command is sent from the serial terminal in synchronization with the synchronous clock signal of the synchronous clock terminal. input. The control command includes address information for designating the semiconductor device, mode information for designating an operation mode, element designation information for designating the driven element, and drive data used for driving the driven element. Each has a field for specifying. The control circuit uses the necessary drive data for the drive unit of the driven element designated by the element designation information when the address information input according to the change in the strobe signal designates its own address. Control specified by the mode information.
2. Details of Embodiments Embodiments will be further described in detail.
  FIG. 1 shows an example of a drive control system according to the present invention. The drive control system shown in the figure is an LED light emission drive control system for illumination in a gaming machine such as a pachinko machine or a slot machine.
  In the LED light emission drive control system, a plurality of controlled boards 3, 4, and 5 receive drive control from the control board 1 via the serial bus 2. The controlled substrate 3 is provided with a plurality of LED strings 23 in which a plurality of LEDs are connected in series as display elements on the circuit board, and a display driver 20 that drives the LEDs to emit light in units of LED strings. Here, one LED string constitutes one display element. The display element is a display control target unit by the display driver, and naturally, one LED may be set as a display control target unit. Similarly, a plurality of LED strings 24 and 25 are mounted on the controlled substrates 4 and 5, and display drivers 21 and 22 for driving the LEDs to emit light in units of LED strings are provided. For example, one end of each of the LED strings 23, 24, and 25 is coupled to a drive power source such as 24V, and the other end is coupled to a drive terminal of the corresponding display driver 20, 21, and 22, and the display drivers 20, 21, and 22 are Light emission, extinction, and gradation are controlled by controlling the pulses that flow through the LED strings 23, 24, and 25 based on the display control commands supplied to the LED strings. Note that the bus buffer 11 may be omitted when the load on the serial bus 2 is small.
  The control board 1 includes a microcomputer 10 and a bus buffer 11 that control the driving of the display drivers 20, 21, and 22. The microcomputer 10 generates a display control command according to the operation program, and the generated display control command is output to the serial bus 2 via the bus buffer 11. When an address is assigned to each of the display drivers 20, 21, and 22 commonly connected to the serial bus 2, and the address information included in the display control command specifies itself, the display driver controls the display control. Operated according to command.
  The serial bus 2 includes a serial signal line 2A for transmitting a serial signal TsD1, a clock signal line 2B for transmitting a synchronous clock signal SCK1 output from the microcomputer, and a strobe signal line 2C for transmitting a strobe signal SS output by the microcomputer. Become. The serial signal TsD1 and the synchronous clock signal SCK1 are output from an SCI controller (not shown) of the microcomputer 10. The strobe signal SS is output from a general-purpose port (not shown) of the microcomputer 10, for example. The drive form for the serial bus 2 is push-pull drive.
  FIG. 2 shows an example of the microcomputer 10. The microcomputer 10 is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a complementary MOS integrated circuit manufacturing technique or the like. The microcomputer 10 includes a central processing unit (CPU) 100 that executes instructions, a RAM 101 that is used for a work area of the CPU 100, a ROM 102 that stores an operation program of the CPU 100, and a DMAC that performs data transfer control in accordance with initial settings by the CPU 100. Direct memory access controller (104), SCIC (serial communication interface controller) 106, TMR (timer) 107, GPRT (general purpose port) 108, SYSC (system control circuit) 105, etc., which are internal buses 109 is connected. The SCIC 106 outputs the serial signal TsD1 and the synchronous clock signal SCK1, and the GPRT 108 outputs the strobe signal SS. The CPU 100 generates a display control command by data processing according to an operation program stored in the ROM 102, controls the output operation of the SCIC 106, and controls the output operation of the GPRT 108 and the like. An external memory (MRY) 12 composed of a synchronous DRAM or the like is connected to the MCNT 104 and used for data processing of the CPU 100.
  FIG. 3 shows an example of the display driver 20. The display driver 20 is not particularly limited, but is a semiconductor device formed on a single semiconductor substrate such as single crystal silicon by a complementary MOS integrated circuit manufacturing technique or the like. The display driver 20 includes a serial interface circuit (SIF) 30, a buffer memory (BUF) 31, a control circuit (DCNT) 32, and a plurality of drive units DUNT1 to DUNTn for individually driving a plurality of LED strings. Each of the drive units DUNT1 to DUNTn includes control pulse generation units PUNT1 to PUNTn, output gates OGT1 to OGTn, and channel-type driving MOS transistors TR1 to TRn. Each of the control pulse generation units PUNT1 to PUNTn includes drive data registers DREG1 to DREGn and pulse voltage generation circuits PLSV1 to PLSVn. The pulse voltage generation circuits PLSV10 to PLSVn generate duty pulse voltages according to the values of the corresponding drive data registers DREG1 to DREGn, and drive the gate electrodes of the drive transistors TR1 to TRn via the output gates OGT1 to OGTn. As a result, the drive MOS transistors TR1 to TRn pass a drive current having a duty controlled by the drive data to the LED string via the drive terminals Q1 to Qn. Thereby, the light emission luminance or gradation of the LED string is controlled. The cut-off control for the driving MOS transistors TR1 to TRn can be performed by setting the duty of the pulse voltage to 0, but here, it can also be realized by initializing the outputs of the output gates OGT1 to OGTn to a low level. ing. The outputs of the output gates OGT1 to OGTn are selectively set to the low level by the turn-off control signals COF1 to COFn output from the control circuit 32.
  The serial interface circuit 30 has a serial terminal 40, a synchronous clock terminal 41, and a strobe terminal 42, and synchronizes with the synchronous clock signal SCK 1 of the synchronous clock terminal 41 in response to a change in the strobe signal SS input to the strobe terminal 42. Then, a display control command is input from the serial terminal 40 as the serial signal TxD1. The buffer memory 31 temporarily holds the input display control command.
  The control circuit 32 is assigned an address determined by the pull-up and pull-down states of the 6-bit address program terminals Add0 to Add5. When the address information input in accordance with the change in the strobe signal SS designates its own address, the control circuit 32 performs drive control of the LED string based on the display control command accompanied with the address information.
  4 and 5 illustrate the data format of the display control command. FIG. 4 shows the case of the normal mode, and FIG. 5 shows the case of the burst mode.
  The display control command determines an address ADDRS for designating a display driver and the like, mode information MOD for designating an operation mode, output bit selection data BITS for designating a drive unit, that is, a drive terminal, and a duty of a drive pulse voltage. The data format includes a field for specifying display drive data DUTY and stop byte STPBYT for each byte.
  In the address ADDRS, the first bit is an address mask bit Amsk, the second bit is a reserved bit, and the 6 bits after the third bit are display driver address information A0 to A5. When the address mask bit Amsk is set to “1”, the collective designation in which the upper address bits A0 and A1 are common regardless of the states of the predetermined lower plural bits A2 to A5 of the display driver address information A0 to A5 is valid. And In short, it is possible to collectively specify a maximum of 16 display drivers having a common upper address A0, A1 among a maximum of 64 display drivers.
  In the mode information MOD, the first bit is transfer mode data Mtrs, the second and third bits are target byte selection data Mbs0 and Mbs1, and the fourth and fifth bits are drive mode data Mdv0 and Mdv1.
  Transfer mode data Mtrs = 0 indicates the normal mode, and transfer mode data Mtrs = 1 indicates the burst mode. In the normal mode, as shown in FIG. 4, the third byte area BYT3 is recognized as output bit selection data BITS, and the fourth byte area BYT4 is recognized as display drive data DUTY.
  The target byte selection data means that when Mbt0, Mbt1 = 0, 0, the drive units DUNT1 to DUNT8 for one byte of Q1 to Q8 can be driven, and Mbt0, Mbt1 = 0, 1 In this case, it means that the drive units DUNT9 to DUNT16 of 1 byte of Q9 to Q16 can be driven. In the case of Mbt0, Mbt1 = 1, 0, the drive unit of 1 byte of Q17 to Q24 at maximum This means that DUNT17 to DUNT24 can be driven, and when Mbt0 and Mbt1 = 1, 1, this means that drive units DUNT25 to DUNT32 for one byte of Q25 to Q32 can be driven. Which one of the drive units for one byte that can be selected is used for driving depends on the value of each bit of the output bit selection data BITS. For example, when Mbt0, Mbt1 = 0, 0, and BITS = 10000001, only Q1 and Q8 are driven by the drive units DUNT1 and DUNT8. As a result, the drive unit designated as the drive target is turned on or off, and when necessary, the drive data is stored in the drive data register DREGi. Which operation the drive unit performs is instructed by drive mode data Mdv0 and Mdv1.
  The drive mode data is “lights off and data hold” when Mdv0, Mdv1 = 0, 0, “light emission and data hold” when Mdv0, Mdv1 = 0, 1, and Mdv0, Mdv1 = 1, 0. Indicates a driving mode of “lighting off and writing”, and when Mdv0 and Mdv1 = 1, 1, “writing and light emission”.
  The drive mode of “write and light emission” is the first mode in which the drive data is written in the drive data register DREGi of the drive unit DUNTi specified by the output bit selection data BITS, and the LED string is emitted using the written drive data. The
  The driving mode of “turning off and writing” is to write drive data to the drive data register DREGi of the drive unit DUNTi specified by the output bit selection data BITS, and to the LED string with the corresponding turn-off control signal COFi regardless of the written drive data. This is a second mode in which the supply of the driving current is cut off and the light is turned off.
  The driving mode of “light emission and data retention” is the third mode in which the corresponding LED string is emitted using the driving data already held in the driving data register DREGi of the drive unit DUNTi specified by the output bit selection data BITS. .
  The driving mode of “turn off and hold data” is the fourth mode in which the corresponding LED string is turned off while keeping the drive data already held in the drive data register DREGi of the drive unit DUNTi specified by the output bit selection data BITS. The
In the burst mode, as illustrated in FIG. 5, the third and subsequent bytes are recognized as 8-byte display drive data, and there is no region recognized as output bit selection data BITS. Accordingly, the selected display driver address ADDRS, a target byte selection data MBT0, drive unit DUNT of 1 byte which is selected by Mbt1 i ~DUNT i + 7 of the driving register DREG i ~DREG i + 7 different display drive data DUTY1~DUTY8 to The operation of storing sequentially is enabled.
  The control circuit 32 of each display driver 20, 21, 22 decodes each field in accordance with the significance of the display control command, and performs drive control of the LED string according to the decoding result.
  FIG. 6 shows a specific data format example of the display control command described above. In the figure, x means indefinite tolerance. In the example of Ex5), the display drive data is expressed in hexadecimal notation for convenience. In this example, address masking is performed and the burst mode is selected. For each of the 16 display drivers assigned to 16 different addresses, the drive registers DREG1 of the drive units DUNT1 to DUNT8 for 1 byte. The operation of sequentially storing different display drive data DUTY1 to DUTY8 in .about.DREG8 is enabled.
  By using the above display control command for LED drive control, 1) individual LED can be individually controlled by address selection by display driver individual address and target byte selection. 2) If the gradation is the same, normal mode can be used. The drive registers of a plurality of drive units can be rewritten simultaneously in one display driver. 3) If the burst mode is selected, the drive registers of the plurality of drive units can be rewritten to different drive data in the display driver. 4) When the surface of the display area is divided into areas A, B, C, and D as shown in FIG. 7, by setting an address mask in both the normal mode and the burst mode, Display drive data can be efficiently rewritten.
  FIG. 8A illustrates a control mode during normal operation as a display control mode on the board surface of FIG. 7, and FIG. 8B illustrates a control mode when a “hit” occurs as a display control mode on the panel surface of FIG. 7. A display control command designating a burst mode is stored in the memory for display control during normal operation in each of the areas A, B, C, and D. During normal operation, the DMAC 103 reads the order display control command from the memory and transfers it to the SCI 106 according to the initial setting by the CPU 100, and the SCI 106 sequentially supplies the transferred display control command to the display drivers 20, 21, 22 via the serial bus 2. To do. As a result, normal display is repeatedly performed on the core areas A, B, C, and D on the board surface. During this time, the CPU 100 is released from the LED drive control and can concentrate on other data processing. When “winning” occurs, the CPU 100 generates a display control command in the normal mode in order to realize a conspicuous display mode according to the operation program, and gives the generated display control command from the SCIC 106 to the display drivers 20, 21, 2. Thus, it is possible to realize a display that is decorated so as to stand out from the normal display of the regions A, B, C, and D.
  The LED light emission drive control system described above has the following effects.
  (1) Since the capture timing of the display control command can be obtained by the strobe signal SS, it is not necessary to add a start bit or the like to the display control command. In this respect, it is easy to adapt the data format of serial transfer to a data processing unit such as a general byte by microcomputer control. For example, the timing waveforms of the strobe signal SS, serial data TxD1, and serial clock SCK1 are illustrated in FIG.
  (2) By specifying the burst mode, it is possible to instruct the driver to sequentially write drive data to the drive data registers of a plurality of drive units. By adopting the burst mode, it becomes possible to efficiently write different drive data not only to some drive data registers but also to many drive data registers.
  (3) The control command adopts an address mask that enables a batch designation to make the lower address bits common regardless of the state of the predetermined upper plurality of bits of the address information, so that some display drivers In addition, the supply of control commands to a large number of display drivers can be made more efficient.
  (4) Diversify the display modes that can be instructed by the control command, command to perform operations such as light emission by writing drive data, light emission by writing drive data, light emission by existing drive data, light extinction while leaving existing drive data unchanged Therefore, it is easy to create software for relatively large display drive control using a large number of ELDs.
  (5) The following processing time can be realized for rewriting the drive control data. Assuming that the data processing speed is 5 Mbps, it takes (1 bit + 5 bytes) / 5 Mbps = 8.2 μs to write the same drive data in the eight drive data registers in the normal mode. When writing different drive data to each of the eight drive data registers in the normal mode when the data processing speed is 5 Mbps, 8.28.2 μs × 8 = 65.6 μs is required. Similarly, in the burst mode, when different driving data is written to the eight driving data registers, (1 bit + 11 bytes) / 5 Mbps = 17.8 μs is sufficient. As is clear from this trial calculation, LED drive control can be performed efficiently if the operation mode is properly used according to the processing. In the above formula, “1 bit” means the generation of the strobe signal SS.
  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.
  For example, the present invention is not limited to using a pulse voltage with duty control for light emission of the LED by the display driver, and using an output gate for turning off the light, and can be changed as appropriate. When gradation display is not performed, duty control is not necessary, and it is possible to change the control only to whether or not the drive current flows. The drive control system according to the present invention is not limited to application to illumination display of an amusement machine. Further, the display element is not limited to the LED or the LED string. The drive form of the display driver can be changed according to the drive form of the display element. Further, the present invention is not limited to display drive control, and can also be applied to variable duty pulse drive control of a stepping motor in a servo control system including a plurality of stepping motors, for example.
DESCRIPTION OF SYMBOLS 1 Control board 2 Serial bus 2A Serial signal line 2B Clock signal line 2C Strobe signal line SCK1 Synchronous clock signal SS Strobe signal TsD1 Serial signal 3, 4, 5 Controlled board 10 Microcomputer 11 Bus buffer 20, 21, 22 Display driver 23 , 24, 25 LED string 30 Serial interface circuit (SIF)
31 Buffer memory (BUF)
32 Control circuit (DCNT)
DUNT1 to DUNTn Drive unit PUNT1 to PUNTn Control pulse generation unit OGT1 to OGTn Output gate TR1 to TRn Drive MOS transistor DREG1 to DREGn Drive data register PLSV1 to PLSVn Pulse voltage generation circuit 100 CPU
104 DMAC
106 SCIC (Serial Communication Interface Controller)
108 GPRT (general-purpose port)

Claims (5)

  1. A semiconductor device having a serial interface circuit, a control circuit, and a plurality of drive units for individually driving a plurality of display elements,
    The serial interface circuit has a serial terminal, a synchronous clock terminal, and a strobe terminal. In response to a change in the strobe signal input to the strobe terminal, a control command is sent from the serial terminal in synchronization with the synchronous clock signal of the synchronous clock terminal. type in,
    The drive unit has a drive data register for storing drive data for a corresponding display element,
    The control command specifies address information for designating a semiconductor device, mode information for designating an operation mode, element designation information for designating the display element, and drive data used for driving the display element. Has a field to
    The control command includes an instruction bit for designating a transfer mode including a normal mode and a burst mode in a field for specifying the mode information,
    The field for specifying the element designation information is configured so that the display element can be individually designated when the normal mode is designated, and the display element is defined in advance when the burst mode is designated. It is configured so that it can be specified in groups,
    When the normal mode is instructed by the control command when the address information input in response to the change in the strobe signal specifies its own address, the control circuit receives the drive data received from the control command. When the burst mode is instructed by the control command, the drive data sequentially received from the control command is written into the drive data register corresponding to each display element designated by the element designation information. sequential write, rows that have the control specified by the mode information to the drive data register of the plurality of display elements of the group specified by,
    The control command further includes address mask information,
    When the address mask is instructed by the address mask information of the control command, the control circuit has its own address according to a collective designation in which the upper address bits are common regardless of the state of the predetermined lower plural bits of the address information. A semiconductor device that determines whether or not is specified .
  2. The control circuit writes the drive data to the drive data register of the display element designated by the display element designation information when the first mode is designated by the mode information, and uses the written drive data to display the display element. The semiconductor device according to claim 1, which emits light .
  3. When the second mode is designated by the mode information, the control circuit writes the drive data to the drive data register of the display element designated by the display element designation information, and is designated regardless of the written drive data. The semiconductor device according to claim 2, wherein the display element is turned off .
  4. The control circuit causes the display element specified by the display element specifying information to emit light using the existing data of the corresponding drive data register by designating the third mode by the mode information. semiconductor devices.
  5. 5. The control circuit turns off the display element designated by the display element designation information without changing the existing data in the corresponding drive data register by designating the fourth mode by the mode information. The semiconductor device as described .
JP2009090886A 2009-04-03 2009-04-03 Semiconductor device Expired - Fee Related JP5607313B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009090886A JP5607313B2 (en) 2009-04-03 2009-04-03 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009090886A JP5607313B2 (en) 2009-04-03 2009-04-03 Semiconductor device

Publications (3)

Publication Number Publication Date
JP2010240091A JP2010240091A (en) 2010-10-28
JP2010240091A5 JP2010240091A5 (en) 2012-04-12
JP5607313B2 true JP5607313B2 (en) 2014-10-15

Family

ID=43093875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009090886A Expired - Fee Related JP5607313B2 (en) 2009-04-03 2009-04-03 Semiconductor device

Country Status (1)

Country Link
JP (1) JP5607313B2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5392478B2 (en) * 2009-05-20 2014-01-22 株式会社大一商会 Pachinko machine
JP2012120617A (en) * 2010-12-07 2012-06-28 Daito Giken:Kk Game machine
JP2013150740A (en) * 2012-01-26 2013-08-08 Fujishoji Co Ltd Game machine
JP5823418B2 (en) * 2013-01-15 2015-11-25 株式会社藤商事 Game machine
JP6140452B2 (en) * 2013-01-15 2017-05-31 株式会社藤商事 Game machine
JP6472219B2 (en) * 2014-11-17 2019-02-20 株式会社三共 Game machine
JP6053855B2 (en) * 2015-04-01 2016-12-27 株式会社藤商事 Game machine
JP6147801B2 (en) * 2015-05-12 2017-06-14 株式会社藤商事 Game machine
JP6022660B2 (en) * 2015-10-06 2016-11-09 株式会社藤商事 Game machine
JP6125593B2 (en) * 2015-10-29 2017-05-10 株式会社藤商事 Game machine
JP6325623B2 (en) * 2016-10-05 2018-05-16 株式会社藤商事 Game machine
JP2019080835A (en) * 2017-10-31 2019-05-30 株式会社オリンピア Game machine

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2759120B2 (en) * 1989-04-05 1998-05-28 株式会社三陽電機製作所 Neon light flasher
JPH11126047A (en) * 1997-10-21 1999-05-11 Nichia Chem Ind Ltd Led display device and its driving method
JP4030471B2 (en) * 2003-06-06 2008-01-09 日本テキサス・インスツルメンツ株式会社 Pulse signal generation circuit
JP4640580B2 (en) * 2005-02-08 2011-03-02 レシップホールディングス株式会社 Lighting control system
JP2007007148A (en) * 2005-06-30 2007-01-18 Heiwa Corp Game machine

Also Published As

Publication number Publication date
JP2010240091A (en) 2010-10-28

Similar Documents

Publication Publication Date Title
JP5607313B2 (en) Semiconductor device
JP4927032B2 (en) Game machine
JP2007007148A (en) Game machine
JP5813694B2 (en) Game machine
CN104077990A (en) LED nixie tube display and key control chip using time division multiplexing technology
JP5813697B2 (en) Game machine
WO2013088930A1 (en) Light source control device and game machine
JP5191558B2 (en) Game machine
JP6022660B2 (en) Game machine
JP4318900B2 (en) Game machine
JP6140452B2 (en) Game machine
JP5823418B2 (en) Game machine
JP5847972B1 (en) Game machine
JP5443582B1 (en) Game machine
JP5813696B2 (en) Game machine
JP5787967B2 (en) Game machine
JP5813698B2 (en) Game machine
JP6053855B2 (en) Game machine
JP6325623B2 (en) Game machine
JP5787966B2 (en) Game machine
JP5400214B1 (en) Game machine
JP6444459B2 (en) Game machine
JP6132741B2 (en) Game machine
JP5731551B2 (en) Game machine
JP6185025B2 (en) Game machine

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120223

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120223

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130926

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131029

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140605

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140730

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140821

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140828

R150 Certificate of patent or registration of utility model

Ref document number: 5607313

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees