JP2009278105A - 薄膜トランジスタの製造方法 - Google Patents
薄膜トランジスタの製造方法 Download PDFInfo
- Publication number
- JP2009278105A JP2009278105A JP2009117601A JP2009117601A JP2009278105A JP 2009278105 A JP2009278105 A JP 2009278105A JP 2009117601 A JP2009117601 A JP 2009117601A JP 2009117601 A JP2009117601 A JP 2009117601A JP 2009278105 A JP2009278105 A JP 2009278105A
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- Prior art keywords
- carbon nanotube
- semiconductor layer
- forming
- thin film
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 229910001887 tin oxide Inorganic materials 0.000 description 1
Classifications
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/464—Lateral top-gate IGFETs comprising only a single gate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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- H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/778—Nanostructure within specified host or matrix material, e.g. nanocomposite films
- Y10S977/784—Electrically conducting, semi-conducting, or semi-insulating host material
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/788—Of specified organic or carbon-based composition
- Y10S977/789—Of specified organic or carbon-based composition in array format
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/788—Of specified organic or carbon-based composition
- Y10S977/795—Composed of biological material
- Y10S977/796—Composed of biological material for electrical or electronic purpose
Abstract
【解決手段】本発明の薄膜トランジスタの製造方法は、カーボンナノチューブアレイを提供する第一ステップと、前記カーボンナノチューブアレイから、少なくとも、一枚のカーボンナノチューブフィルムを引き伸ばす第二ステップと、絶縁基板を提供し、該絶縁基板の表面に少なくとも一枚の前記カーボンナノチューブフィルムを設置し、半導体層を形成する第三ステップと、前記半導体層にソース電極及びドレイン電極を分離して形成し、該ソース電極及びドレイン電極を前記半導体層に電気的に接続させる第四ステップと、前記半導体層に絶縁層を形成する第五ステップと、前記絶縁層の表面にゲート電極を形成し、薄膜トランジスタを形成する第六ステップと、を含む。
【選択図】図1
Description
トランジスタの製造方法に関するものである。
図1と図2を参照すると、本発明の実施例1は、トップゲート型(Top Gate Type)薄膜トランジスタ10の製造方法を提供する。該製造方法は、下記のステップを含む。
図4と図5を参照すると、本実施例は、ボトムゲート型(Bottom Gate Type)薄膜トランジスタ20の製造方法を提供する。該製造方法は、前記実施例1の薄膜トランジスタ10の製造方法と基本的に同じである。
図6を参照すると、本施例は、トップゲート型薄膜トランジスタアレイの製造方法を提供する。該製造方法は、前記実施例1の薄膜トランジスタの製造方法と基本的に同じである。異なる所は、本実施例が一つの絶縁基板に複数の薄膜トランジスタを形成し、薄膜トランジスタアレイを形成することである。具体的には、下記のステップを含む。
本実施例は、ボトムゲート型薄膜トランジスタアレイの製造方法を提供する。該製造方法は、前記実施例2の製造方法と基本的に同じで、具体的には、下記のステップを含む。カーボンナノチューブアレイを提供する第一ステップと、前記カーボンナノチューブアレイから、少なくとも、一枚のカーボンナノチューブフィルムを引き伸ばす第二ステップと、絶縁基板を提供し、該絶縁基板の表面に複数のゲート電極を形成する第三ステップと、前記の複数のゲート電極を被覆するように、絶縁層を形成する第四ステップと、前記絶縁層の表面に少なくとも、一枚のカーボンナノチューブフィルムを設置し、該カーボンナノチューブフィルムをパターン化し、複数の半導体層を形成し、該複数の半導体層が前記絶縁層により複数の前記ゲート電極に対向し、絶縁的に設置される第五ステップと、前記半導体層の表面に、ソース電極及びドレイン電極を分離して形成し、該ソース電極及びドレイン電極を前記半導体層に電気的に接続させる第六ステップと、を含む。
110、210 絶縁基板
120、220 ゲート電極
130、230 絶縁層
140、240 半導体層
151、251 ソース電極
152、252 ドレイン電極
Claims (6)
- カーボンナノチューブアレイを提供する第一ステップと、
前記カーボンナノチューブアレイから、少なくとも、一枚のカーボンナノチューブフィルムを引き伸ばす第二ステップと、
絶縁基板を提供し、該絶縁基板の表面に少なくとも一枚の前記カーボンナノチューブフィルムを設置し、半導体層を形成する第三ステップと、
前記半導体層にソース電極及びドレイン電極を分離して形成し、該ソース電極及びドレイン電極を前記半導体層に電気的に接続させる第四ステップと、
前記半導体層に絶縁層を形成する第五ステップと、
前記絶縁層の表面にゲート電極を形成し、薄膜トランジスタを形成する第六ステップと、を含むことを特徴とする薄膜トランジスタの製造方法。 - カーボンナノチューブアレイを提供する第一ステップと、
前記カーボンナノチューブアレイから、少なくとも、一枚のカーボンナノチューブフィルムを引き伸ばす第二ステップと、
絶縁基板を提供し、該絶縁基板の表面にゲート電極を形成する第三ステップと、
前記ゲート電極を被覆するように絶縁層を形成する第四ステップと、
前記絶縁層の表面に少なくとも、一枚のカーボンナノチューブフィルムを設置し、半導体層を形成する第五ステップと、
前記半導体層の表面に、ソース電極及びドレイン電極を分離して形成し、該ソース電極及びドレイン電極を前記半導体層に電気的に接続させる第六ステップと、を含むことを特徴とする薄膜トランジスタの製造方法。 - 前記カーボンナノチューブフィルムが所定の方向に沿って配列された複数のカーボンナノチューブを含み、各々のカーボンナノチューブが分子間力で緊密に連接されることを特徴とする、請求項1又は2に記載の薄膜トランジスタの製造方法。
- 前記ソース電極及び前記ドレイン電極を、前記カーボンナノチューブフィルムにおけるカーボンナノチューブが配列した方向に沿って設置することを特徴とする、請求項1から3のいずれか一項に記載の薄膜トランジスタの製造方法。
- 前記ソース電極及び前記ドレイン電極を分離して形成した後、該ソース電極と該ドレイン電極に電圧を印加し、前記カーボンナノチューブフィルムにおける、金属性のカーボンナノチューブを焼切り、金属性のカーボンナノチューブを除去することを特徴とする、請求項1から4のいずれか一項に記載の薄膜トランジスタの製造方法。
- 少なくとも一枚の前記カーボンナノチューブフィルムを設置した後、水素プラズマ、マイクロ波、テラヘルツ波、赤外光、紫外光又は可視光で前記カーボンナノチューブフィルムを照射し、前記カーボンナノチューブフィルムにおける、金属性のカーボンナノチューブを焼切り、金属性のカーボンナノチューブを除去することを特徴とする、請求項1から4のいずれか一項に記載の薄膜トランジスタの製造方法。
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US7947542B2 (en) | 2011-05-24 |
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