JP2009212360A - 半導体装置並びにその製造方法およびその実装方法 - Google Patents
半導体装置並びにその製造方法およびその実装方法 Download PDFInfo
- Publication number
- JP2009212360A JP2009212360A JP2008054870A JP2008054870A JP2009212360A JP 2009212360 A JP2009212360 A JP 2009212360A JP 2008054870 A JP2008054870 A JP 2008054870A JP 2008054870 A JP2008054870 A JP 2008054870A JP 2009212360 A JP2009212360 A JP 2009212360A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- pad
- semiconductor device
- lead
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/85132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】パッドPD1とリードRとをワイヤW1で接続する場合において、パッドPD1をファーストボンディングし、その後、リードRをセカンドボンディングする。このとき、パッドPD1でファーストボンディングを実施した後、リバースモーションが行なわれることになる。このとき、リードRと接続するパッドPD1の形状を長方形とし、長方形の短辺をy方向に配置することにより、リバースモーションでキャピラリが不揮発性メモリチップCHP2側に移動する移動距離よりも、パッドPD1と不揮発性メモリチップCHP2との間のクリアランスを大きくする。
【選択図】図4
Description
本実施の形態1における半導体装置について図面を参照しながら説明する。本実施の形態1における半導体装置は、例えば、遊技機器に使用されるものであり、1つのパッケージでシステムを構成するSIP(System In Package)となっている。
省略して示している。
前記実施の形態1では、4Gタイプの不揮発性メモリチップを1つ配線基板に搭載する例について説明したが、本実施の形態2では、2Gタイプの不揮発性メモリチップを2つ配線基板に搭載する例について説明する。
C キャピラリ
CE チップセレクト端子
CHP1 コントローラチップ(第2半導体チップ)
CHP2 不揮発性メモリチップ(第1半導体チップ)
CHP3 外部LSIチップ
CHP4 不揮発性メモリチップ
CHP5 不揮発性メモリチップ
DAF1 絶縁性フィルム
DAF2 絶縁性フィルム
DAF3 絶縁性フィルム
ER1 有効領域
ER2 有効領域
IF1 外部インターフェイス
IF2 内部インターフェイス
L1 配線
L2 配線
L3 配線
L4 配線
LS 配線基板
MR 樹脂
OR アウタリード(アウタリード部)
P パッケージ
PD1 パッド(第1ボンディングリード)
PD2 パッド(第1電極)
PD3 パッド(第2ボンディングリード)
PD4 パッド(第2電極)
PD5 パッド(ボンディングリード)
PD6 パッド(ボンディングリード)
PD7 パッド(ボンディングリード)
PD8 パッド(ボンディングリード)
PD9 パッド(電極)
PD10 パッド(電極)
PRE パワーオンリセット端子
R リード(インナリード部)
SOC ソケット
T タブ(ダイパッド)
W ワイヤ
W1 ワイヤ
W2 ワイヤ
W3 ワイヤ
W4 ワイヤ
W5 ワイヤ
Claims (24)
- 平面形状が矩形形状から成り、複数のボンディングリードが形成された表面を有する配線基板と、
平面形状が矩形形状から成り、複数の電極が形成された主面を有し、前記配線基板の前記表面上に配置された半導体チップと、
を含み、
前記複数のボンディングリードのそれぞれは、平面形状が長方形から成り、
前記複数のボンディングリードは、前記複数のボンディングリードのそれぞれの長辺が前記半導体チップの一辺と並ぶように配置されていることを特徴とする半導体装置。 - (a)導電材料からなる矩形形状のタブと、
(b)前記タブの周囲に配置されたリードと、
(c)前記タブ上に配置された矩形形状の配線基板と、
(d)前記配線基板上に配置された第1半導体チップとを備え、
前記配線基板の一辺に並行するように、前記配線基板の表面には平面形状が長方形からなる第1ボンディングリードが形成されており、前記第1ボンディングリードは、前記リードとワイヤで電気的に接続されている半導体装置であって、
前記第1ボンディングリードの長辺は、前記配線基板の前記一辺と並行するように配置され、前記第1ボンディングリードの短辺は、前記配線基板の前記一辺と交差する方向と並行するように配置されていることを特徴とする半導体装置。 - 請求項2記載の半導体装置であって、
前記第1半導体チップは、平面形状が長方形をしており、
前記第1半導体チップの長辺は、前記配線基板の前記一辺と並行するように配置され、
前記第1半導体チップの長辺と前記配線基板の前記一辺の間の領域に前記第1ボンディングリードが形成されていることを特徴とする半導体装置。 - 請求項3記載の半導体装置であって、
前記第1半導体チップの短辺と並行するように、前記第1半導体チップの表面に第1電極が形成され、かつ、前記配線基板の辺であって前記一辺と交差する他辺と並行するように、前記配線基板の表面に第2ボンディングリードが形成されており、
前記第1電極と前記第2ボンディングリードとはワイヤで電気的に接続されていることを特徴とする半導体装置。 - 請求項4記載の半導体装置であって、
前記配線基板に形成されている前記第1ボンディングリードと、前記配線基板に形成されている前記第2ボンディングリードとは、前記配線基板に形成されている配線で電気的に接続されていることを特徴とする半導体装置。 - 請求項5記載の半導体装置であって、
前記配線基板は多層配線基板であることを特徴とする半導体装置。 - 請求項4記載の半導体装置であって、
前記第2ボンディングリードは、平面形状が長方形をしていることを特徴とする半導体装置。 - 請求項7記載の半導体装置であって、
前記第2ボンディングリードの長辺は、前記配線基板の前記一辺と並行するように配置され、前記第2ボンディングリードの短辺は、前記配線基板の前記一辺と交差する方向と並行するように配置されていることを特徴とする半導体装置。 - 請求項8記載の半導体装置であって、
前記第1ボンディングリードの大きさと前記第2ボンディングリードの大きさとは等しいことを特徴とする半導体装置。 - 請求項8記載の半導体装置であって、
前記第1ボンディングリードの大きさは、前記第2ボンディングリードの大きさよりも小さいことを特徴とする半導体装置。 - 請求項2記載の半導体装置であって、
前記配線基板と前記第1半導体チップとは絶縁性フィルムで接着されていることを特徴とする半導体装置。 - 請求項2記載の半導体装置であって、
前記配線基板上には、前記第1半導体チップの他に、第2半導体チップが配置されていることを特徴とする半導体装置。 - 請求項12記載の半導体装置であって、
前記第1半導体チップは、不揮発性メモリを形成した不揮発性メモリチップであり、
前記第2半導体チップは、前記不揮発性メモリを制御する集積回路を形成したコントローラチップであることを特徴とする半導体装置。 - 実装基板に設けられたソケットに挿入して実装される半導体装置であって、
タブと、
前記タブの周囲に配置された複数のリードと、
平面形状が前記タブの外形寸法よりも小さい矩形形状から成り、複数の第1ボンディングリード及び複数の第2ボンディングリードが形成された表面を有し、前記タブ上に第1絶縁性フィルムを介して配置された配線基板と、
平面形状が矩形形状から成り、複数の第1電極が形成された第1主面を有し、前記配線基板の前記表面上に第2絶縁性フィルムを介して配置された第1半導体チップと、
前記配線基板の前記複数の第1ボンディングリードと前記複数のリードとをそれぞれ電気的に接続する複数の第1ワイヤと、
前記第1半導体チップの前記複数の第1電極と前記配線基板の前記複数の第2ボンディングリードとをそれぞれ電気的に接続する複数の第2ワイヤと、
前記タブ、前記複数のリードのそれぞれの一部、前記配線基板、前記第1半導体チップ、前記複数の第1ワイヤ及び前記複数の第2ワイヤを封止する封止体とを含むことを特徴とする半導体装置。 - 請求項14記載の半導体装置であって、
前記第1ボンディングリードは、配線を介して前記第2ボンディングリードと電気的に接続されていることを特徴とする半導体装置。 - 請求項14記載の半導体装置であって、
前記配線基板の前記表面上には、平面形状が短形形状から成り、複数の第2電極が形成された第2主面を有する第2半導体チップが、第3絶縁性フィルムを介して配置されていることを特徴とする半導体装置。 - (a)矩形形状のタブと前記タブの周囲に形成されているリードを含むリードフレームを用意する工程と、
(b)前記タブ上に配線基板を搭載する工程と、
(c)前記配線基板上に第1半導体チップを搭載する工程とを備え、
前記配線基板の一辺に並行するように、前記配線基板の表面には平面形状が長方形からなる第1ボンディングリードが形成されており、前記第1ボンディングリードの長辺は、前記配線基板の前記一辺と並行するように配置され、前記第1ボンディングリードの短辺は、前記配線基板の前記一辺と交差する方向に並行するように配置されている半導体装置の製造方法であって、
(d)前記第1ボンディングリードと前記リードとを第1ワイヤで電気的に接続する工程を有し、
前記(d)工程は、前記第1ワイヤの一端部を前記第1ボンディングリードに接続した後、前記第1ワイヤの前記一端部とは反対側の他端部を前記リードと接続することを特徴とする半導体装置の製造方法。 - 請求項17記載の半導体装置の製造方法であって、
前記(b)工程は、前記タブと前記配線基板とを第1絶縁性フィルムで接続し、
前記(c)工程も、前記配線基板と前記第1半導体チップとを第2絶縁性フィルムで接続することを特徴とする半導体装置の製造方法。 - 請求項17記載の半導体装置の製造方法であって、
前記第1半導体チップは平面形状が長方形をしており、
前記第1半導体チップの長辺は、前記配線基板の前記一辺と並行するように配置され、
前記第1半導体チップの長辺と前記配線基板の前記一辺の間の領域に前記第1ボンディングリードが形成されていることを特徴とする半導体装置の製造方法。 - 請求項19記載の半導体装置の製造方法であって、
前記第1半導体チップの短辺と並行するように、前記第1半導体チップの表面に第1電極が形成され、かつ、前記配線基板の辺であって前記一辺と交差する他辺と並行するように、前記配線基板の表面に第2ボンディングリードが形成されており、
(e)さらに、前記第1電極と前記第2ボンディングリードとを第2ワイヤで接続する工程を有することを特徴とする半導体装置の製造方法。 - 請求項20記載の半導体装置の製造方法であって、
前記(e)工程は、前記第2ワイヤの一端部を前記第1電極に接続した後、前記第2ワイヤの前記一端部とは反対側の他端部を前記第2ボンディングリードと接続することを特徴とする半導体装置の製造方法。 - 請求項21記載の半導体装置の製造方法であって、
前記第2ボンディングリードは、平面形状が長方形をしており、
前記第2ボンディングリードの長辺は、前記配線基板の前記一辺と並行するように配置され、前記第2ボンディングリードの短辺は、前記配線基板の前記一辺と交差する方向と並行するように配置されていることを特徴とする半導体装置の製造方法。 - 請求項20記載の半導体装置の製造方法であって、
前記(c)工程後、前記(e)工程を実施し、
前記(e)工程後、前記(d)工程を実施することを特徴とする半導体装置の製造方法。 - 半導体チップを封止することにより形成されたパッケージを実装基板のソケットに挿入する工程を含み、
前記パッケージは、
(a)導電材料からなる矩形形状のタブと、
(b)前記タブの周囲に配置されたリードと、
(c)前記タブ上に配置された矩形形状の配線基板と、
(d)前記配線基板上に配置された前記半導体チップと、
(e)前記半導体チップを封止する封止材とを備え、
前記配線基板の一辺に並行するように、前記配線基板の表面には平面形状が長方形からなる第1ボンディングリードが形成されており、前記第1ボンディングリードは、前記リードとワイヤで電気的に接続されているものであり、
前記第1ボンディングリードの長辺は、前記配線基板の前記一辺と並行するように配置され、前記第1ボンディングリードの短辺は、前記配線基板の前記一辺と交差する方向と並行するように配置されている半導体装置の実装方法であって、
前記封止材から露出している前記リードの一部を示すアウタリードを前記実装基板の前記ソケットに挿入することにより、前記パッケージを前記実装基板に実装することを特徴とする半導体装置の実装方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008054870A JP4951555B2 (ja) | 2008-03-05 | 2008-03-05 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008054870A JP4951555B2 (ja) | 2008-03-05 | 2008-03-05 | 半導体装置の製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2009212360A true JP2009212360A (ja) | 2009-09-17 |
JP2009212360A5 JP2009212360A5 (ja) | 2011-04-07 |
JP4951555B2 JP4951555B2 (ja) | 2012-06-13 |
Family
ID=41185209
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008054870A Expired - Fee Related JP4951555B2 (ja) | 2008-03-05 | 2008-03-05 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4951555B2 (ja) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03268347A (ja) * | 1990-03-16 | 1991-11-29 | Hitachi Ltd | 半導体装置 |
JPH05263288A (ja) * | 1992-03-18 | 1993-10-12 | Fujitsu Ltd | 電気めっき方法 |
JPH1012800A (ja) * | 1996-06-19 | 1998-01-16 | Unisia Jecs Corp | 半導体素子の接続装置 |
JP2003031610A (ja) * | 2001-07-16 | 2003-01-31 | Nec Corp | 半導体装置及びそのワイヤーボンディング方法 |
JP2005317830A (ja) * | 2004-04-30 | 2005-11-10 | Elpida Memory Inc | 半導体装置、マルチチップパッケージ、およびワイヤボンディング方法 |
-
2008
- 2008-03-05 JP JP2008054870A patent/JP4951555B2/ja not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03268347A (ja) * | 1990-03-16 | 1991-11-29 | Hitachi Ltd | 半導体装置 |
JPH05263288A (ja) * | 1992-03-18 | 1993-10-12 | Fujitsu Ltd | 電気めっき方法 |
JPH1012800A (ja) * | 1996-06-19 | 1998-01-16 | Unisia Jecs Corp | 半導体素子の接続装置 |
JP2003031610A (ja) * | 2001-07-16 | 2003-01-31 | Nec Corp | 半導体装置及びそのワイヤーボンディング方法 |
JP2005317830A (ja) * | 2004-04-30 | 2005-11-10 | Elpida Memory Inc | 半導体装置、マルチチップパッケージ、およびワイヤボンディング方法 |
Also Published As
Publication number | Publication date |
---|---|
JP4951555B2 (ja) | 2012-06-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10211159B2 (en) | Semiconductor packages having semiconductor chips disposed in opening in shielding core plate | |
US9377825B2 (en) | Semiconductor device | |
US7009303B2 (en) | Multi-chip module | |
JP4588027B2 (ja) | スタック式電子アセンブリ | |
US10593617B2 (en) | Semiconductor device | |
JP2017022241A (ja) | 半導体装置及び電子機器 | |
JP2010278318A (ja) | 半導体装置 | |
JP2007027287A (ja) | 半導体装置およびその製造方法 | |
JP2016012693A (ja) | 半導体装置 | |
JP4033968B2 (ja) | 複数チップ混載型半導体装置 | |
KR20070005745A (ko) | 이원 접속 방식을 가지는 반도체 패키지 및 그 제조 방법 | |
KR101407614B1 (ko) | 인쇄회로기판, 반도체 패키지, 카드 및 시스템 | |
US8169066B2 (en) | Semiconductor package | |
US8823185B2 (en) | Semiconductor packages | |
JP4951555B2 (ja) | 半導体装置の製造方法 | |
KR101252305B1 (ko) | 멀티칩 모듈 | |
JP2016167523A (ja) | 半導体装置および電子機器 | |
US20210407972A1 (en) | Semiconductor package and method of fabricating the same | |
JP5166903B2 (ja) | 半導体装置 | |
JP4174008B2 (ja) | 半導体装置 | |
JPH05136312A (ja) | 半導体装置 | |
JP2023031660A (ja) | 半導体装置及び電子機器 | |
JP5770258B2 (ja) | 半導体装置の製造方法 | |
US20070297146A1 (en) | Data Communications with an Integrated Circuit | |
JPH02198163A (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20100528 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110217 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110217 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120206 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120214 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120312 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150316 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |