JP2009158853A - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
JP2009158853A
JP2009158853A JP2007338047A JP2007338047A JP2009158853A JP 2009158853 A JP2009158853 A JP 2009158853A JP 2007338047 A JP2007338047 A JP 2007338047A JP 2007338047 A JP2007338047 A JP 2007338047A JP 2009158853 A JP2009158853 A JP 2009158853A
Authority
JP
Japan
Prior art keywords
layer
impurity
impurity diffusion
channel
channel layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007338047A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009158853A5 (https=
Inventor
Akira Sotozono
明 外園
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2007338047A priority Critical patent/JP2009158853A/ja
Priority to US12/340,027 priority patent/US7985985B2/en
Publication of JP2009158853A publication Critical patent/JP2009158853A/ja
Publication of JP2009158853A5 publication Critical patent/JP2009158853A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2007338047A 2007-12-27 2007-12-27 半導体装置 Pending JP2009158853A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007338047A JP2009158853A (ja) 2007-12-27 2007-12-27 半導体装置
US12/340,027 US7985985B2 (en) 2007-12-27 2008-12-19 Semiconductor device and method of fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007338047A JP2009158853A (ja) 2007-12-27 2007-12-27 半導体装置

Publications (2)

Publication Number Publication Date
JP2009158853A true JP2009158853A (ja) 2009-07-16
JP2009158853A5 JP2009158853A5 (https=) 2010-04-15

Family

ID=40797038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007338047A Pending JP2009158853A (ja) 2007-12-27 2007-12-27 半導体装置

Country Status (2)

Country Link
US (1) US7985985B2 (https=)
JP (1) JP2009158853A (https=)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8154077B2 (en) 2010-02-02 2012-04-10 Kabushiki Kaisha Toshiba Semiconductor device
JP2013545315A (ja) * 2010-12-06 2013-12-19 インターナショナル・ビジネス・マシーンズ・コーポレーション 高Ｋ／金属ゲートＭＯＳＦＥＴを有するＶｔ調整及び短チャネル制御のための構造体及び方法。
JP2016516298A (ja) * 2013-03-14 2016-06-02 インテル・コーポレーション ナノワイヤトランジスタのリーク低減構造
KR20170019541A (ko) * 2015-08-11 2017-02-22 삼성전자주식회사 3차원 반도체 메모리 장치

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5682185B2 (ja) 2010-09-07 2015-03-11 ソニー株式会社 半導体パッケージおよび半導体パッケージの製造方法ならびに光学モジュール
US9660049B2 (en) * 2011-11-03 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor transistor device with dopant profile
US9209181B2 (en) 2013-06-14 2015-12-08 Globalfoundries Inc. Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures
KR102104062B1 (ko) * 2013-10-31 2020-04-23 삼성전자 주식회사 기판 구조체, 이를 포함한 ｃｍｏｓ 소자 및 ｃｍｏｓ 소자 제조 방법
US9246002B2 (en) 2014-03-13 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for semiconductor device
US10103064B2 (en) 2014-05-28 2018-10-16 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor structure including epitaxial channel layers and raised source/drain regions
US20190131454A1 (en) * 2017-11-01 2019-05-02 Qualcomm Incorporated Semiconductor device with strained silicon layers on porous silicon
JP7150524B2 (ja) 2018-08-24 2022-10-11 キオクシア株式会社 半導体装置
US11616058B2 (en) 2020-12-10 2023-03-28 Texas Instruments Incorporated Semiconductor device with diffusion suppression and LDD implants and an embedded non-LDD semiconductor device
CN116344590B (zh) * 2023-05-23 2023-09-12 合肥晶合集成电路股份有限公司 一种半导体器件及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06326306A (ja) * 1993-04-29 1994-11-25 Samsung Electron Co Ltd Ｍｏｓトランジスタおよびその製造方法
JPH11500873A (ja) * 1995-12-15 1999-01-19 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ ＳｉＧｅ層を具えた半導体電界効果デバイス
JP2000031481A (ja) * 1998-07-15 2000-01-28 Nec Corp 半導体装置およびその製造方法
JP2000077654A (ja) * 1998-09-03 2000-03-14 Matsushita Electric Ind Co Ltd 電界効果型半導体装置およびその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6426279B1 (en) * 1999-08-18 2002-07-30 Advanced Micro Devices, Inc. Epitaxial delta doping for retrograde channel profile
US20050104092A1 (en) * 2003-11-19 2005-05-19 International Business Machiness Corportion Method of reducing dislocation-induced leakage in a strained-layer field-effect transistor
KR101594335B1 (ko) * 2007-12-03 2016-02-16 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06326306A (ja) * 1993-04-29 1994-11-25 Samsung Electron Co Ltd Ｍｏｓトランジスタおよびその製造方法
JPH11500873A (ja) * 1995-12-15 1999-01-19 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ ＳｉＧｅ層を具えた半導体電界効果デバイス
JP2000031481A (ja) * 1998-07-15 2000-01-28 Nec Corp 半導体装置およびその製造方法
JP2000077654A (ja) * 1998-09-03 2000-03-14 Matsushita Electric Ind Co Ltd 電界効果型半導体装置およびその製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8154077B2 (en) 2010-02-02 2012-04-10 Kabushiki Kaisha Toshiba Semiconductor device
JP2013545315A (ja) * 2010-12-06 2013-12-19 インターナショナル・ビジネス・マシーンズ・コーポレーション 高Ｋ／金属ゲートＭＯＳＦＥＴを有するＶｔ調整及び短チャネル制御のための構造体及び方法。
JP2016516298A (ja) * 2013-03-14 2016-06-02 インテル・コーポレーション ナノワイヤトランジスタのリーク低減構造
US9825130B2 (en) 2013-03-14 2017-11-21 Intel Corporation Leakage reduction structures for nanowire transistors
KR20170019541A (ko) * 2015-08-11 2017-02-22 삼성전자주식회사 3차원 반도체 메모리 장치
KR102437779B1 (ko) * 2015-08-11 2022-08-30 삼성전자주식회사 3차원 반도체 메모리 장치

Also Published As

Publication number Publication date
US7985985B2 (en) 2011-07-26
US20090166685A1 (en) 2009-07-02

Similar Documents

Publication Publication Date Title
JP2009158853A (ja) 半導体装置
US7888747B2 (en) Semiconductor device and method of fabricating the same
JP5028093B2 (ja) 半導体製造用のゲート電極ドーパント活性化方法
US7037773B2 (en) Method of manufacturing metal-oxide-semiconductor transistor
US20100012988A1 (en) Metal oxide semiconductor devices having implanted carbon diffusion retardation layers and methods for fabricating the same
US8709896B2 (en) Semiconductor device and fabrication method
JP2011171706A (ja) トランジスタ及びその製造方法
US6743704B2 (en) Method of manufacturing a semiconductor device
JP2009099702A (ja) 半導体装置及びその製造方法
US20100003799A1 (en) Method for forming p-type lightly doped drain region using germanium pre-amorphous treatment
JP4299866B2 (ja) 半導体装置の製造方法
JP3998665B2 (ja) 半導体装置およびその製造方法
US7148130B2 (en) Semiconductor device and method of manufacturing the same
JP2005150267A (ja) 半導体装置とその製造方法
JPWO2007026677A1 (ja) 半導体装置の製造方法
US7118977B2 (en) System and method for improved dopant profiles in CMOS transistors
US7365362B2 (en) Semiconductor device and method of fabricating semiconductor device using oxidation
US20080054370A1 (en) Semiconductor device and method of fabricating the same
JPWO2009084376A1 (ja) 半導体装置及びその製造方法
JP2007194277A (ja) 半導体装置の製造方法
JP4828982B2 (ja) 半導体装置の製造方法
JP2000208642A (ja) デュアルゲ―トｍｏｓトランジスタの製造方法。
JP3918218B2 (ja) 半導体装置の製造方法
JP2005175082A (ja) 半導体装置及びその製造方法
JP2007053394A (ja) 半導体装置とその製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100226

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100226

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20111125

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20111205

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120719

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120803

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20121130