JP2013545315A - 高K/金属ゲートMOSFETを有するVt調整及び短チャネル制御のための構造体及び方法。 - Google Patents
高K/金属ゲートMOSFETを有するVt調整及び短チャネル制御のための構造体及び方法。 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
Abstract
【解決手段】 その上部領域内に配置されたウェル領域12Bを有する半導体基板12を含む半導体デバイスが提供される。ウェル領域上に、半導体材料スタック14が配置される。半導体材料スタックは、下から上に、半導体含有バッファ層15及び非ドープ半導体チャネル層16を含み、半導体材料スタックの半導体含有バッファ層は、ウェル領域の上面上に直接配置される。この構造体はまた、非ドープ半導体チャネル層の上面上に直接配置されたゲート材料スタック18も含む。本開示において用いられるゲート材料スタックは、下から上に、高kゲート誘電体層20、仕事関数金属層22及びポリシリコン層24を含む。
【選択図】 図4
Description
12:半導体基板
12A:半導体基板12の下部領域
12B:ウェル領域
14、118、118’:半導体材料スタック
15:半導体含有バッファ層
16:非ドープ半導体含有チャネル層
18:ゲート材料スタック
18’:パターン形成されたゲート・スタック
20、112、112’:高kゲート誘電体層
22、114、114’:仕事関数金属層
24、116、116’:ポリシリコン層
26:内側スペーサ
28:延長領域
30:外側スペーサ
32、126、126’:ソース/ドレイン領域
100:CMOS構造体
102:pFETデバイス領域
103:分離領域
104:nFETデバイス領域
106、106’:ウェル領域
108:pFET
110:nFET
120:非ドープ半導体含有バッファ層
120’:非ドープ又はドープ半導体含有バッファ層
122、122’:非ドープ半導体含有チャネル層
124、124’:ソース/ドレイン延長領域
Claims (25)
- その上部領域内に配置されたウェル領域12Bを有する半導体基板12と、
下から上に、半導体含有バッファ層15及び非ドープ半導体含有チャネル層16を含む半導体材料スタック14であって、前記半導体材料スタックの前記半導体含有バッファ層は前記ウェル領域の上面上に直接配置される、半導体材料スタック14と、
前記非ドープ半導体含有チャネル層16の上面上に直接配置され、下から上に、高kゲート誘電体層20、仕事関数金属層22、及びポリシリコン層24を含む、ゲート材料スタック18と、
を含む半導体構造体100。 - 前記ウェル領域はn型ドーパントを含み、かつ、5×1018原子/cm3又はそれより大きいドーパント濃度を有する、請求項1に記載の半導体構造体。
- 前記半導体含有バッファ層は非ドープSiを含み、前記非ドープ半導体含有チャネル層はSiGe合金を含む、請求項2に記載の半導体構造体。
- 前記仕事関数金属層は、シリコン価電子帯端金属を含むpFET仕事関数金属層である、請求項3に記載の半導体構造体。
- 前記シリコン価電子帯端金属は、Pt、Rh、Ir、Ru、Cu、Os、Be、Co、Pd、Te、Cr、Ni、TiN、又はこれらの合金を含む、請求項4に記載の半導体構造体。
- 前記ウェル領域はp型ドーパントを含み、かつ、5×1018原子/cm3又はそれより大きいドーパント濃度を有する、請求項1に記載の半導体構造体。
- 前記半導体含有バッファ層は非ドープ又はp型ドープSiCを含み、前記非ドープ半導体含有チャネル層はSiを含む、請求項6に記載の半導体構造体。
- 前記仕事関数金属層は、シリコン伝導帯端金属を含むnFET仕事関数金属層である、請求項7に記載の半導体構造体。
- 前記シリコン伝導帯端金属は、Hf、Ti、Zr、Cd、La、Tl、Yb、Al、Ce、Eu、Li、Pb、Tb、Ni、In、Lu、Sm、V、Zr、Ga、Mg、Gd、TiAl、又はこれらの合金を含む、請求項8に記載の半導体構造体。
- 内部に配置された少なくとも1つのpFETデバイス領域102及び少なくとも1つのnFETデバイス領域104を有する半導体基板12を含み、
前記少なくとも1つのpFETデバイス領域は、前記半導体基板12の上部領域内に配置されたnウェル領域106と、下から上に、第1の非ドープ半導体含有バッファ層120及び第1の非ドープ半導体含有チャネル層122を含む第1の半導体材料スタックであって、第1の半導体材料スタックの前記第1の非ドープ半導体含有バッファ層は前記nウェル領域106の上面上に直接配置される、第1の半導体材料スタック118と、前記第1の非ドープ半導体含有チャネル層の上面上に直接配置され、下から上に、第1の高kゲート誘電体層112、pFET仕事関数金属層114及び第1のポリシリコン層116を含むpFETゲート材料スタックとを含み、
前記少なくとも1つのnFETデバイス領域104は、前記半導体基板12の別の上部領域内に配置されたpウェル領域106’と、下から上に、第2の半導体含有バッファ層120’及び第2の非ドープ半導体含有チャネル層122’を含む第2の半導体材料スタックであって、第2の半導体材料スタックの前記第2の半導体含有バッファ層は、前記pウェル領域の上面上に直接配置される、第2の半導体材料スタック118’と、前記第2の非ドープ半導体含有チャネル層の上面上に直接配置され、下から上に、第2の高kゲート誘電体層、nFET仕事関数金属層及び第2のポリシリコン層を含むnFETゲート材料スタックとを含む、半導体構造体100。 - 前記nウェル領域はn型ドーパントを含み、かつ、5×1018原子/cm3又はそれより大きいドーパント濃度を有し、前記pウェル領域はp型ドーパントを含み、かつ、5×1018原子/cm3又はそれより大きいドーパント濃度を有する、請求項10に記載の半導体構造体。
- 前記第1の非ドープ半導体含有バッファ層はSiを含み、前記第1の非ドープ半導体含有チャネル層はSiGe合金を含む、請求項10に記載の半導体構造体。
- 前記pFET仕事関数金属層はシリコン価電子帯端金属を含む、請求項10に記載の半導体構造体。
- 前記シリコン価電子帯端金属は、Pt、Rh、Ir、Ru、Cu、Os、Be、Co、Pd、Te、Cr、Ni、TiN、又はこれらの合金を含む、請求項13に記載の半導体構造体。
- 前記第2の半導体含有バッファ層は非ドープ又はp型ドープSiCを含み、前記第2の非ドープ半導体含有チャネル層はSiを含む、請求項10に記載の半導体構造体。
- 前記nFET仕事関数金属層はシリコン伝導帯端金属を含む、請求項10に記載の半導体構造体。
- 前記シリコン伝導帯端金属は、Hf、Ti、Zr、Cd、La、Tl、Yb、Al、Ce、Eu、Li、Pb、Tb、Ni、In、Lu、Sm、V、Zr、Ga、Mg、Gd、TiAl、又はこれらの合金を含む、請求項16に記載の半導体構造体。
- 半導体構造体100を製造する方法であって、
その上部領域内に配置されたウェル領域12Bを有する半導体基板12を準備することと、
前記ウェル領域の上に半導体材料スタック14を形成することであって、前記半導体材料スタックは、下から上に、半導体含有バッファ層15及び非ドープ半導体含有チャネル層16を含み、前記半導体材料スタックの前記半導体含有バッファ層15は前記ウェル領域の上面上に直接配置される、形成することと、
前記非ドープ半導体含有チャネル層16の上面上に直接ゲート材料スタック18を形成することであって、前記ゲート材料スタックは、下から上に、高kゲート誘電体層20、仕事関数金属層22及びポリシリコン層24を含む、形成することと、
を含む方法。 - 前記ウェル領域は、前記基板の前記上部領域内に5×1019原子/cm3を上回る濃度でn型ドーパントを導入することによって形成される、請求項18に記載の方法。
- 前記半導体材料スタックを形成することは、非ドープSi層を前記半導体含有バッファ層としてエピタキシャルに成長させることと、SiGe合金層を前記非ドープ半導体含有チャネル層としてエピタキシャルに成長させることとを含む、請求項18に記載の方法。
- 前記ゲート材料スタックを形成することは、pFET仕事関数金属層を前記仕事関数金属層として選択し、堆積させることを含み、前記pFET仕事関数金属層はシリコン価電子帯端金属である、請求項18に記載の方法。
- 前記ウェル領域は、前記基板の前記上部領域内に5×1018原子/cm3を上回る濃度でp型ドーパントを導入することによって形成される、請求項18に記載の方法。
- 前記半導体材料スタックを形成することは、非ドープ又はp型ドープSiC層を前記半導体含有バッファ層としてエピタキシャルに成長させることと、Si層を前記非ドープ半導体含有チャネル層としてエピタキシャルに成長させることとを含む、請求項18に記載の方法。
- 前記ゲート材料スタックを形成することは、nFET仕事関数金属層を前記仕事関数金属層として選択し、堆積させることを含み、前記nFET仕事関数金属層はシリコン伝導帯端金属である、請求項18に記載の方法。
- 前記半導体基板の上部領域内に配置された別のウェル領域を準備することと、
前記別のウェル領域の上に別の半導体材料スタックを形成することであって、前記別の半導体材料スタックは、下から上に、別の半導体含有バッファ層及び別の非ドープ半導体含有チャネル層を含み、前記別の半導体材料スタックの前記別の半導体含有バッファ層は前記別のウェル領域の上面上に直接配置される、形成することと、
前記別の非ドープ半導体チャネル層の上面上に直接別のゲート材料スタックを形成することであって、前記別のゲート材料スタックは、下から上に、別の高kゲート誘電体層、別の仕事関数金属層及び別のポリシリコン層を含む、形成することと、
をさらに含む、請求項18に記載の方法。
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PCT/US2011/051675 WO2012078225A1 (en) | 2010-12-06 | 2011-09-15 | STRUCTURE AND METHOD FOR Vt TUNING AND SHORT CHANNEL CONTROL WITH HIGH K/METAL GATE MOSFETs |
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