JP2009148919A - Optical head, its drive method, light emitting device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To take measures for a defective element in each light emitting line. <P>SOLUTION: When a light emitting element 104 is not designated by an element designation means capable of designating the light emitting element 104 to which a drive current Ids is to be supplied, a selection part 108 selects the light emitting element 104 according to a selection signal SEL, and the drive current Ids is supplied to the selected light emitting element 104. When the light emitting element 104 is designated by the element designation means, the selection part 108 selects the light emitting element 104 designated by the element designation means regardless of the selection signal SEL. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an optical head using a light emitting element, a driving method thereof, a light emitting device, and an electronic apparatus.

For example, in an electrophotographic image forming apparatus, a light emitting device in which a plurality of light emitting elements are arranged on a substrate is used as an optical head for forming an electrostatic latent image on an image carrier such as a photosensitive drum. Patent Document 1 discloses a technique in which a plurality of light emission lines in which a plurality of light emitting elements are arranged along the main scanning direction are provided, and the light emission lines that are actually used for exposure of the image carrier are changed according to predetermined conditions. ing.
JP 2005-96259 A

The configuration of Patent Document 1 only switches the light emitting line to be used. For example, even when a light emitting failure element exists in the light emitting line in use, the light emitting element with the light emitting failure has to be used as it is. . Therefore, there has been a problem that it is impossible to eliminate a decrease in light emission intensity or variation caused by the presence of the defective element.
In view of such circumstances, an object of the present invention is to solve the problem of reducing the influence (decrease or variation in light emission intensity) of light emitting elements in each light emitting line.

  In order to solve the above problems, an optical head according to the present invention includes a plurality of element groups each including a plurality of light emitting elements that emit light at a luminance corresponding to a drive current, and two or more light emitting elements belonging to different element groups. Each of the plurality of unit circuits, and a selection signal for selecting one of the element groups is supplied to each unit circuit in common. Current generating means for generating, selecting means for selecting any one of the two or more light emitting elements included in the unit circuit, and drive current supplying means for supplying a driving current to the light emitting elements selected by the selecting means And an element designating means capable of designating any one of the two or more light emitting elements included in the unit circuit, and the selecting means is selected when the light emitting element is not designated by the element designating means. According to signal Select emitting element, if the light-emitting element is designated by the element designation means, chosen independently of the selection signal of the designated light-emitting element.

  According to the above aspect, for example, in the inspection at the time of product shipment, when a light emitting failure element is detected among the light emitting elements of the element group constituting one light emitting line, the light emitting element to which a drive current is to be supplied The light emitting elements of other light emitting lines can be designated by the element designating means. Accordingly, since the light emitting elements of other light emitting lines are selected regardless of the selection signal, it is possible to suppress a decrease in emission intensity and variations in the light emitting lines caused by the presence of defective elements.

  In a preferred aspect of the present invention, it is preferable that the element designating unit has a storage unit that rewritably stores element designating data designating the light emitting element to which the drive current is to be supplied. According to this aspect, for example, when an optical head is used, if a light emission failure is detected in any one of two or more light emitting elements included in a unit circuit, the element designating unit in the unit circuit The contents of the storage unit can be rewritten with element designating data for designating the light emitting element in which no light emission failure is detected. As a result, the light emitting element on which no light emission failure is detected is selected regardless of the selection signal. Accordingly, it is possible to suppress a decrease in light emission intensity or variation in the light emission line, which is caused by the presence of a light emitting element having a poor light emission.

The light emitting device according to the present invention is a light emitting device including an optical head and a control circuit,
The optical head includes a plurality of element groups each including a plurality of light emitting elements that emit light at a luminance corresponding to a driving current, and a plurality of unit circuits each including two or more light emitting elements belonging to different element groups. A selection signal for selecting any element group is commonly supplied to each unit circuit. Each of the plurality of unit circuits includes a current generation unit that generates a drive current and two or more light-emitting elements included in the unit circuit. Selection means for selecting any one of the light emitting elements, and drive current supply means for supplying a drive current to the light emitting elements selected by the selection means, the control circuit for each of the plurality of unit circuits, The element designation data that can designate any one of the two or more light emitting elements included in the unit circuit is supplied to the selection unit, and the selection unit in each of the plurality of unit circuits is configured to emit the light emitting element according to the element designation data. If not specified, it selects the light emitting element in response to the selection signal, if the light-emitting element is designated by the element designation data, chosen independently of the selection signal of the designated light-emitting element. Also in the above aspect, it is preferable that the element designating unit has a storage unit that rewritably stores element designating data designating the light emitting element to which the drive current is to be supplied.

    Next, an electronic apparatus according to the present invention includes the light emitting device exemplified above. The light emitting device according to the present invention is used in various electronic devices. A typical example of the electronic apparatus according to the present invention is an electrophotographic image forming apparatus in which the light emitting device according to each of the above embodiments is used for exposure of an image carrier such as a photosensitive drum. The image forming apparatus includes an image carrier on which a latent image is formed by exposure, a light emitting device of the present invention that exposes the image carrier, and a developer (for example, toner) added to the latent image on the image carrier. A developing device to be formed.

  Furthermore, the above-described invention can also be understood as a method for controlling an optical head. That is, a plurality of element groups each including a plurality of light emitting elements that emit light with luminance according to a drive current, and a plurality of unit circuits each including two or more light emitting elements belonging to different element groups, A selection signal for selecting the element group is commonly supplied to each unit circuit, and each of the plurality of unit circuits includes any one of current generation means for generating a drive current and two or more light emitting elements included in the unit circuit. And an element designating unit capable of designating the light emitting element, and when the light emitting element is not designated by the element designating unit, the light emitting element is selected according to the selection signal and the light emission is performed. A driving current is supplied to the element, and when the light emitting element is designated by the element designating means, the designated light emitting element is selected regardless of the selection signal, and the driving current is supplied to the light emitting element. DoThe same effect as that of the optical head according to the present invention can be obtained by the above control method.

<A: First Embodiment>
FIG. 1 is a perspective view showing a partial configuration of an image forming apparatus using the light emitting device 10 according to the first embodiment of the present invention. As shown in FIG. 1, the image forming apparatus includes a light emitting device 10, a condensing lens array 11, and a photosensitive drum (image carrier) 12. The light emitting device 10 includes a large number of light emitting elements (not shown in FIG. 1) arranged linearly on the surface of the substrate 13. These light emitting elements selectively emit light according to the form of an image to be printed on a recording material such as paper. The photosensitive drum 12 is supported by a rotating shaft extending in the main scanning direction, and rotates in the sub-scanning direction in which the recording material is conveyed with the outer peripheral surface facing the light emitting device 10.

  The condensing lens array 11 is disposed in the gap between the light emitting device 10 and the photosensitive drum 12. The condensing lens array 11 includes a large number of gradient index lenses arranged in an array with each optical axis directed toward the light emitting device 10. As the condensing lens array 11, for example, there is SLA (Selfoc Lens Array) available from Nippon Sheet Glass Co., Ltd. (Selfoc / SELFOC is a registered trademark of Nippon Sheet Glass Co., Ltd.).

  Light emitted from each light emitting element of the light emitting device 10 passes through each gradient index lens of the condensing lens array 11 and reaches the surface of the photosensitive drum 12. By this exposure, a latent image (electrostatic latent image) corresponding to a desired image is formed on the surface of the photosensitive drum 12.

FIG. 2 is a diagram illustrating a schematic configuration of the light emitting device 10. The light emitting device 10 includes an optical head 100 and a control circuit 200. As shown in FIG. 2, the optical head 100 has a structure in which a shift register 102 and n unit circuits U (U _{1 to} U _n ) are arranged on the surface of the substrate 13. A start pulse SP and a clock signal CLK are supplied from the control circuit 200 to the shift register 102. The shift register 102 sequentially shifts the start pulse SP according to the clock signal CLK and transfers it to each unit circuit U. At this time, a signal transferred from the shift register to each unit circuit U is referred to as a latch pulse signal LATi (i = 1 to n).

  As shown in FIG. 2, each unit circuit U includes a first light emitting element 104 a and a second light emitting element 104 b that emit light with a luminance corresponding to the driving current, a driving unit 106 that generates a driving current, A selection unit 108 that selects any one of the light emitting elements 104a and 104b to which a driving current is to be supplied, and element designation data SD that can designate the light emitting element 104 that is to be supplied with a driving current. A memory 110 to be stored and a drive current supply unit 112 that supplies a drive current to the light emitting element 104 selected by the selection unit 108 are included. As shown in FIG. 2, a set of n first light emitting elements 104a in each unit circuit U constitutes an element group G1 (one light emitting line), and n second light emitting elements in each unit circuit U. A group of 104b constitutes an element group G2 (the other light emitting line).

To the drive unit 106 in each unit circuit U (U _{1 to} U _n ), gradation data D specifying the gradation of each light emitting element 104 is supplied from the control circuit 200 via the gradation data line 300. The selection unit 108 in each unit circuit U (U _{1 to} U _n ) receives a selection signal SEL for selecting one of the element groups G1 and G2 (light emission line) from the element groups G1 and G2. Commonly supplied from the control circuit 200 via the line 400. In the memory 110 in each unit circuit U (U _{1 to} U _n ), element designation data SD that can designate the light emitting element 104 to which the drive current is to be supplied is supplied from the control circuit 200 via the data line 500. The selection unit 108 in each unit circuit U (U _{1 to} U _n ) selects the light emitting element 104 to which a drive current is to be supplied based on the element designation data SD and the selection signal SEL stored in the memory 110.

Figure 3 is a block diagram showing a detailed electrical configuration of the unit circuit U _1. Other unit circuit U ₂ ~U _n has the same configuration as the unit circuit U _1, here illustrating a unit circuit U ₁ as an example.
As shown in FIGS. 2 and 3, the unit circuit _{U 1} includes a first light emitting element 104a and the second light emitting element 104b, a driving unit 106, a selection unit 108, a memory 110 (110a, 110b), A drive current supply unit 112, a first selection circuit 114, and a second selection circuit 116 are included.

As shown in FIG. 3, the latch pulse signal LAT1 transferred from the shift register 102 in the unit circuit _{U 1} is supplied to the first selection circuit 114 and second selection circuit 116. A write enable signal WE1 is supplied from the control circuit 200 to the first selection circuit 114, and a write enable signal WE2 is supplied from the control circuit 200 to the second selection circuit 116. When the write enable signal WE1 becomes H level, the first selection circuit 114 takes in the element designation data SD (SD1, SD2) from the data line 500 when the latch pulse signal LAT1 is supplied, and the element designation data SD ( SD1, SD2) are supplied to the memory 110. The memory 110 includes a first memory 110a and a second memory 110b. In this embodiment, these memories 110 are configured as rewritable nonvolatile memories. The first element designation data SD1 is written to the first memory 110a, and the second element designation data SD2 is written to the second memory 110b. The first element designation data SD1 and the second element designation data SD2 are each 1-bit data. On the other hand, when the write enable signal WE2 becomes H level, the second selection circuit 114 supplies the latch pulse signal LAT1 to the drive unit 106.

  The driving unit 106 includes a switching transistor Tw and a driving transistor Td. When the latch pulse signal LAT1 from the second selection circuit 116 is supplied to the gate of the switching transistor Tw, the switching transistor Tw is turned on. When the switching transistor Tw is turned on, a potential corresponding to the gradation data D from the gradation data line 300 is supplied to the gate of the driving transistor Td. In the drive transistor Td, a drive current Ids corresponding to the gate-source voltage is generated. The drive current Ids generated by the drive transistor Td is supplied to the drive current supply unit 112.

  The drive current supply unit 112 includes a first transistor Te1 and a second transistor Te2. When the first transistor Te1 is turned on, the driving current Ids is supplied to the first light emitting element 104a. When the second transistor Te2 is turned on, the driving current Ids is supplied to the second light emitting element 104b. . Which of the first transistor Te1 and the second transistor Te2 is turned on depends on the selection operation by the selection unit 108. This operation will be described later.

  The selection unit 108 is based on the first element designation data SD1 stored in the first memory 110a, the second element designation data SD2 stored in the second memory 110b, and the selection signal SEL. The light emitting element 104 to which the drive current Ids is to be supplied is selected from the first light emitting element 104a and the second light emitting element 104b. As illustrated in FIG. 3, the selection unit 108 includes an AND circuit 120, first to third inverters INV1 to INV3, a first switch SW1, and a second switch SW2. The AND circuit 120 outputs a logical product of the inverted signal of the first element designation data SD1 supplied from the first memory 110a and the selection signal SEL supplied from the selection signal line 400. The first switch SW1 is means for determining whether or not to supply the output of the AND circuit 120 inverted by the first inverter INV1 to the point Z shown in FIG. The second switch SW2 is means for determining whether or not the output of the AND circuit can be supplied to the Z point shown in FIG.

  The second element designating data SD2 is supplied from the second memory 110b to the first switch SW1. When the second element designation data SD2 is at a high level, the first switch SW1 is turned on. When the second element designation data SD2 is at a low level, the first switch SW1 is turned off. The second element designation data SD2 inverted by the second inverter INV2 is supplied to the second switch SW2. When the inverted signal of the second element designating data SD2 is at a high level, the second switch SW2 is turned on. When the inverted signal of the second element designating data SD2 is at a low level, the second switch SW2 is turned off. It becomes. In other words, one of the first switch SW1 and the second switch SW2 is turned on by the second element designation data SD2 supplied from the second memory 110b. When the first switch SW1 is turned on, the output of the first inverter INV1 is supplied to the point Z shown in FIG. 3 via the switch SW1. On the other hand, when the second switch SW2 is turned on, the output of the AND circuit 120 is supplied to the point Z shown in FIG. 3 via the switch SW2.

  The signal supplied to the point Z shown in FIG. 3 is supplied to the gate of the first transistor Te1 of the drive current supply unit 112, inverted by the third inverter INV3, and supplied to the gate of the second transistor Te2. The If the signal supplied to the Z point is at a high level, the first transistor Te1 is turned on and the second transistor Te2 is turned off. On the other hand, if the signal supplied to the point Z is at a low level, the first transistor Te1 is turned off and the second transistor Te2 is turned on.

  The element designation data SD stored in the memory 110 of each unit circuit U includes a state in which neither the first light emitting element 104a nor the second light emitting element 104b is designated (hereinafter referred to as “non-designated state”), The selection unit 108 is selectively instructed to designate either the light emitting element 104a or the second light emitting element 104b. More specifically, when both the first element designation data SD1 and the second element designation data SD2 are designated at a low level (“0”), the non-designated state is instructed to the selection unit 108. On the other hand, when both the first element designation data SD1 and the second element designation data SD2 are set to a high level (“1”), designation of the first light emitting element 104a is instructed to the selection unit 108. . In addition, when the first element designation data SD1 is set to the high level and the second element designation data SD2 is set to the low level, the selection unit 108 is instructed to designate the second light emitting element 104b.

  When a defect is detected in any one of the first light emitting element 104a and the second light emitting element 104b in the i-th unit circuit Ui (i = 1 to n), the element designation data SD of the unit circuit Ui is detected. Is set to designate the other light emitting element 104. For example, the element designation data SD is set in advance according to the result of measuring the luminance of each light emitting element 104 in the process of manufacturing the light emitting device 10, and then stored in a storage device (not shown). That is, when the measured luminance value of the i-th light emitting element 104 belonging to one of the element group G1 and the element group G2 is lower than a predetermined reference value, the i-th light emission belonging to the other of the element group G1 and the element group G2. Element designation data SD of the i-th unit circuit Ui is created so as to designate the element 104. In addition, when the luminance of any light emitting element 104 of the unit circuit Ui exceeds the reference value, the element designation data SD of the unit circuit Ui is set so as to indicate a non-designated state.

  The control circuit 200 sets the write enable signal WE1 to a high level at a predetermined time (for example, when the light emitting device 10 is turned on), reads the element designation data SD stored in the storage device, and serially sets the data line. Output to 500. The element designation data SD corresponding to each unit circuit U is sequentially taken into the unit circuit U according to the latch signals LAT1 to LATn and stored in the memory 110.

  Next, specific operations of the unit circuit U (in particular, the selection unit 108 and the drive current supply unit 112) will be described. FIG. 4 shows a unit when the element designation data SD is not designated (the first element designation data SD1 and the second element designation data SD2 are both at low level) and the selection signal SEL is set at high level. 3 is a diagram schematically showing a state of a circuit U. FIG. As shown in FIG. 4, the AND circuit 120 includes an inversion signal (that is, a high level) of the low-level first element designation data SD <b> 1 and a high-level selection signal SEL supplied from the selection signal line 400. The output of the AND circuit 120 becomes high level. The first switch SW1 is turned off when low-level second element designation data SD2 is supplied from the second memory 110b. The second switch SW2 is turned on when an inverted signal of the low-level second element designation data SD2, that is, a high-level signal, is supplied from the second inverter INV2. Therefore, the high level output of the AND circuit 120 is supplied to the point Z via the switch SW2. As a result, the first transistor Te1 is turned on, and the second transistor Te2 is turned off. Accordingly, the drive current Ids is supplied to the first light emitting element 104a via the first transistor Te1.

  FIG. 5 shows a unit when the element designation data SD is in the non-designated state (both the first element designation data SD1 and the second element designation data SD2 are low level) and the selection signal SEL is set to the low level. 3 is a diagram schematically showing a state of a circuit U. FIG. As shown in FIG. 5, both the first element designation data SD1 written in the first memory 110a and the second element designation data SD2 written in the second memory 110b are set to the low level, and the selection signal SEL is set to a low level. In this case, as shown in FIG. 5, a low level signal is supplied to the gate of the first transistor Te1 to be turned off, and a high level signal is supplied to the gate of the second transistor Te2 to turn it on. It becomes a state. Accordingly, the drive current Ids is supplied to the second light emitting element 104b via the second transistor Te2.

  As described above, when the light emitting element 104 is not designated by the element designation data SD, the selection unit 108 selects the light emitting element 104 according to the selection signal SEL as shown in FIGS. That is, when the selection signal SEL is at a high level, the first light emitting element 104a is selected, and when the selection signal SEL is at a low level, the second light emitting element 104b is selected.

  FIG. 6 schematically shows the state of the unit circuit U when the first light emitting element 104a is designated by the element designation data SD (both the first element designation data SD1 and the second element designation data SD2 are at a high level). FIG. In this case, as shown in FIG. 6, since the AND circuit 120 is supplied with a low level signal obtained by inverting the first element designation data SD1, the output of the AND circuit 120 is the selection signal SEL being at the high level. It becomes low level regardless of whether it is low level or not.

  The first switch SW1 is turned on when the high-level second element designation data SD2 is supplied from the second memory 110b. The second switch SW2 is turned off when a signal obtained by inverting the second element designation data SD2 from the second inverter INV, that is, a low-level signal is supplied. Therefore, the output (high level signal) of the AND circuit 120 inverted by the first inverter INV1 is supplied to the Z point. As a result, the first transistor Te1 is turned on, and the second transistor Te2 is turned off. Accordingly, the drive current Ids is supplied to the first light emitting element 104a via the first transistor Te1.

  FIG. 7 shows the state of the unit circuit U when the second light emitting element 104b is designated by the element designation data SD (the first element designation data SD1 is high level and the second element designation data SD2 is low level). It is a figure shown typically. In this case, as shown in FIG. 7, regardless of the selection signal SEL, a low level signal is supplied to the gate of the first transistor Te1, and the gate is turned off. Is turned on. Accordingly, the drive current Ids is supplied to the second light emitting element 104b via the second transistor Te2.

  As described above, when the light emitting element 104 is designated by the element designation data SD, the selection unit 108 determines that the designated light emitting element 104 is not related to the selection signal SEL, as shown in FIGS. Select According to the configuration of the present embodiment, when the light emitting element 104 of one element group G includes a light emitting failure element, the element designation data SD is set so as to designate the light emitting element 104 of the other element group G. be able to. As a result, the defective element is not selected in accordance with the selection signal SEL, and the designated light-emitting element 104 is selected regardless of the selection signal SEL. Therefore, the influence of the defective element (decrease in emission intensity or variation). Can be reduced.

  In the present embodiment, since the memory 110 is configured to be rewritable, for example, when a light emission failure of any one of the light emitting elements 104 is detected in the unit circuit Ui during the operation of the light emitting device 10, the light emission failure. The element designating data SD designating the other light emitting element 104 in which no is detected can be supplied to the memory 110 in the unit circuit Ui, and the content held in the memory 110 can be rewritten to the element designating data SD. As a result, the light emitting element 104 designated by the element designation data SD is selected regardless of the selection signal SEL. Accordingly, it is possible to reduce the influence (such as a decrease in emission intensity and variation) of a light emitting element having a poor light emission.

<B: Second Embodiment>
The present embodiment is different from the first embodiment in that the memory 110 is not used for specifying the light emitting element 104. FIG. 8A is a schematic configuration diagram of a first potential setting unit 600a used instead of the first memory 110a. The first potential setting unit 600a includes a wiring C1 extending from the reference power supply VDD to the ground potential GND. The wiring C1 is connected to the input side of the AND circuit 120 via a connection point Y1 provided in the middle of the wiring C1. As shown in FIG. 8A, a resistor r1 is provided on the path from the connection point Y1 to the ground potential GND. FIG. 8B is a schematic configuration diagram of a second potential setting unit 600b used instead of the second memory 110b. The second potential setting unit 600b includes a wiring C2 extending from the reference power supply VDD to the ground potential GND. The wiring C2 is connected to the first switch SW1 and the second inverter INV2 via a connection point Y2 provided in the middle of the wiring C2. A resistor r2 is provided in a path from the connection point Y2 to the ground potential GND.

  The first potential setting unit 600a and the second potential setting unit 600b selectively select a non-designated state and a state in which one of the first light emitting element 104a and the second light emitting element 104b is designated. To instruct. More specifically, it is selected when both the output of the first potential setting unit 600a and the output of the second potential setting unit 600b are set to a low level (the potentials at the connection point Y1 and the connection point Y2 are 0). A non-designated state is instructed to the unit 108. On the other hand, when both the output of the first potential setting unit 600a and the output of the second potential setting unit 600b are set to a high level (the potential at the connection point Y1 and the connection point Y2 is VDD), the first light emission is performed. The selection of the element 104a is instructed to the selection unit 108. In addition, when the output of the first potential setting unit 600a is set to a high level and the output of the second potential setting unit 600b is set to a low level, the designation of the second light emitting element 104b is given to the selection unit 108. Instructed.

  When the non-designated state is instructed, in the first potential setting unit 600a, the path from the reference power supply VDD to the connection point Y1 in the wiring C1 is laser-cut as shown in FIG. 8C. As a result, the potential at the connection point Y1 becomes 0V, and the potential supplied to the AND circuit 120 also becomes 0V. Therefore, a low level signal is supplied to the AND circuit 120a. In the second potential setting unit 600b, as shown in FIG. 8D, the path from the reference power supply VDD to the connection point Y2 in the wiring C2 is laser cut. As a result, the potential at the connection point Y2 becomes 0V, and the potential supplied to the first switch SW1 and the second inverter INV2 also becomes 0V. Therefore, a low level signal is supplied to the first switch SW1 and the second inverter INV2. Then, as shown in FIGS. 4 and 5, the light emitting element 104 is selected according to the selection signal SEL.

  Next, a case where the first light emitting element 104a is designated will be described. In this case, the first potential setting unit 600a is configured as shown in FIG. 8A, the potential at the connection point Y1 becomes the potential VDD supplied from the reference power supply VDD, and the potential VDD is supplied to the AND circuit 120. . As a result, a high level signal is supplied to the AND circuit 120. Further, the second potential setting unit 600b is configured as shown in FIG. 8B, and the potential at the connection point Y2 becomes the potential VDD supplied from the reference power supply VDD, and the potential VDD is the first switch SW1 and the second switch. To the inverter INV2. Thus, a high level signal is supplied to the first switch SW1 and the second inverter INV2. Then, as shown in FIG. 6, the first light emitting element 104a is selected regardless of the selection signal SEL.

  Next, a case where the second light emitting element 104b is designated will be described. In this case, the first potential setting unit 600a is configured as shown in FIG. 8A, and a high level signal is supplied to the AND circuit 120. Further, the second potential setting unit 600b is configured as shown in FIG. 8D, and a low level signal is supplied to the first switch SW1 and the second inverter INV2. Then, as shown in FIG. 7, the second light emitting element 104b is selected regardless of the selection signal SEL.

  According to the configuration of this embodiment, in the configuration in which the memory 110 is not provided, the selection unit 108 selectively selects a non-designated state and a state in which one of the first light-emitting element 104a and the second light-emitting element 104b is designated. Can be instructed. As will be understood from the description of the first and second embodiments, in a specific aspect of the present invention, the configuration of the light emitting element 104 (element specifying means) to which the drive current Ids should be supplied is arbitrary. It is.

<C: Modification>
The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible. Also, two or more of the modifications shown below can be combined.

(1) Modification 1
In each of the above-described embodiments, the selection unit 108 has the configuration illustrated in FIG. 3, but is not limited thereto, and the configuration of the selection unit 108 is arbitrary. In short, the selection unit 108 selects the light emitting element 104 according to the selection signal SEL when the light emitting element 104 is not designated by the element designating unit (for example, the memory 110 or the potential setting unit 600), and the light emitting element 104 is selected by the element designating unit. If 104 is designated, it is sufficient if it has a function of selecting the designated light emitting element 104 regardless of the selection signal SEL.

(2) Modification 2
In the first embodiment described above, the memory 110 is configured by a non-volatile memory. However, the present invention is not limited to this. For example, the memory 110 may be configured by a volatile memory. However, if the memory 110 is configured by a nonvolatile memory, there is an advantage that it is not necessary to repeatedly write (refresh) the element designation data SD to the memory 110 during the operation of the light emitting device 10.

(3) Modification 3
The light emitting element 104 may be an OLED element, an inorganic light emitting diode, or an LED (Light Emitting Diode). In short, all elements that emit light in response to supply of electric energy (application of electric field or supply of current) can be used as the light-emitting element 104 of the present invention.

<D: Electronic equipment>
Next, with reference to FIG. 9, an image forming apparatus which is one aspect of the electronic apparatus according to the invention will be described. This image forming apparatus is a tandem type full color image forming apparatus using a belt intermediate transfer body system.

  In this image forming apparatus, four light emitting devices 10K, 10C, 10M, and 10Y each having the same configuration are provided with four photosensitive drums (image carriers) 110K, 110C, and 110M having the same configuration. , 110Y are arranged at positions facing the image forming surface 110. The light emitting devices 10K, 10C, 10M, and 10Y have the same configuration as the light emitting device 10 according to each of the above embodiments.

  As shown in FIG. 9, the image forming apparatus is provided with a driving roller 121 and a driven roller 122, and an endless intermediate transfer belt 120 is wound around these rollers 121 and 122, and an arrow indicates. As shown, the periphery of the rollers 121 and 122 is rotated. Although not shown, tension applying means such as a tension roller that applies tension to the intermediate transfer belt 120 may be provided.

  Around the intermediate transfer belt 120, four photosensitive drums 110K, 110C, 110M, and 110Y each having a photosensitive layer on the outer peripheral surface are arranged at a predetermined interval. The subscripts “K”, “C”, “M”, and “Y” mean that they are used to form black, cyan, magenta, and yellow visible images, respectively. The same applies to other members. The photosensitive drums 110K, 110C, 110M, and 110Y are rotationally driven in synchronization with the driving of the intermediate transfer belt 120.

  Around each photosensitive drum 110 (K, C, M, Y), there is a corona charger 111 (K, C, M, Y), a light emitting device 10 (K, C, M, Y), and a developing unit. 114 (K, C, M, Y) are arranged. The corona charger 111 (K, C, M, Y) uniformly charges the image forming surface 110A (outer peripheral surface) of the corresponding photosensitive drum 110 (K, C, M, Y). The light emitting device 10 (K, C, M, Y) writes an electrostatic latent image on the charged image forming surface 110A of each photosensitive drum. In each light emitting device 10 (K, C, M, Y), a plurality of light emitting elements 20 are arranged along the bus (main scanning direction) of the photosensitive drum 110 (K, C, M, Y). The electrostatic latent image is written by irradiating the photosensitive drum 110 (K, C, M, Y) with light by the plurality of light emitting elements 20. The developing device 114 (K, C, M, Y) has a visible image (that is, a visible image) on the photosensitive drum 110 (K, C, M, Y) by attaching toner as a developer to the electrostatic latent image. ).

  The black, cyan, magenta, and yellow developed images formed by the four-color single-color image forming stations are superimposed on the intermediate transfer belt 120 by being sequentially primary-transferred onto the intermediate transfer belt 120. As a result, a full-color visible image is formed. Four primary transfer corotrons (transfer devices) 112 (K, C, M, Y) are arranged inside the intermediate transfer belt 120. The primary transfer corotron 112 (K, C, M, Y) is disposed in the vicinity of the photosensitive drum 110 (K, C, M, Y), and the photosensitive drum 110 (K, C, M, Y). The electrostatic image is electrostatically attracted from the toner image to transfer the visible image to the intermediate transfer belt 120 passing between the photosensitive drum and the primary transfer corotron.

  A sheet 102 as an object (recording material) on which an image is to be finally formed is fed one by one from the sheet feeding cassette 101 by the pickup roller 103 and is subjected to secondary transfer with the intermediate transfer belt 120 in contact with the driving roller 121. Sent to the nip between the rollers 126. The full-color visible image on the intermediate transfer belt 120 is secondarily transferred to one side of the sheet 102 by the secondary transfer roller 126 and fixed on the sheet 102 through the fixing roller pair 127 as a fixing unit. . Thereafter, the sheet 102 is discharged onto a paper discharge cassette formed in the upper part of the apparatus by a paper discharge roller pair 128.

  Next, another embodiment of the image forming apparatus according to the present invention will be described with reference to FIG. This image forming apparatus is a rotary developing type full-color image forming apparatus using a belt intermediate transfer body system. As shown in FIG. 10, a corona charger 168, a rotary developing unit 161, the light emitting device 10 according to the above embodiment, and an intermediate transfer belt 169 are provided around the photosensitive drum 110. Yes.

  The corona charger 168 uniformly charges the outer peripheral surface of the photosensitive drum 110. The light emitting device 10 writes an electrostatic latent image on the charged image forming surface (outer peripheral surface) of the photosensitive drum 110. In the light emitting device 10, a plurality of light emitting elements 32 are arranged along the bus line (main scanning direction) of the photosensitive drum 110. The electrostatic latent image is written by irradiating the photosensitive drum 110 with light from these light emitting elements 32.

  The developing unit 161 is a drum in which four developing units 163Y, 163C, 163M, and 163K are arranged at an angular interval of 90 °, and can rotate counterclockwise about the shaft 161a. The developing units 163Y, 163C, 163M, and 163K supply yellow, cyan, magenta, and black toner to the photosensitive drum 110, respectively, and attach the toner as a developer to the electrostatic latent image, thereby the photosensitive drum 110. A visible image (ie, a visible image) is formed.

  The endless intermediate transfer belt 169 is wound around a driving roller 170a, a driven roller 170b, a primary transfer roller 166, and a tension roller, and is rotated around these rollers in a direction indicated by an arrow. The primary transfer roller 166 transfers the visible image to the intermediate transfer belt 169 that passes between the photosensitive drum 110 and the primary transfer roller 166 by electrostatically attracting the visible image from the photosensitive drum 110.

  Specifically, in the first rotation of the photosensitive drum 110, an electrostatic latent image for a yellow (Y) image is written by the light emitting device 10, and a developed image of the same color is formed by the developing device 163Y. The image is transferred to the transfer belt 169. Further, in the next rotation, the electrostatic latent image for the cyan (C) image is written by the light emitting device 10A, and a developed image of the same color is formed by the developing device 163C, and the intermediate transfer is performed so as to overlap the yellow developed image. Transferred to the belt 169. Then, while the photosensitive drum 110 rotates four times in this way, the yellow, cyan, magenta, and black visible images are sequentially superimposed on the intermediate transfer belt 169, and as a result, a full-color visible image becomes a transfer belt 169. Formed on top. When images are finally formed on both sides of a sheet as an object on which an image is to be formed, the same color images of the front and back surfaces are transferred to the intermediate transfer belt 169, and then the front and back surfaces are transferred to the intermediate transfer belt 169. A full-color visible image is formed on the intermediate transfer belt 169 in such a manner that the visible image of the next color is transferred.

  The image forming apparatus is provided with a sheet conveyance path 174 through which a sheet passes. The sheets are picked up one by one from the paper feed cassette 178 by the pick-up roller 179, advanced through the sheet transport path 174 by the transport roller, and between the intermediate transfer belt 169 and the secondary transfer roller 171 in contact with the drive roller 170a. Pass through the nip. The secondary transfer roller 171 transfers the developed image to one side of the sheet by electrostatically attracting a full-color developed image from the intermediate transfer belt 169 collectively. The secondary transfer roller 171 can be moved closer to and away from the intermediate transfer belt 169 by a clutch (not shown). The secondary transfer roller 171 is brought into contact with the intermediate transfer belt 169 when a full-color visible image is transferred onto the sheet, and is separated from the secondary transfer roller 171 while the visible image is superimposed on the intermediate transfer belt 169.

  The sheet on which the image has been transferred as described above is conveyed to the fixing device 172 and is passed between the heating roller 172a and the pressure roller 172b of the fixing device 172, whereby the visible image on the sheet is fixed. The sheet after the fixing process is drawn into the discharge roller pair 176 and proceeds in the direction of arrow F. In the case of double-sided printing, after most of the sheet passes through the paper discharge roller pair 176, the paper discharge roller pair 176 is rotated in the reverse direction and introduced into the double-sided printing conveyance path 175 as indicated by an arrow G. The Then, the visible image is transferred to the other surface of the sheet by the secondary transfer roller 171, the fixing process is performed again by the fixing device 172, and then the sheet is discharged by the discharge roller pair 176.

  Since the image forming apparatus illustrated in FIGS. 9 and 10 uses a light source (exposure means) employing an OLED element as the light emitting element 20, the apparatus is made smaller than when a laser scanning optical system is used. . Note that the light-emitting device 10 of the present invention can also be employed in electrophotographic image forming apparatuses other than those exemplified above. For example, the light emitting device according to the present invention is also applied to an image forming apparatus that directly transfers a visible image from a photosensitive drum to a sheet without using an intermediate transfer belt, and an image forming apparatus that forms a monochrome image. 10 can be applied.

  The use of the light emitting device according to the present invention is not limited to exposure of a photoreceptor. For example, the light emitting device of the present invention is employed in an image reading device such as a scanner as a line type optical head (illumination device) that irradiates a reading target such as an original with light. As this type of image reading apparatus, there is a scanner, a copying machine or a reading part of a facsimile, a barcode reader, or a two-dimensional image code reader for reading a two-dimensional image code such as a QR code (registered trademark). In addition, a light-emitting device in which a plurality of light-emitting elements (particularly light-emitting elements) are arranged in a planar shape is also employed as a backlight unit disposed on the back side of a liquid crystal panel. A light-emitting device in which a plurality of light-emitting elements are arranged in a matrix is employed as a display device for various electronic devices.

1 is a perspective view showing a partial configuration of an image forming apparatus according to a first embodiment. It is a figure which shows schematic structure of the light-emitting device which concerns on the same embodiment. 2 is a block diagram showing an electrical configuration of a unit circuit U ₁ according to the same embodiment. FIG. It is a block diagram showing operation of a selection part concerning the embodiment. It is a block diagram showing operation of a selection part concerning the embodiment. It is a block diagram showing operation of a selection part concerning the embodiment. It is a block diagram showing operation of a selection part concerning the embodiment. It is explanatory drawing which shows the specific aspect of 2nd Embodiment. It is a perspective view which shows the specific example (image forming apparatus) of the electronic device which concerns on this invention. It is a perspective view which shows the specific example (image forming apparatus) of the electronic device which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Light-emitting device, 100 ... Optical head, 104 ... Light-emitting element, 106 ... Drive part, 108 ... Selection part, 110 ... Memory, 112 ... Drive current supply part, 200 ... Control circuit, U _{1 to} Un ₌ Unit circuit, SD ... Element designation data, SEL ... Selection signal, Td ... Drive transistor, Ids ... Drive current.

Claims (5)

A plurality of element groups each including a plurality of light emitting elements that emit light at a luminance according to the drive current;
A plurality of unit circuits each including two or more light emitting elements belonging to different element groups,
An optical head in which a selection signal for selecting any one of the element groups is supplied in common to the unit circuits,
Each of the plurality of unit circuits is
Current generating means for generating the drive current;
Selecting means for selecting any one of the two or more light emitting elements included in the unit circuit;
Drive current supply means for supplying the drive current to the light emitting element selected by the selection means;
An element designating unit capable of designating any one of the two or more light emitting elements included in the unit circuit;
The selection means includes
When the light emitting element is not designated by the element designating unit, the light emitting element is selected according to the selection signal,
An optical head that, when the light emitting element is designated by the element designating means, selects the designated light emitting element irrespective of the selection signal. The optical head according to claim 1,
The optical element has a storage unit in which the element specifying means stores rewritable element specifying data specifying any one of the two or more light emitting elements. A light emitting device including an optical head and a control circuit,
The optical head is
A plurality of element groups each including a plurality of light emitting elements that emit light at a luminance according to the drive current;
A plurality of unit circuits each including two or more light emitting elements belonging to different element groups,
A selection signal for selecting any one of the element groups is supplied to the unit circuits in common.
Each of the plurality of unit circuits is
Current generating means for generating the drive current;
Selecting means for selecting any one of the two or more light emitting elements included in the unit circuit;
Drive current supply means for supplying the drive current to the light emitting element selected by the selection means,
The control circuit includes:
For each of the plurality of unit circuits,
Supplying element specifying data capable of specifying any one of the two or more light emitting elements included in the unit circuit to the selection unit;
The selection means in each of the plurality of unit circuits is:
When the light emitting element is not designated by the element designation data, the light emitting element is selected according to the selection signal,
When the light emitting element is designated by the element designation data, the designated light emitting element is selected regardless of the selection signal.   An electronic apparatus comprising the light emitting device according to claim 3. A plurality of element groups each including a plurality of light emitting elements that emit light at a luminance according to the drive current;
A plurality of unit circuits each including two or more light emitting elements belonging to different element groups,
A selection signal for selecting any one of the element groups included in the unit circuit is supplied in common to the unit circuits,
Each of the plurality of unit circuits is
Current generating means for generating the drive current;
An element designating unit capable of designating any one of the two or more light emitting elements included in the unit circuit, and a method of driving an optical head comprising:
When the light emitting element is not designated by the element designating means, the light emitting element is selected according to the selection signal and the driving current is supplied to the light emitting element,
When the light emitting element is designated by the element designating means, the optical head driving method for selecting the designated light emitting element irrespective of the selection signal and supplying the drive current to the light emitting element.

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