JP2006076226A - Light emitting apparatus, its driving method and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a line head whose emission luminance is made uniform. <P>SOLUTION: Blocks B1 to B39 are provided with 89 pixel circuits P1 to P89, and a block B40 is provided with 73 pixel circuits P1 to P73. As distances from supply terminals Ta and Tb are made longer, a power supply impedance is increased. A load is reduced because the pixel circuits are set so that the number of the pixel circuits P1 to P73 included in the block B40 farthest from the supply terminals Ta and Tb. As a result, power supply variation of power supply lines La and Lb is suppressed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a light emitting device using a light emitting element that emits light having a magnitude corresponding to the amount of current, such as an organic light emitting diode element, a driving method thereof, and an image forming apparatus.

In recent years, organic light emitting diodes (hereinafter referred to as “OLED elements”) elements called organic electroluminescence elements and light emitting polymer elements have attracted attention as next-generation light-emitting devices that replace liquid crystal elements. An image forming apparatus using a line head provided with a large number of OLED elements in one line as an exposure means has been developed. In such a line head, a plurality of pixel circuits including an OLED element and a transistor for driving the OLED element are arranged. For example, Patent Document 1 discloses a line head composed of one line of OLED elements.
Here, the plurality of pixel circuits are arranged in one direction, and power is supplied to each pixel circuit via a power supply line. These pixel circuits may be divided into a plurality of blocks and the pixel circuits may be driven in units of blocks. The total number of pixel circuits of the line head is determined according to the resolution and the width of the paper. On the other hand, the number of blocks is appropriately set according to design specifications. For this reason, the number of pixel circuits included in all the blocks is not divided equally, and fractions may occur.
JP-A-4-363264

By the way, when the pixel circuit is driven in units of blocks, the load fluctuates at the timing when the block to be driven is switched. If the impedance of the power supply line is ideally zero, the power supply voltage does not fluctuate even if the load fluctuates.
However, in an actual device, there is a wiring resistance in the power supply line. In addition, in a device in which the length is determined in accordance with the width of the sheet, such as a line head, the length of the power supply line is increased and the wiring resistance is increased. Therefore, the power supply voltage fluctuates in synchronization with the block switching. As described above, when the number of pixel circuits included in each block is not constant, a problem arises in relation to how to handle fractions and fluctuations in power supply voltage.
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a light emitting device capable of reducing fluctuations in power supply voltage, and a control method for the light emitting device. It is in.

  In order to solve the above-described problem, a light-emitting device according to the present invention includes a plurality of pixel circuits each having a light-emitting element and arranged in one direction, and connected to each of the plurality of pixel circuits. And a drive unit that divides the plurality of pixel circuits into a plurality of blocks and drives the pixel circuit for each block, and is adjacent to one end of the power supply line in the adjacent block The number of the pixel circuits included in the side block is set to be equal to or larger than the number of the pixel circuits included in the block far from one end of the power supply line.

  According to the present invention, since the pixel circuit is driven in units of blocks, the size of the load is determined according to the number of pixel circuits included in each block. On the other hand, the impedance of the power line increases as the distance from one end to which power is supplied increases. In the adjacent block, the number of pixel circuits included in the block closer to one end of the power supply line is equal to or larger than the number of pixel circuits included in the block farther from one end of the power supply line. Therefore, the load can be lightened at a location where the power source impedance is large. For this reason, power supply fluctuations can be suppressed and the light emission luminance of the light emitting elements can be made close to each other.

Here, the number of the pixel circuits included in the block farthest from one end of the power supply line is set as K, the number of the pixel circuits included in the other blocks is set as J, and J> K is set. Is preferred. In this case, the load at the highest power supply impedance can be lightened to suppress power supply fluctuations, and the light emission brightness of the light emitting elements can be made close to each other.
The number of the pixel circuits included in the block closest to one end of the power supply line may be L, the number of the pixel circuits included in the other blocks may be all M, and M <L may be set. preferable. In this case, the load at the lowest power supply impedance can be increased so as to suppress power supply fluctuations, and the light emission luminance of the light emitting elements can be made close to each other.

  The light emitting element emits light having a magnitude corresponding to the amount of drive current, and each of the plurality of pixel circuits includes a logic circuit that operates by power supplied from the power supply line, and It is preferable to include a current supply unit that generates the drive current according to a calculation result. In this case, the malfunction of the logic circuit can be prevented by suppressing the fluctuation of the power supply voltage.

  An image forming apparatus according to the present invention includes a photoconductor on which an image is formed by irradiation of light, and a head unit that forms the image by irradiating the photoconductor with light. It is used for the head part. As described above, since the light emitting device can make the light emission luminance of each light emitting element close to uniform, the printing quality can be improved.

  Further, the driving method of the light emitting device according to the present invention includes a plurality of pixel circuits each provided with a light emitting element and arranged in one direction, and connected to each of the plurality of pixel circuits, and power is supplied from one end thereof. A plurality of pixel circuits are divided into a plurality of blocks, and the adjacent blocks are included in a block closer to one end of the power supply line. The number of pixel circuits is set to be equal to or larger than the number of pixel circuits included in a block far from one end of the power supply line, and the pixel circuits are driven for each block. .

Embodiments of the present invention will be described below with reference to the drawings.
<Light emitting device>
FIG. 1 is a block diagram showing a configuration of a light emitting device according to an embodiment of the present invention. The light-emitting device includes a printer head unit 10 as an image forming apparatus and its peripheral circuits. The light emitting device includes a control circuit 20, an image processing circuit 30, and a power supply circuit 40 as peripheral circuits of the head unit 10. The control circuit 20 generates a start pulse signal SP and a clock signal CLK. The start pulse signal SP is a signal that becomes active at the start of the main scanning period. The clock signal CLK gives a time serving as a reference for main scanning. The image processing circuit 30 outputs parallel format data signals D1 to D89. The data signals D1 to D89 in this example are binary signals instructing to turn on / off the OLED element. The power supply circuit 40 generates a high-potential-side power supply signal VHHEL and a low-potential-side power supply signal VSSEL in addition to the logic circuit power supply signals VHH and VSS.

The head unit 10 is a line-type optical head and includes 89 data lines L1 to L89, signal lines Ls1 to Ls40, a shift register 50, pixel blocks B1 to B40, and power supply lines La and Lb. Pixel blocks B1 to B40 are arranged in the X direction. The data lines L1 to L89 and the power supply lines La and Lb are arranged in parallel with the X direction.
The shift register 50 is configured by cascading a plurality of unit shift circuits (not shown), and sequentially shifts the start pulse signal SP according to the clock signal CLK to generate shift signals SR1, SR2,... SR41. As shown in FIG. 2, each of the shift signals SR1 to SR41 is a signal that is active only for a period of one cycle of the clock signal CLK. In addition, the active periods of adjacent shift signals overlap by a half cycle of the clock signal CLK.

The shift signals SR1 to SR41 are supplied to the pixel blocks B1 to B40 via the signal lines Ls1 to Ls41. Each of the pixel blocks B1 to B39 includes 89 pixel circuits P1 to P89, and the pixel block B40 includes 73 pixel circuits P1 to P73. The pixel circuits P1 to P89 have the same configuration. In the following description, when individual pixel circuits are not problematic, they are simply referred to as pixel circuits P.
The high potential power signal VHHEL is supplied to the supply terminal Ta of the power supply line La, while the low potential power signal VSSEL is supplied to the supply terminal Tb of the power supply line Lb. Each pixel circuit P is connected to the power supply lines La and Lb, and receives the power supply of the high potential power signal VHHEL and the low potential power signal VSSEL through them. The pixel block closest to the supply terminals Ta and Tb is B1, and the farthest pixel block is B40.

FIG. 2 shows a detailed configuration of the pixel circuit P, and FIG. 3 shows a timing chart thereof. This pixel circuit P belongs to the first block B1 and is connected to the data line L1. The NOR circuit 60 generates a sampling signal SAM1 that is high during a period from time t2 to time t3 when both the shift signal SR1 and the shift signal SR2 are low (active), and supplies the sampling signal SAM1 to the latch circuit 70.
The latch circuit 70 includes a transfer gate 71, inverters 72 to 74, and a clocked inverter 75. In the period from time t1 to time t2, since the shift signal SR1 is at a low level, the clocked inverter 75 is in a high impedance state. Further, since the sampling signal SAM1 is at a low level, the transfer gate is turned off. As a result, an equivalent circuit of the latch circuit 70 is as shown in FIG.

Next, from time t2 to time t3, the shift signal SR1 is maintained at the low level, but the sampling signal SAM1 is at the high level. At this time, the clocked inverter 75 maintains a high impedance state, while the transfer gate is turned on. As a result, the equivalent circuit of the latch circuit 70 is as shown in FIG. 4B, and the logic level of the data signal D1 is captured.
Next, after time t4, the shift signal SR1 becomes high level, and the clocked inverter 75 operates as an inverter. Further, since the sampling signal SAM1 is at a low level, the transfer gate is turned off. As a result, an equivalent circuit of the data latch circuit 70 is as shown in FIG. In other words, the logic level of the data signal D1 is stored in the latch circuit 70 until the data signal D1 is taken in and the next writing is performed.

  The output signal of the latch circuit 70 is supplied to the node Q via the inverter 82. The gate of the driving transistor 83 and the gate of the control transistor 84 are connected to the node Q. The drive transistor 83 is composed of a P-channel TFT, and the control transistor is composed of an N-channel TFT. A high potential side power supply signal VDDEL is supplied to the drain of the driving transistor 83, and the anode of the OLED element 85 is connected to the source thereof. A low potential side power signal VSSEL is supplied to the cathode of the OLED element 85. The control transistor 84 short-circuits the OLED element 85 in the on state.

  Here, when the logic level of the node Q is low, the drive transistor 83 is turned on and the control transistor 84 is turned off. At this time, the drive current is supplied to the OLED element 85, and the OLED element 85 is lit. On the other hand, when the logic level of the node Q is high, the drive transistor 83 is turned off and the control transistor 84 is turned on. At this time, no driving current is supplied to the OLED element 85, and the OLED element 85 is turned off.

  A transfer gate 80 is provided between the node Q and the input terminal of the inverter 74. The control signal READB is active at a low level. In the active period of this signal, the transfer gate 80 is turned on. At this time, the node Q and the input terminal of the inverter 74 are connected, and the inverter 74 and the inverter 82 form a latch circuit.

In the pixel circuit P described above, the logic level of the node Q is allowed to change when the sample signal SAM1 becomes active. The sample signal SAM1 is similarly generated in the other pixel circuits P belonging to the block B1. Accordingly, the pixel circuits P1 to P89 belonging to the block B1 execute the writing operation at the same time. The same applies to the other blocks B2 to B40. Therefore, the OLED element 85 is turned on / off in units of blocks.
When the pixel circuit P is driven in units of blocks in this way, the potentials of the high potential power signal VHHEL and the low potential power signal VSSEL change in synchronization with the timing at which the signal waveforms of the sample signals SAM1, SAM2,. This is because wiring resistance exists in the power supply lines La and Lb.

  FIG. 5 schematically shows the relationship between the equivalent circuit of the power supply lines La and Lb and the power supply impedance. As shown in this figure, since the wiring resistance R is distributed in the power supply lines La and Lb, the power supply impedance increases as the distance between the supply terminals Ta and Tb increases. The voltage fluctuation of the power supply lines La and Lb is determined by both the load and the power supply impedance. In order to reduce the voltage fluctuation, the load should be reduced as the power supply impedance increases. In this example, the magnitude of the load is determined according to the number of pixel circuits P included in each of the blocks B1 to B40, and the power supply impedance is determined according to the distance from the supply terminals Ta and Tb. Therefore, in order to reduce the voltage fluctuation, it is only necessary to set so that the number of pixel circuits P included in each block does not increase as the distance from the supply terminals Ta and Tb increases. More specifically, in the adjacent blocks Bk (k is a natural number from 1 to 39) and Bk + 1, the number of pixel circuits P included in the block Bk closer to the supply terminals Ta and Tb is the supply terminals Ta and Tb. It is preferable to set so that it is equal to or larger than the number of pixel circuits P included in the block Bk + 1 on the far side.

  In this example, the number of pixel circuits P included in the blocks B1 to B39 is “89”, and the number of pixel circuits P included in the block B40 farthest from the supply terminals Ta and Tb is “73”. Can be lightened, and voltage fluctuations between the high-potential power supply signal VDDEL and the low-potential power supply signal VSSEL can be suppressed. The luminance of the OLED element 85 varies according to the magnitude of the drive current, and the magnitude of the drive current varies according to the voltage between the high potential side power supply signal VDDEL and the low potential side power supply signal VSSEL. Therefore, by suppressing the voltage fluctuation, the light emission luminance of the OLED element 85 in each of the blocks B1 to B40 can be made closer to uniform.

When the number of pixel circuits P included in each of the blocks B1 to B40 is N1 to N40, it may be set as follows.
(1) N1> N2, N2 = N3 =... = N40
For example, N1 = 112, N2 = N3 =... = N40 = 88 may be set. In this case, the number N1 of pixel circuits P included in the block B1 closest to the supply terminals Ta and Tb is larger than the number N2 of pixel circuits included in the other blocks B2 to B40. For this reason, a heavy load is driven at a location where the power source impedance is low. As a result, the voltage fluctuation between the high potential side power supply signal VDDEL and the low potential side power supply signal VSSEL can be suppressed, and the light emission luminance of the OLED element 85 in each of the blocks B1 to B40 can be made close to uniform. . In addition, the number of pixel circuits P included in the blocks B2 to B40 can be the same, and fractions can be combined into the block B1.

(2) N1>N2> N3 ...> N40
In this case, the number of pixel circuits P included in each of the blocks B1 to B30 is decreased as the distance from the supply terminals Ta and Tb is increased. Therefore, since the load becomes lighter as the power supply impedance increases, the light emission luminance of the OLED element 85 in each of the blocks B1 to B40 can be made more uniform.
(3) N1 = N2> N3 = N4... = N40
For example, N1 = N2 = 100, N3 = N4... = N40 = 88 may be set.
(4) N1 = N2... = N38> N39 = N40
For example, N1 = N2... = N38 = 89, N39 = N40 = 81 may be set.

<Image forming apparatus>
FIG. 6 is a vertical side view showing an example of an image forming apparatus using the head unit 10 described above. This image forming apparatus includes four organic EL array exposure heads 10K, 10C, 10M, and 10Y having the same configuration, and four corresponding photosensitive drums (image carriers) 110K, 110C, and 110M having the same configuration. , 110Y, respectively, and is configured as a tandem image forming apparatus. The organic EL array exposure heads 10K, 10C, 10M, and 10Y are configured by the head unit 10 described above.

  As shown in FIG. 6, the image forming apparatus includes a driving roller 121 and a driven roller 122, and includes an intermediate transfer belt 120 that is driven to circulate in the direction of the arrow shown in the drawing. Photosensitive members 110K, 110C, 110M, and 110Y having photosensitive layers are arranged on the outer peripheral surface as four image carriers arranged at predetermined intervals with respect to the intermediate transfer belt 120. K, C, M, and Y added after the reference sign mean black, cyan, magenta, and yellow, respectively, and indicate that the photoconductors are black, cyan, magenta, and yellow, respectively. The same applies to other members. The photoreceptors 110K, 110C, 110M, and 110Y are rotationally driven in synchronization with the driving of the intermediate transfer belt 120.

Around each photoconductor 110 (K, C, M, Y), charging means (corona charger) 111 (K) for uniformly charging the outer peripheral surface of the photoconductor 110 (K, C, M, Y), respectively. , C, M, Y) and the outer peripheral surface uniformly charged by the charging means 111 (K, C, M, Y) are synchronized with the rotation of the photoconductor 110 (K, C, M, Y). The organic EL array exposure head 10 (K, C, M, Y) as described above of the present invention that sequentially scans the lines is provided.
Further, a developing device 114 (K) that applies toner as a developer to the electrostatic latent image formed by the organic EL array exposure head 10 (K, C, M, Y) to form a visible image (toner image). , C, M, Y).

  Here, in each organic EL array exposure head 10 (K, C, M, Y), the array direction of the organic EL array exposure head 10 (K, C, M, Y) is the photosensitive drum 110 (K, C, M). , Y) along the bus. The light emission energy peak wavelength of each organic EL array exposure head 10 (K, C, M, Y) and the sensitivity peak wavelength of the photoconductor 110 (K, C, M, Y) are set to substantially coincide with each other. ing.

  The developing device 114 (K, C, M, Y) uses, for example, a non-magnetic one-component toner as a developer, and the one-component developer is conveyed to the developing roller by a supply roller, for example, and adhered to the developing roller surface. The film thickness of the developer is regulated by a regulation blade, and the developing roller is brought into contact with or increased in thickness by the photoreceptor 110 (K, C, M, Y). The toner image is developed by attaching a developer according to the potential level.

The black, cyan, magenta, and yellow toner images formed by the four-color single-color toner image forming station are sequentially primary-transferred onto the intermediate transfer belt 120 and sequentially superimposed on the intermediate transfer belt 120 to form a full color. It becomes. The recording medium 102 fed one by one from the paper feed cassette 101 by the pickup roller 103 is sent to the secondary transfer roller 126. The toner image on the intermediate transfer belt 120 is secondarily transferred to the recording medium 102 such as a sheet by the secondary transfer roller 126 and is fixed on the recording medium 102 by passing through the fixing roller pair 127 as a fixing unit. Thereafter, the recording medium 102 is discharged onto a paper discharge tray formed in the upper part of the apparatus by a paper discharge roller pair 128.
As described above, since the image forming apparatus of FIG. 9 uses the organic EL array as the writing means, the apparatus can be made smaller than when the laser scanning optical system is used.

Next, another embodiment of the image forming apparatus according to the present invention will be described.
FIG. 7 is a vertical side view of the image forming apparatus. In FIG. 7, the image forming apparatus includes, as main components, a developing device 161 having a rotary structure, a photosensitive drum 165 that functions as an image carrier, an exposure head 167 provided with an organic EL array, an intermediate transfer belt 169, and paper. A conveyance path 174, a fixing roller heating roller 172, and a paper feed tray 178 are provided. The exposure head 167 is configured by the head unit 10 described above.
In the developing device 161, the developing rotary 161a rotates counterclockwise about the shaft 161b. The inside of the development rotary 161a is divided into four, and image forming units for four colors of yellow (Y), cyan (C), magenta (M), and black (K) are provided. The developing rollers 162a to 162d and the toner supply rollers 163a to 163 are respectively arranged in the image forming units for the four colors. Further, the toner is regulated to a predetermined thickness by the regulation flades 164a to 164d.

The photosensitive drum 165 is charged by a charger 168 and is driven in a direction opposite to the developing roller 162a by a drive motor (not shown), for example, a step motor. The intermediate transfer belt 169 is stretched between the driven roller 170b and the drive roller 170a, and the drive roller 170a is connected to the drive motor of the photosensitive drum 165 to transmit power to the intermediate transfer belt. By driving the drive motor, the drive roller 170a of the intermediate transfer belt 169 is rotated in the opposite direction to the photosensitive drum 165.
The paper conveyance path 174 is provided with a plurality of conveyance rollers, a pair of paper discharge rollers 176, and the like, and conveys the paper. An image (toner image) on one side carried on the intermediate transfer belt 169 is transferred to one side of the paper at the position of the secondary transfer roller 171. The secondary transfer roller 171 is separated from and brought into contact with the intermediate transfer belt 169 by a clutch, and is brought into contact with the intermediate transfer belt 169 when the clutch is turned on, so that an image is transferred onto the sheet.

The sheet on which the image has been transferred as described above is then subjected to a fixing process by a fixing device having a fixing heater. The fixing device is provided with a heating roller 172 and a pressure roller 173. The sheet after the fixing process is drawn into the discharge roller pair 176 and proceeds in the direction of arrow F. When the paper discharge roller pair 176 rotates in the reverse direction from this state, the paper reverses its direction and advances in the double-sided printing conveyance path 175 in the direction of arrow G. The sheets are picked up one by one from the paper feed tray 178 by the pickup roller 179.
For example, a low-speed brushless smoke is used as a drive motor for driving the conveyance roller in the sheet conveyance path. The intermediate transfer belt 169 uses a step motor because it requires color misregistration correction. Each of these motors is controlled by a signal from a control means (not shown).

In the state shown in the drawing, a yellow (Y) electrostatic latent image is formed on the photosensitive drum 165, and a high voltage is applied to the developing roller 128a, whereby a yellow image is formed on the photosensitive drum 165. When all of the yellow back side and front side images are carried on the intermediate transfer belt 169, the development rotary 161a rotates 90 degrees.
The intermediate transfer belt 169 rotates once and returns to the position of the photosensitive drum 165. Next, two images of cyan (C) are formed on the photosensitive drum 165, and this image is carried on the yellow image carried on the intermediate transfer belt 169. Thereafter, the 90-degree rotation of the development rotary 161 and the one-rotation process after the image is carried on the intermediate transfer belt 169 are repeated in the same manner.

  For carrying four color images, the intermediate transfer belt 169 rotates four times, and then the rotation position is further controlled to transfer the image onto the sheet at the position of the secondary transfer roller 171. The paper fed from the paper feed tray 178 is transported by the transport path 174, and the color image is transferred to one side of the paper at the position of the secondary transfer roller 171. The sheet on which the image is transferred on one side is reversed by the discharge roller pair 176 as described above, and stands by on the conveyance path. Thereafter, the sheet is conveyed to the position of the secondary transfer roller 171 at an appropriate timing, and the color image is transferred to the other side. The housing 180 is provided with an exhaust fan 181.

It is a block diagram which shows the structure of the light-emitting device of this invention. It is a circuit diagram of the pixel circuit of the same device. It is a timing chart of the same circuit. 3 is an equivalent circuit diagram of a latch circuit 70 used in the circuit. FIG. It is a conceptual diagram which shows typically the relationship between the equivalent circuit of power supply line La and Lb, and power supply impedance. It is a vertical side view which shows an example of an image forming apparatus. It is a vertical side view which shows the other example of an image forming apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Light-emitting device (head part), Ta, Tb ... Supply terminal, La, Lb ... Power supply line, B1-B40 ... Block, P1-P89 ... Pixel circuit, 60 ... NOR circuit, 70 ... Latch circuit, 85 ... OLED element (Light-emitting element), 110Y, 110M, 110C, 110K.

Claims (6)

A plurality of pixel circuits each including a light emitting element and arranged in one direction;
A power line connected to each of the plurality of pixel circuits and supplied with power from one end thereof;
Driving means for dividing the plurality of pixel circuits into a plurality of blocks and driving the pixel circuits for each of the blocks;
In the adjacent block, the number of the pixel circuits included in the block closer to one end of the power supply line is equal to or larger than the number of the pixel circuits included in the block farther from one end of the power supply line. Set as
A light emitting device characterized by that.   The number of the pixel circuits included in the block farthest from one end of the power supply line is set as K, the number of the pixel circuits included in the other blocks is set as J, and J> K is set. The light emitting device according to claim 1.   The number of the pixel circuits included in the block closest to one end of the power supply line is L, the number of the pixel circuits included in the other blocks is all M, and M <L. The light emitting device according to claim 1. The light emitting element emits light having a magnitude corresponding to the amount of driving current,
Each of the plurality of pixel circuits includes a logic circuit that operates by power supplied from the power supply line, and a current supply unit that generates the drive current according to a calculation result of the logic circuit.
The light emitting device according to any one of claims 1 to 3. A photoreceptor on which an image is formed by irradiation of light;
A head unit that irradiates the photosensitive member with light and forms the image;
An image forming apparatus using the light emitting device according to claim 1 for the head portion. A method for driving a light emitting device, comprising: a plurality of pixel circuits each including a light emitting element; and a plurality of pixel circuits arranged in one direction; and a power supply line connected to each of the plurality of pixel circuits and supplied with power from one end thereof. There,
Dividing the plurality of pixel circuits into a plurality of blocks;
In the adjacent block, the number of the pixel circuits included in the block closer to one end of the power supply line is equal to or larger than the number of the pixel circuits included in the block farther from one end of the power supply line. Set as
A driving method of a light emitting device, wherein the pixel circuit is driven for each block.

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