JP2008080608A - Exposure head, image formation device, and exposure method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the circuit scale of an exposure head of a multiple exposure system. <P>SOLUTION: A processing unit U1 of the exposure head 10 has a first drive circuit DR11 supplying the first drive current Ip1 to a first light emitting element P11, a second drive circuit DR12 supplying the second drive current Ip2 to a second light emitting element P12, a compensating circuit C1, and a memory circuit M1 supplying a compensation value to the compensating circuit C1. The first drive circuit DR11 generates a predetermined current Iv1 and supplies the current Iv1 to the first light emitting element P11 as the first drive current Ip1 according to gradation signals d11 supplied from a control circuit 20. The compensation circuit C1 generates a compensation current Ic according to the compensation value supplied from the memory circuit M1 and supplies the same to the second drive circuit DR12. The second drive circuit DR12 generates a predetermined current Iv2, combines the same with the compensation current Ic, and supplies the current Iv2 and the compensation current Ic to the second light emitting element P12 as the second drive current Ip2 according to the gradation signal d12. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an exposure head for irradiating an image carrier with light emitted from a light emitting element formed of an organic EL (Electroluminescence) material or the like, an exposure method, and an image forming apparatus using the exposure head.

In a printer as an image forming apparatus, an exposure head for forming an electrostatic latent image on an image carrier such as a photosensitive drum is used. In the exposure head, a plurality of light emitting elements are generally arranged in an array in the main scanning direction. In addition, a plurality of (for example, two) light emitting elements are arranged in the sub scanning direction. There is a technique for forming one image by performing multiple exposure by irradiating light emitted from each light emitting element to one exposure position of an image carrier at different timings (see Patent Document 1).
JP 2004-82361 A

  By the way, the drive current supplied to each light emitting element may vary due to an error in manufacturing a transistor for driving the element. In order to absorb this variation in drive current, a correction circuit and a memory circuit for storing a correction value supplied to the correction circuit are provided in each drive circuit. However, as a result, there is a problem that the circuit scale is enlarged. The present invention has been made in view of such circumstances, and an object thereof is to solve the problem of reducing the circuit scale in an exposure head employing a multiple exposure method.

  The present invention will be described below. In order to facilitate understanding of the present invention, reference numerals in the accompanying drawings are appended in parentheses, but the present invention is not limited to the illustrated embodiment.

  In order to solve the above-described problem, the exposure head (10) according to the present invention causes the light emitted from each of the first and second light emitting elements (P11, P12) to be at one exposure position of the image carrier (110). An exposure head (10) capable of forming an image corresponding to a gradation designated at the exposure position by irradiating at different timings, and generating a first drive current (Iv1, Ip1) The total amount of light emitted from the first drive circuit (DR11) supplied to the first light emitting element (P11) and the first and second light emitting elements (P11, P12) depends on the gradation. One memory circuit (M1) that stores a correction value (Cv1) set to be equal to the amount of light and a correction current (Ic) corresponding to the correction value (Cv1) supplied from the memory circuit (M1). One correction circuit (C, C1) to be generated And a second drive circuit (DR12) that generates a predetermined current (Iv2), combines it with the correction current (Ic), and supplies the second drive current (Ip2) to the second light emitting element (P12). The first light emitting element (P11) outputs an emitted light having a light amount corresponding to the first driving current (Ip1), and the second light emitting element (P12) corresponds to the second driving current (Ip2). The amount of emitted light is output.

  In the present invention, using one correction circuit and one memory circuit that supplies a correction value to the correction circuit, the total amount of light emitted from the first and second light emitting elements is corrected. Specifically, the correction current supplied from the correction circuit is added to the second drive current that causes the second light emitting element to emit light. The correction current is a current based on a correction value that is set so that the total amount of light emitted from the first and second light emitting elements is equal to the amount of light according to the specified gradation. The total light amount of the first and second light emitting elements is corrected to the light amount corresponding to the gradation. Therefore, the circuit scale relating to the correction circuit and the memory circuit can be halved as compared with the configuration in which one correction circuit and one memory circuit are provided in each of the first and second light emitting elements to correct the light amount.

  In a preferred aspect of the present invention, the correction value (Cv1) is obtained by supplying only the correction current (Ic) to the second light emitting element (P12), so that the second light emitting element (P12) The second drive circuit (DR12) is set so as to be able to emit a light amount obtained by subtracting a light amount of light emitted from the first light emitting element (P11) from a light amount corresponding to a gradation, and the second drive circuit (DR12) The correction current (Ic) is supplied as the second drive current (Ip2) to the second light emitting element (P12) without generating Iv2). According to this aspect, since one correction circuit and one memory circuit are used to correct the amount of light emitted from the two light emitting elements, the same effect as described above can be obtained. Further, in this aspect, the correction value is determined so that the second light emitting element emits light with a light amount obtained by subtracting the light amount of the light emitted from the first light emitting element from the light amount according to the gradation. The correction current from the correction circuit is supplied to the second light emitting element as the second drive current without the second drive circuit generating a predetermined current. Therefore, as compared with an aspect in which the second drive circuit generates a predetermined current, an element (drive element) for generating a current becomes unnecessary, and the configuration is simplified.

  In order to solve the above problems, the exposure head (10A) of the present invention irradiates the light emitted from each of the first and second light emitting elements (P11, P12) to one exposure position of the image carrier at different timings. Thus, an exposure head (10A) capable of forming an image corresponding to the gradation designated at the exposure position, and emitting from the first and second light emitting elements (P11, P12). One memory circuit that is set so that the total amount of light is equal to the amount of light according to the gradation, and stores a correction value (Cv1) common to the first and second light emitting elements (P11, P12) (M1) and a first correction circuit that generates a first correction current (Ic11) according to the correction value (Cv1) supplied from the memory circuit (M1) and supplies the first correction current (Ic11) to the first drive circuit (C11) and the memory circuit (M ) To generate a second correction current (Ic12) corresponding to the correction value supplied from the second drive circuit, and supply the second correction circuit (C12) to the second drive circuit, and a first current (Iv1). A first drive circuit (DR11) that is generated and combined with the first correction current (Ic11) and supplied to the first light emitting element (P11) as a first drive current (Ip1), and a second current (Iv2) ) And is combined with the second correction current (Ic12) and supplied to the second light emitting element (P12) as a second drive current (Ip2) substantially equal to the first drive current (Ip1). A drive circuit (DR12), wherein the first light emitting element (P11) outputs an amount of emitted light corresponding to the first driving current (Ip1), and the second light emitting element (P12) Output light having a light amount corresponding to the second drive current (Ip2) is output.

  The present invention employs a configuration in which one correction circuit is provided for each of the first and second light emitting elements, and one common memory circuit is provided for both the light emitting elements. Since one memory circuit is connected in common to the first correction circuit and the second correction circuit, the circuit scale can be reduced as compared with a mode in which a memory circuit is provided for each correction circuit. Since this memory circuit stores a correction value common to the first and second light emitting elements, each correction circuit supplies a correction current having substantially the same flow rate to the first drive circuit and the second drive circuit. . When the first current and the second current are substantially equal, the first drive current supplied to the first light emitting element and the second drive current supplied to the second light emitting element are substantially equal. The degree of deterioration of the light emitting element has a correlation with a value obtained by integrating the light emission amount. According to this invention, the light emission amounts of the first and second light emitting elements are equalized, and the degree of deterioration of the light emitting elements does not vary between the first and second light emitting elements. Accordingly, since the lifetime of the second light emitting element is extended as compared with the aspect in which the correction current is supplied only to the second light emitting element, the lifetime of the apparatus as the entire exposure head is extended.

  In a preferred aspect of the present invention, the correction circuit (C, C1, C11, C12) includes a plurality of current generation circuits (TrC1, TrC2, TrC3) having different weights, and each current generation circuit (TrC1, The correction currents (Ic, Ic11, Ic12) are generated by synthesizing the currents (Ic1, Ic2, Ic3) output from TrC2, TrC3). In this aspect, the correction current is generated by adding the currents output from the plurality of current generation circuits. Since each current generation circuit has a different weight (size), a correction current (Ic) having an expected value can be obtained by appropriately setting a weight ratio between the current generation circuits and selectively generating a current. It becomes possible. Therefore, the required correction can be performed by a correction circuit having a simple configuration.

  In another preferred aspect of the present invention, the first drive circuit (DR11) is provided in a path for supplying the first drive current (Ip1) to the first light emitting element (P11), and is turned on / off. The first switching element (Tr12) to be controlled is provided, and the second driving circuit (DR12) is provided in a path for supplying the second driving current (Ip2) to the second light emitting element (P12), and is turned on. A control means (20, 20A) that includes a second switching element (Tr22) that is controlled to be turned off, and that turns on the first and second switching elements for a time corresponding to the designated gradation at different timings. ). In this aspect, a PWM (Pulse Width Modulation) method is employed in which each drive current is supplied to each of the first and second light emitting elements for a time corresponding to a designated gradation. According to this method, since the gradation is controlled by the time for supplying the drive current, it is not necessary to set the correction current generated by the correction circuit according to the gradation. That is, the correction current can be controlled independently of the gradation. The control means turns on the first switching element and the second switching element at different timings, and these time differences are set so that light can be irradiated to one exposure position on the image carrier. . More specifically, when the relative speed between the image carrier and the exposure head is V and the distance between the first light emitting element and the second light emitting element is W, the time difference ΔT is given by ΔT = W / V. In addition, the time when the first switching element is turned on coincides with the time when the second switching element is turned on. For this reason, the control means may generate a first control signal for controlling the first switching element, and generate a second control signal for controlling the second switching element by delaying the first control signal by the time difference ΔT.

  Furthermore, the present invention provides an image carrier (110) on which an image is formed by light emitted from the exposure head (10) of any one of the above aspects and the first and second light emitting elements (P11, P12). ). According to the image forming apparatus of the present invention, any of the effects described above can be achieved.

  The present invention designates the exposure position by irradiating light emitted from each of the first and second light emitting elements (P11, P12) to one exposure position of the image carrier (110) at different timings. An exposure method for forming an image according to gradation, wherein the total amount of light emitted from the first and second light emitting elements (P11, P12) is a light amount corresponding to the designated gradation. A correction current (Ic) corresponding to a correction value set to be equal to is generated, a first drive current (Iv1, Ip1) is generated and supplied to the first light emitting element (P11) to generate the first drive current (Iv1, Ip1). The second light emitting element (P12) is caused to emit light, and the second driving current (Ip2) corrected by the correction current (Ic) is supplied to the second light emitting element (P12). It is also grasped as an exposure method for emitting light. In the present invention, only by additionally supplying a correction current to the second light emitting element, the sum of the amounts of light emitted from the first and second light emitting elements is a value corresponding to the designated gradation. It is corrected to. Therefore, compared with the case where the light amount is corrected for each of the first and second light emitting elements, correction can be performed easily, and the load related to control is reduced.

  Furthermore, the present invention designates the exposure position by irradiating light emitted from each of the first and second light emitting elements (P11, P12) to one exposure position of the image carrier (110) at different timings. An exposure method for forming an image according to the gradation, wherein the total amount of light emitted from the first and second light emitting elements (P11, P12) is a light amount corresponding to the gradation. The first correction current (Ic11) is generated according to the correction value common to the first and second light emitting elements (P11, P12), and the first current (Iv1) A first drive current (Ip1) obtained by combining the first correction current (Ic11) is generated and supplied to the first light emitting element (P11) to cause the first light emitting element (P11) to emit light, and A second correction current (Ic12) is generated according to the common correction value, and the second correction current (Ic12) is generated. A second driving current (Ip2) obtained by combining the current (Iv2) and the second correction current (Ic12) is generated and supplied to the second light emitting element (P12) to supply the second light emitting element (P12). ) Is also grasped as an exposure method for emitting light. In the present invention, since a common correction value is set for both the first and second light emitting elements, the correction can be easily performed as compared with the case where the correction value is set separately. The load related to is reduced. Further, in the configuration in which the correction current is supplied to only one of the first and second light emitting elements to correct the light amount, the lifetime of the element varies between the two. However, in this aspect, since substantially the same drive current is supplied to both the first and second light emitting elements, the variation is eliminated and the life of the entire exposure head is extended.

Various embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the common part in each figure.
<A. First Embodiment>
FIG. 1 is a perspective view showing a partial configuration of an image printing apparatus using an exposure head according to the present embodiment. As shown in the figure, the image printing apparatus includes an exposure head 10, a condensing lens array 15, and a photosensitive drum (image carrier) 110. The exposure head 10 has a large number of light emitting elements arranged in an array. These light emitting elements selectively emit light according to an image to be printed on a recording material such as paper. The condensing lens array 15 is disposed between the exposure head 10 and the photosensitive drum 110. The condensing lens array 15 includes a large number of gradient index lenses arranged in an array with each optical axis directed to the exposure head 10. An example of such a condensing lens array 15 is SLA (Selfoc Lens Array) available from Nippon Sheet Glass Co., Ltd. (Selfoc / SELFOC is a registered trademark of Nippon Sheet Glass Co., Ltd.). Light emitted from each light emitting element of the exposure head 10 passes through each gradient index lens of the condensing lens array 15 and forms an image on the surface of the photosensitive drum 110. The photosensitive drum 110 rotates, and a latent image corresponding to a desired image is formed at a predetermined exposure position on the surface of the photosensitive drum 110.

  FIG. 2 schematically shows the arrangement of the light emitting elements P of the exposure head 10. In this embodiment, an organic EL diode is used as the light emitting element. As shown in FIG. 2, 2 × n light emitting elements P are arranged in two rows parallel to the main scanning direction X (rotational axis direction of the photosensitive drum 110) and n columns parallel to the sub-scanning direction Y. ing. In each row, n light emitting elements P of P11 (P12), P21 (P22), P31 (P32), P41 (P42),... Pn1 (Pn2) are arranged. In each row, the emitted light from each of P11 and P12 is applied to the same exposure position (printing dot) on the surface of the photosensitive drum 110. Specifically, when the exposure position reaches the emission position of the light emitting element P11 due to the rotation of the photosensitive drum 110, the light from the light emitting element P11 is first irradiated to the exposure position, and the photosensitive drum 110 further rotates. Thus, when the exposure position reaches the emission position of the light emitting element P12, the light from the light emitting element P12 is irradiated to the exposure position. As a result, a latent image corresponding to the designated gradation is formed at the exposure position. Similarly, the emitted light from P21 and P22 is irradiated to the same exposure position, and the emitted light from P31 and P32 is irradiated to the same exposure position. That is, the exposure head 10 of the present embodiment is a double exposure system that irradiates the light emitted from the two light emitting elements P in each row to the same exposure position. In the following description, each of P11, P21, P31, P41,... Pn1 is designated as “first light emitting element”, and each of P12, P22, P32, P42,. Called “element”.

  FIG. 3 is a block diagram showing the electrical configuration of the exposure head 10. As shown in FIG. 3, the exposure head 10 includes a pair [P11, P12], [P21, P22], [P31, P32],... [Pn1, Pn2] of a first light emitting element and a second light emitting element. ] N processing units U (U1, U2, U3,... Un) for generating a driving current for driving each of the light emitting elements P and supplying them to each light emitting element P. The exposure head 10 further includes a control circuit 20 that controls each processing unit U. The control circuit 20 is supplied with image data Din and a clock signal CK from the outside, and the control circuit 20 has a gradation signal d (d11,) corresponding to the gradation specified by the image data Din at the timing specified by the clock signal CK. d12, d21, d22, d31, d32,... dn1, dn2) are supplied to each processing unit U.

  The processing unit U1 includes a first drive circuit DR11 that supplies a first drive current Ip1 to the first light emitting element P11, and a second drive circuit DR12 that supplies a second drive current Ip2 to the second light emitting element P12. . Further, the processing unit U1 includes a correction circuit C1 and a memory circuit M1. The correction circuit C1 is connected to the second drive circuit DR12, and the memory circuit M1 is connected to the correction circuit C1. The gradation signal d11 is supplied from the control circuit 20 to the first drive circuit DR11, the gradation signal d12 is supplied to the second drive circuit, and the correction value Cv1 is supplied to the memory circuit M1.

  FIG. 4 shows a detailed circuit configuration of the processing unit U1. The first drive circuit DR11 includes a P-channel drive transistor Tr11 and an N-channel selection transistor Tr12. A power supply potential VEL is supplied to the source of the drive transistor Tr11, and a reference potential VREF supplied from the outside is supplied to the gate. The drain of the selection transistor Tr12 is connected to the drain of the drive transistor Tr11. The source of the selection transistor Tr12 is connected to the anode of the light emitting element P11. The gradation signal d11 is supplied from the control circuit 20 to the gate of the selection transistor Tr12. A ground potential GND is applied to the cathode of the light emitting element P11. Although not shown, the other processing units U2, U3,... Un have the same configuration as the processing unit U1.

  In the present embodiment, the gradation of each light emitting element P is controlled using a PWM (Pulse Width Modulation) method. In the PWM method, the voltage applied to the gate of the selection transistor Tr12 is set to H level (ON state; voltage for causing the light emitting element P to emit light) in a period corresponding to the gradation value designated for the light emitting element P, and the remaining The gray level is controlled by setting it to L level (OFF state; voltage for turning off the light emitting element P) during the period. The gradation signal d is a signal that designates a period during which the selection transistor Tr12 is on. That is, the gradation signal d is a voltage that is at the H level in a period corresponding to the designated gradation.

  In the above circuit configuration, when the gate of the selection transistor Tr12 of the first drive circuit DR11 changes to the on state according to the gradation signal d11, the gate of the drive transistor Tr11 is set for a period specified for the light emitting element P11. A drive current Ip1 corresponding to the supplied reference potential VREF (that is, a current Iv1 flowing between the source and drain of the drive transistor Tr11) flows to the light emitting element P11, and the light emitting element P11 emits light.

  As shown in FIG. 4, the second drive circuit DR12 has substantially the same configuration as the first drive circuit DR11. However, the second drive circuit DR12 has a node Nc connected to the correction circuit C1 on the path from the drain of the drive transistor Tr21 to the drain of the selection transistor Tr22, and is supplied from the current Iv2 generated by itself and the correction circuit C1. The corrected current Ic is combined to generate a second drive current Ip2, which is supplied to the anode of the second light emitting element P12.

  Specifically, the drive transistor Tr21 of the second drive circuit DR12 generates a current Iv2 corresponding to the reference potential VREF, while the correction circuit C1 generates a correction current Ic based on the correction value Cv1 supplied from the memory circuit M1. To do. The correction current Ic is combined with the current Iv2 in the second drive circuit DR12 and supplied to the drain of the selection transistor Tr22. A gradation signal d12 that specifies the gradation of the light emitting element P12 is supplied to the gate of the selection transistor Tr22, and the current Iv2 and the correction current Ic emit light during the period when the gate is turned on by the gradation signal d12. It flows to the element P12 and the light emitting element P12 emits light.

  FIG. 5 is a graph showing the ratio of the current Iv1 generated by the drive transistor Tr11 of the first drive circuit DR11, the current Iv2 generated by the drive transistor Tr21 of the second drive circuit DR12, and the correction current Ic. . The horizontal axis of this graph is each address of the print dots arranged in a line parallel to the main scanning direction (X in FIG. 2) of the exposure head 10, and the number of print dots corresponds to the number of the light emitting elements P. In the description of FIG. 2, the number of light emitting elements P arranged in each row is described as n. However, in the graph of FIG. 5, dot addresses 1 to 20 are shown for simplicity. The vertical axis indicates the exposure power required for each print dot. The exposure power is the sum of the light emission powers of the first light emitting element P11 and the second light emitting element P12, and is proportional to the sum of the drive currents supplied to the light emitting elements P11 and P12. In the graph of FIG. 5, each ratio of the current Iv1, the current Iv2, and the correction current Ic when the required exposure power is 100% is shown.

  By the way, in the performance of a transistor, for example, there are slight variations in gate width and gate length and variations due to impurities contained in a semiconductor (that is, variations in manufacturing). For this reason, even when a voltage of the same level is applied to the gate, the output current varies depending on the transistor. For this reason, when only the drive transistors Tr11 and Tr21 are driven, the exposure power varies for each print dot. In the present embodiment, in order to absorb this variation, a correction current Ic as an addition current is generated in a correction circuit C1 separate from the drive circuits DR11 and DR12. Specifically, when the required exposure power is X, the exposure power obtained by the current Iv1 is Y, and the exposure power obtained by the current Iv2 is Z, the correction current Ic corresponding to X− (Y + Z) is one. The correction circuit C1 is generated. As described above, the correction current Ic is combined with the current Iv2 generated by the second drive circuit DR12 and flows through the second light emitting element P12 as the second drive current Ip2. As a result, the current Iv1 flows through the first light emitting element P11, the current Iv2 and the correction current Ic flow through the second light emitting element P12, and the driving current flowing through the first and second light emitting elements P11 and P12 is entirely reduced. , The exposure power corresponding to the current Iv1 + Iv2 + Ic is ensured. That is, in the present embodiment, both the currents Iv1 and Iv2 generated by the drive transistors Tr11 and Tr21 are corrected by the correction current Ic. In other words, the magnitude of the correction current Ic is set including not only the variation of the drive transistor Tr21 but also the variation of the drive transistor Tr11.

  Further, when there are errors in various characteristics (for example, light emission efficiency) of the light emitting element P, even if the drive current Ip having the same current value is supplied to all the light emitting elements P, the actual light emitting element P is exposed. Variations occur in power. In this embodiment, by appropriately setting the magnitude of the correction current Ic, such variations in the optical system can be similarly corrected.

  On the other hand, a method of separately adding the correction current Ic to the first drive circuit DR11 and the second drive circuit DR12 is also conceivable. That is, the variation in current generated by the drive transistor Tr11 of the first drive circuit DR11 and the variation in current generated by the drive transistor Tr21 of the second drive circuit DR12 are corrected by individual correction currents according to individual correction values. It is. However, in this method, it is necessary to provide one memory circuit and one correction circuit for both the first and second drive circuits. In the exposure head of the exposure system by multiple exposure, if the number of sets of memory circuits and correction circuits is provided as many as the number of light emitting elements P to be subjected to multiple exposure, the circuit scale is enlarged. As a result, the exposure head is hindered from being reduced in size and cost. Therefore, in the present embodiment, both the current Iv1 and the current Iv2 are corrected together by only providing one memory circuit M1 and one correction circuit C1 for the first drive circuit DR11 and the second drive circuit DR12. It is configured to do. The correction value Cv1 stored in the memory circuit M1 is set to a value that absorbs variations in both the drive transistors Tr11 and Tr21, and the correction current Ic generated according to the correction value Cv1 is the sum of the current Iv1 and the current Iv2. Further, necessary exposure power is added to make the total uniform. With such a configuration, it becomes possible to suppress the enlargement of the circuit.

  Here, details of the correction value Cv will be described. The control circuit 20 stores different correction values Cv (Cv1, Cv2,... CVn) for each dot address in a storage unit (not shown). The correction value Cv is a value indicating the correction current Ic generated by each correction circuit C for each dot address. The correction current Ic is a value obtained by subtracting the currents Iv1 and Iv2 from the total current amount corresponding to the necessary exposure power X. The value of the correction current Ic is obtained, for example, by actually measuring the currents Iv1 and Iv2 generated by the drive transistors Tr in the exposure head 10 for each dot address. Alternatively, the correction current Ic can be determined based on the result of measuring the exposure power (gradation) of each light emitting element P in advance. On the other hand, since the light amount of the light emitting element P is a product of exposure power and time, the correction value Cv1 is the light emitting elements P11, P12 when each of the light emitting elements P11 and P12 emits light for the period specified by the gradation signal d. Is set so that the total light amount of the emitted light from is equal to the light amount corresponding to the designated gradation. Further, the correction value Cv is a binarized 3-bit value (x, y, z) determined in consideration of the performance of the current generation circuit (drive transistor) in the correction circuit C based on the correction current Ic. is there. The correction value Cv is supplied to the memory circuit M corresponding to the dot address. As shown in FIG. 4, the memory circuit M1 includes correction value memories M11, M12, and M13. The 3-bit correction value Cv1 supplied to the memory circuit M1 is stored one bit at a time in each of the correction value memories M11, M12, and M13.

  As shown in FIG. 4, the correction circuit C1 includes three drive transistors TrC1, TrC2, and TrC3. The drive transistors TrC1, TrC2, and TrC3 are connected in parallel, the power supply potential VEL is supplied to the source, and the reference potential VREF is supplied to the gate. On the drain side, select transistors TrC4, TrC5, TrC6 are connected, respectively. These selection transistors are switching elements that are turned on or off based on a signal (H or L) supplied from the correction value memories M11, M12, and M13 to the gate. In the present embodiment, the drive transistors TrC1, TrC2, and TrC3 are weighted by setting the size ratio to “1: 2: 4”. When the correction value (x, y, z) = (1, 1, 1), all of the selection transistors TrC4, TrC5, TrC6 are turned on, and the current Ic1 generated by each of the drive transistors TrC1, TrC2, TrC. , Ic2, and Ic3 all flow through the selection transistors TrC4, TrC5, and TrC6, and a correction current Ic = Ic1 + Ic2 + Ic3 is generated. Since the ratio of the weight (w) is “1: 2: 4”, the correction current Ic has a weight of “7w”. Similarly, in the case of the correction value (0, 1, 1), the weight “6w”, in the case of the correction value (1, 0, 1), the weight “5w” and the correction value (0, 0, 1). In this case, the weight is “4w”, the correction value (1, 1, 0) is the weight “3w”, the correction value (0, 1, 0) is the weight “2w”, and the correction value (1,0). , 0), the weight is “1w”, and in the case of the correction value (0, 0, 0), the weight is “0w”, and a total of eight levels of correction current Ic is generated according to the value in the correction value memory. .

  Here, as described above, the correction circuit C is a current addition type circuit that generates a correction current Ic as an addition current. Therefore, the sizes of the drive transistors Tr11 and Tr21 of the drive circuit are set so that the sum of the current Iv1 and the current Iv2 does not exceed the required exposure power at the maximum. The ideal value is set to be Iv1 = Iv2 ++ 1/2 · Ic. By setting in this way, even when each of the currents Iv1 and Iv2 increases or decreases with respect to the set value, an intended exposure power can be obtained only by appropriately increasing or decreasing the correction current Ic as the addition current. Is possible.

  In the above configuration, first, the current Iv1 corresponding to the reference potential VREF flows as the first drive current Ip1 in the first light emitting element P11 during the period (t1) when the selection transistor Tr12 is on. Then, after t1, in a period (t2) in which the selection transistor Tr22 is on at a timing different from t1, the current Iv2 corresponding to the reference potential VREF and the correction current Ic generated by the correction circuit C1 are second driven. The current Ip2 flows through the second light emitting element P12. That is, a predetermined exposure position on the photosensitive drum 110 is irradiated with light emitted from the first light emitting element P11 with an exposure power corresponding to the first drive current Ip1 for a period t1, and then the second The light emitted from the second light emitting element P12 is irradiated during the period t2 with the exposure power corresponding to the drive current Ip2, and as a result, a latent image corresponding to the gradation specified by the image data Din is formed. Here, the time difference between the start of the period t1 and the start of the period t2 is ΔT, the distance between the first light emitting element P11 and the second light emitting element P12 is W, and the relative speed between the photosensitive drum 110 and the exposure head 10 is V. , The time difference ΔT is given by ΔT = W / V. Further, the control circuit 20 generates a gradation d11 that is at the H level for a period corresponding to the gradation to be displayed, and delays this by a time difference ΔT to generate a gradation signal d12.

  As described above, in the exposure head 10 of the present embodiment, one memory is used for two light emitting elements P (that is, two drive circuits DR) in a configuration employing a double exposure method using two light emitting elements P. By only providing the circuit M and the correction circuit C, the exposure power of the two light emitting elements P as a whole is corrected. Therefore, the circuit scale can be reduced as compared with a configuration in which one set of memory circuit and correction circuit is provided for each light emitting element P. When attention is paid only to the memory circuit and the correction circuit, the circuit scale becomes 1/2. Therefore, it is possible to correct the exposure power to a desired value with a small circuit scale.

  The correction circuit C includes a plurality of drive transistors TrC1, TrC2, and TrC3 (current generation circuits) having different weights, and combines currents generated by the drive transistors to generate a correction current. Circuit. Therefore, it is possible to obtain a correction current having an expected value by appropriately setting the weight ratio of the driving transistor and selectively generating the current. Therefore, the exposure power can be corrected with a correction circuit having a simple configuration.

  The first driving circuit includes a selection transistor Tr12 (first switching element), and the second driving circuit includes a selection transistor Tr22 (second switching element), which has a gradation specified by the gradation signal d. The selection transistors Tr12 and Tr22 are turned on at different timings (t1 and t2) for the corresponding time. That is, in the present embodiment, a PWM (Pulse Width Modulation) method is employed in which each drive current is supplied to each of the first and second light emitting elements P11 and P12 for a time corresponding to a specified gradation. ing. According to this method, since the gradation is controlled by the time for supplying the drive currents Ip1 and Ip2, it is not necessary to set the correction current Ic generated by the correction circuit C1 according to the gradation. That is, the correction current Ic can be controlled independently of the gradation.

<B. Second Embodiment>
In the first embodiment, the second drive circuit DR12 itself generates the current Iv2, and the current Iv2 is combined with the correction current Ic generated by the correction circuit C1 to form the second drive current Ip2 as the second light emitting element. It was set as the structure supplied to P12. In contrast, in the present embodiment, the second drive circuit DR12 does not generate the current Iv2, but instead, a correction current having a value corresponding to the sum of the current Iv2 and the correction current Ic in the first embodiment is corrected. Generated by C1.

  FIG. 6 is a diagram showing a circuit configuration of the processing unit U1 according to the present embodiment, and FIG. 7 corresponds to the graph of FIG. 5 in the first embodiment, and shows a current Iv1 generated by the first drive circuit DR11, It is a graph which shows the ratio of the correction electric current IcA produced | generated by the correction circuit C1. As shown in FIG. 6, in the present embodiment, the drive transistor Tr21 as in the first embodiment is omitted in the second drive circuit DR12A, and only the selection transistor Tr22 is provided. Except for this point, the configuration of the exposure head 10 of the present embodiment is the same as that of the exposure head 10 of the first embodiment, and thus description thereof will be omitted as appropriate.

  As shown in FIG. 6, the correction circuit C1 includes three drive transistors TrC1, TrC2, and TrC3, and generates currents Ic1, Ic2, and Ic3 corresponding to the sizes thereof. The ratio of the sizes of the drive transistors TrC1, TrC2, and TrC3 is set to “1: 2: 4” as in the first embodiment.

  In the storage unit of the control circuit 20 of the present embodiment, different correction values are stored for each dot address. As shown in FIG. 7, the correction value is a value determined such that the second correction current IcA is a value obtained by subtracting the current Iv1 from the total current amount corresponding to the exposure power necessary for the necessary exposure power. It is. Further, since the light amount of the light emitting element P is a product of the exposure power and time, the correction value is obtained from the light emitting elements P11 and P12 when each of the light emitting elements P11 and P12 emits light for the period specified by the gradation signal d. The total amount of the emitted light is set to be equal to the amount of light according to the designated gradation. In particular, in the present embodiment, the correction value is determined so that the second light emitting element can emit a light amount obtained by subtracting the light amount of the light emitted from the first light emitting element P11 from the light amount according to the designated gradation. Value.

  This correction value is supplied as a 3-bit value (x, y, z) to the memory circuit M corresponding to the dot address, and stored in the correction value memories M11, M12, and M13 one bit at a time. The selection transistors TrC4, TrC5, TrC6 are turned on or off according to the signals (H or L) supplied from the correction value memories M11, M12, M13. As a result, the combination of the currents Ic1, Ic2, Ic3 is The correction current IcA is supplied to the drain of the selection transistor Tr22 of the second drive circuit DR12. The selection transistor Tr22 is turned on during a period (t2) in which the gradation signal d12 applied to the gate is at the H level, and the correction current IcA flows to the second light emitting element P12 as the second drive current Ip2. On the other hand, in the first drive circuit DR11, the selection transistor Tr12 is turned on during the period (t1) when the gradation signal d11 is at the H level, and the current Iv1 generated by the drive transistor Tr11 is the first drive current Ip1. It flows to one light emitting element P11. Note that, similarly to the first embodiment, the period t1 is a timing different from t2, which is T before the period t2.

  As described above, in the present embodiment, the second drive current Ip2 supplied to the second light emitting element P12 is generated only by the correction circuit C1 without providing the drive transistor Tr21 in the second drive circuit DR12A. Since the second drive current Ip2 includes the correction current Ic, the exposure power as a whole can be made uniform between the dot addresses. Therefore, the same effect can be obtained with a simpler configuration as compared with the first embodiment.

<C. Third Embodiment>
In the first and second embodiments described above, one memory circuit M1 and one correction circuit C1 are provided for two of the first drive circuit DR11 and the second drive circuit DR12. In contrast, in the present embodiment, one memory circuit is provided for two of the first drive circuit DR11 and the second drive circuit DR12, and one correction circuit is provided for each of the first drive circuits DR11 and DR12. It is different from the above embodiment in that it is provided. Since the exposure head of this embodiment is the same as that of the first embodiment except for this point, the description thereof will be omitted as appropriate.

  FIG. 8 is a block diagram showing the arrangement of the exposure head 10A according to this embodiment. As shown in FIG. 8, the exposure head 10A includes a control circuit 20A and a plurality of processing units UA (UA1, UA2,... UAn). Each processing unit UA is connected to the anodes of the first and second light emitting elements P. Each processing unit UA generates a drive current to be supplied to the first and second light emitting elements P based on the gradation signal d and the correction value Cv supplied from the control circuit 20A.

  As shown in FIG. 8, the processing unit UA1 supplies a first drive circuit DR11 that supplies a first drive current Ip1 to the first light emitting element P11, and a second drive current Ip2 to the second light emitting element P12. It has a second drive circuit DR12, a correction circuit C11 that supplies a correction current Ic11 to the first drive circuit DR11, and a correction circuit C12 that supplies a correction current Ic12 to the second drive circuit DR12. The processing unit UA1 further includes one memory circuit MA1, and the same correction value Cv1 is given to each of the correction circuit C11 and the correction circuit C12 from the memory circuit MA1.

  FIG. 9 is a circuit diagram showing a circuit configuration of the processing unit UA1. As shown in FIG. 9, the first drive circuit DR11 includes a drive transistor Tr11 and a selection transistor Tr12. The drive transistor Tr11 generates a current Iv1 corresponding to the reference potential VREF applied to the gate. A node Nc for connecting the correction circuit C11 and the first drive circuit DR11 is provided on the path from the drive transistor Tr11 to the selection transistor Tr12. The correction current Ic11 from the correction circuit C11 is supplied from the node Nc to the first drive. It is supplied to the circuit DR11. The selection transistor Tr12 is turned on during the period (t1) when the gradation signal d11 is at the H level, and the first drive current Ip1 obtained by synthesizing the current Iv1 and the correction current Ic11 flows into the first light emitting element P11 and the first transistor The light emitting element P11 emits light. The second drive circuit DR12 also has the same configuration as the first drive circuit DR11. That is, during the period (t2) when the selection transistor Tr22 is on, the second drive current Ip2 obtained by combining the current Iv2 and the correction current Ic12 flows to the second light emitting element P12, and the second light emitting element P12 emits light.

  Each of the correction circuits C11 and C12 has the same configuration as the correction circuit C1 in the first embodiment. As in the first embodiment, the drive transistors TrC1, TrC2, TrC3 have different weights, and the selection transistors TrC4, TrC5, TrC6 are turned on or off based on the correction value Cv1 supplied from the correction circuit MA1. Thus, the correction currents Ic11 and Ic12 at the level specified by the correction value Cv1 are output.

  By the way, the drive transistor Tr11 of the first drive circuit DR11 and the drive transistor Tr21 of the second drive circuit DR12 are located close to each other in the circuit layout. For this reason, the characteristics of both are often almost equal. In this case, since the current Iv1 is substantially equal to the current Iv2, the correction currents Ic11 and Ic12 may be substantially equal. Therefore, in this embodiment, instead of providing the memory circuit individually for each of the correction circuits C11 and C12, only one memory circuit MA1 is provided, and the correction value Cv1 is set as a value common to the correction circuits C11 and C12. ing. Thereby, the circuit scale can be reduced as compared with the case where the memory circuits are provided corresponding to the number of the light emitting elements P.

  The lifetime of the light emitting element is proportional to the light emission amount and the light emission time. In the first and second embodiments, since only the second drive current Ip2 supplied to the second light emitting element P12 is a current including the correction current Ic, the first light emitting element P11 in which only the current Iv1 flows is used. In comparison with the second light emitting element P12, the deterioration of the element becomes more severe. In the present embodiment, the current Iv1 and the correction current Ic11 are supplied as drive currents to the first light emitting element P11, and the current Iv2 substantially equal to the current Iv1 is corrected to the second light emitting element P12. Since the correction current Ic12 generated in accordance with the same correction value as that of the current Ic11 is supplied, the currents flowing through the two are almost equal as a whole, and when the light emission time is the same, the degree of deterioration of the element is equal between the two. become. Therefore, as a result, the lifetime of the exposure head 10A as a whole can be extended as compared with the configurations of the first and second embodiments.

  FIG. 10 is a graph showing, for each dot address, the ratio of the current Iv1, the correction current Ic11, the current Iv2, and the correction current Ic12 to the exposure power of 100%. Similar to FIG. 5, the graph of FIG. 10 shows only 20 dot addresses instead of n dot addresses for simplicity.

  As shown in FIG. 10, the correction value Cv is set for each dot address in accordance with the characteristics (variation) of the drive transistor used for exposure of each print dot. For example, at the dot address “2”, a correction value Cv2 that specifies correction currents Ic11 and Ic12 larger than the dot address “1” is set. Thus, the correction value for each dot address is appropriately set so that the exposure power as a whole is uniform between the dots. The ratio of the current Iv1 and the correction current Ic11 to the entire exposure power is approximately 50%, and the ratio of the current Iv2 and the correction current Ic12 is also approximately 50%. As described above, since the current Iv1 and the current Iv2 are generated by the drive transistors having substantially the same characteristics, both are substantially equal, and the correction current Ic11 and the correction current Ic12 generated according to the common correction value Cv are approximately equal. . Therefore, the amounts of current flowing through the first light emitting element P11 and the second light emitting element P12 are substantially equal, and as a result, the deterioration of both elements is comparable.

  Even if the characteristics of the drive transistors Tr11 and Tr21 are greatly different, the correction currents Ic11 and Ic12 have a difference of 1% between the currents Iv1 and Iv2 and 100% so that the total exposure power becomes 100%. / 2. Therefore, the exposure power as the whole double exposure can be made equal. In this case, there is a difference between the first drive current and the second drive current, and thus there is a difference in lifetime between the light emitting elements P11 and P12. However, since such variation is rare, the lifetime is reduced as a whole. Can be extended.

  As described above, in the exposure head 10A of the present embodiment, one drive circuit and one correction circuit are provided for each of the two light emitting elements P11 and P12 that emit light at different timings with respect to one exposure position. Provided is only one memory circuit common to the two elements. Therefore, the circuit scale is suppressed as compared with the case where one memory circuit is provided for each of the light emitting elements P11 and P12. Furthermore, since substantially the same amount of drive current flows through the first and second light emitting elements P11 and P12 as a total, the degree of deterioration of both elements is made uniform when the light emission time is the same. Thus, according to the exposure head 10A of the present embodiment, it is possible to suppress the circuit scale of the processing unit without impairing the life of the entire exposure head.

<D. Modification>
In the first and second embodiments described above, the double exposure method in which one exposure position (printing dot) is exposed by two light emitting elements P11 and P12 is adopted. You may employ | adopt the multiple exposure system which exposes one exposure position. In that case, one memory circuit and one correction circuit may be provided for a plurality of light-emitting elements exposed to one exposure position. Further, in the third embodiment, in the case of the multiple exposure method, a configuration may be adopted in which a common correction value is given to each correction circuit from one memory circuit. In any aspect, the same effect as described above is achieved.

In the first to third embodiments, the digital switch that outputs the value “1” or “0” to each of the selection transistors TrC4 to TrC6 from each of the correction value memories M11 to M13 is used. Alternatively, an analog memory that outputs an analog value may be used.
FIG. 11 is a diagram illustrating a configuration of a memory and a correction circuit when the present modification is applied to the first embodiment.

  As shown in FIG. 11, the memory M1a according to the present modification includes analog memories M11a, M12a, and M13a. The analog memory M11a has a correction value memory M11 that holds and outputs a correction value Cv of “1” or “0”, a transfer gate TrG that receives an output value from the correction value memory M11, and a transfer gate TrG. And an inverter Ivr connected thereto. The transfer gate TrG outputs a voltage that turns on the drive transistor TrC1 when the output value of the correction value memory M11 is “1”, and turns off the drive transistor TrC1 when the output value of the correction memory M11 is “0”. Output voltage (ie, VREF). Each of the analog memories M12a and M13a has a configuration similar to that of the analog memory M11a. The analog memory M12a has a correction value memory M12, and the analog memory 13a has a correction value memory M13.

  The voltages output from the analog memories M11a, M12a, and M13a are applied to the gates of the drive transistors TrC1, TrC2, and TrC3 of the correction circuit C1a. When the applied voltage is a voltage that turns on each of the drive transistors TrC1, TrC2, and TrC3, currents Ic1 to Ic3 are generated, and the currents Ic1 to Ic3 are combined and input to the selection transistor Tr22. As described above, even when the analog memories 11a to M13a are used instead of the digital memories M11 to M13 and the switching elements (select transistors TrC4 to TrC6), it is possible to obtain the same effect as that of the above embodiment.

<E. Image printing device>
As shown in FIG. 1, the exposure heads 10 and 10A according to the above embodiments can be used as a line-type optical head for writing a latent image on an image carrier in an image printing apparatus using an electrophotographic method. . Examples of the image printing apparatus include a printer, a printing part of a copying machine, and a printing part of a facsimile. FIG. 12 is a longitudinal sectional view showing an example of an image printing apparatus using the exposure heads 10 and 10A as a line type optical head. This image printing apparatus is a tandem type full-color image printing apparatus using a belt intermediate transfer body system.

  In this image printing apparatus, four organic EL arrays 10K, 10C, 10M, and 10Y having the same configuration are exposed to four photosensitive drums (image carriers) 110K, 110C, 110M, and 110Y having the same configuration. It is arranged at each position. The organic EL arrays 10K, 10C, 10M, and 10Y are the exposure heads 10 and 10A according to any of the embodiments exemplified above.

  As shown in FIG. 12, the image printing apparatus is provided with a driving roller 121 and a driven roller 122. An endless intermediate transfer belt 120 is wound around these rollers 121 and 122, and an arrow indicates As shown, the periphery of the rollers 121 and 122 is rotated. Although not shown, tension applying means such as a tension roller that applies tension to the intermediate transfer belt 120 may be provided.

  Around the intermediate transfer belt 120, four photosensitive drums 110K, 110C, 110M, and 110Y each having a photosensitive layer on the outer peripheral surface are arranged at a predetermined interval. The subscripts K, C, M, and Y mean that they are used to form black, cyan, magenta, and yellow visible images, respectively. The same applies to other members. The photosensitive drums 110K, 110C, 110M, and 110Y are rotationally driven in synchronization with the driving of the intermediate transfer belt 120.

  Around each photosensitive drum 110 (K, C, M, Y), there is a corona charger 111 (K, C, M, Y), an organic EL array 10 (K, C, M, Y), and development. A device 114 (K, C, M, Y) is arranged. The corona charger 111 (K, C, M, Y) uniformly charges the outer peripheral surface of the corresponding photosensitive drum 110 (K, C, M, Y). The organic EL array 10 (K, C, M, Y) writes an electrostatic latent image on the charged outer peripheral surface of the photosensitive drum. Each organic EL array 10 (K, C, M, Y) is installed such that the arrangement direction of the plurality of light emitting elements P is along the bus (main scanning direction) of the photosensitive drum 110 (K, C, M, Y). Is done. The electrostatic latent image is written by irradiating the photosensitive drum with light by the plurality of light emitting elements P described above. The developing device 114 (K, C, M, Y) forms a visible image, that is, a visible image on the photosensitive drum by attaching toner as a developer to the electrostatic latent image.

  The black, cyan, magenta, and yellow developed images formed by the four-color single-color image forming station are sequentially transferred onto the intermediate transfer belt 120 to be superimposed on the intermediate transfer belt 120. As a result, a full-color image is obtained. Four primary transfer corotrons (transfer devices) 112 (K, C, M, Y) are arranged inside the intermediate transfer belt 120. The primary transfer corotron 112 (K, C, M, Y) is disposed in the vicinity of the photosensitive drum 110 (K, C, M, Y), and the photosensitive drum 110 (K, C, M, Y). The electrostatic image is electrostatically attracted from the toner image to transfer the visible image to the intermediate transfer belt 120 passing between the photosensitive drum and the primary transfer corotron.

  A sheet 102 as an object on which an image is to be finally formed is fed one by one from the sheet feeding cassette 101 by the pickup roller 103, and between the intermediate transfer belt 120 and the secondary transfer roller 126 in contact with the driving roller 121. Sent to the nip. The full-color visible image on the intermediate transfer belt 120 is secondarily transferred to one side of the sheet 102 by the secondary transfer roller 126 and fixed on the sheet 102 through the fixing roller pair 127 as a fixing unit. . Thereafter, the sheet 102 is discharged onto a paper discharge cassette formed in the upper part of the apparatus by a paper discharge roller pair 128.

Next, another embodiment of the image printing apparatus according to the present invention will be described.
FIG. 13 is a longitudinal sectional view of another image printing apparatus using the exposure heads 10 and 10A as a line type optical head. This image printing apparatus is a rotary development type full-color image printing apparatus using a belt intermediate transfer body system. In the image printing apparatus shown in FIG. 13, a corona charger 168, a rotary developing unit 161, an organic EL array 167, and an intermediate transfer belt 169 are provided around the photosensitive drum 165.

  The corona charger 168 uniformly charges the outer peripheral surface of the photosensitive drum 165. The organic EL array 167 writes an electrostatic latent image on the charged outer peripheral surface of the photosensitive drum 165. The organic EL array 167 is the exposure heads 10, 10 </ b> A of the embodiments exemplified above, and is installed so that the arrangement direction of the plurality of light emitting elements P is along the bus line (main scanning direction) of the photosensitive drum 165. The electrostatic latent image is written by irradiating the photosensitive drum 165 with light from these light emitting elements P.

  The developing unit 161 is a drum in which four developing units 163Y, 163C, 163M, and 163K are arranged at an angular interval of 90 °, and can rotate counterclockwise about the shaft 161a. The developing units 163Y, 163C, 163M, and 163K supply yellow, cyan, magenta, and black toners to the photosensitive drum 165, respectively, and attach the toner as a developer to the electrostatic latent image, thereby the photosensitive drum 165. A visible image, that is, a visible image is formed.

  The endless intermediate transfer belt 169 is wound around a driving roller 170a, a driven roller 170b, a primary transfer roller 166, and a tension roller, and is rotated around these rollers in a direction indicated by an arrow. The primary transfer roller 166 transfers the visible image to the intermediate transfer belt 169 that passes between the photosensitive drum and the primary transfer roller 166 by electrostatically attracting the visible image from the photosensitive drum 165.

  Specifically, in the first rotation of the photosensitive drum 165, an electrostatic latent image for a yellow (Y) image is written by the organic array 167, and a developed image of the same color is formed by the developing unit 163Y. The image is transferred to the transfer belt 169. Further, in the next rotation, an electrostatic latent image for a cyan (C) image is written by the organic array 167, a developed image of the same color is formed by the developing device 163C, and an intermediate transfer is performed so as to overlap the yellow developed image. Transferred to the belt 169. Then, during the four rotations of the photosensitive drum 165, yellow, cyan, magenta, and black visible images are sequentially superimposed on the intermediate transfer belt 169. As a result, a full-color visible image is formed on the transfer belt 169. It is formed. When images are finally formed on both sides of a sheet as an object on which an image is to be formed, the same color images of the front and back surfaces are transferred to the intermediate transfer belt 169, and then the front and back surfaces are transferred to the intermediate transfer belt 169. A full-color visible image is obtained on the intermediate transfer belt 169 by transferring the visible image of the next color.

  The image printing apparatus is provided with a sheet conveyance path 174 through which a sheet is passed. The sheets are picked up one by one from the paper feed cassette 178 by the pick-up roller 179, advanced through the sheet transport path 174 by the transport roller, and between the intermediate transfer belt 169 and the secondary transfer roller 171 in contact with the drive roller 170a. Pass through the nip. The secondary transfer roller 171 transfers the developed image to one side of the sheet by electrostatically attracting a full-color developed image from the intermediate transfer belt 169 collectively. The secondary transfer roller 171 can be moved closer to and away from the intermediate transfer belt 169 by a clutch (not shown). The secondary transfer roller 171 is brought into contact with the intermediate transfer belt 169 when a full-color visible image is transferred onto the sheet, and is separated from the secondary transfer roller 171 while the visible image is superimposed on the intermediate transfer belt 169.

  The sheet on which the image has been transferred as described above is conveyed to the fixing device 172 and is passed between the heating roller 172a and the pressure roller 172b of the fixing device 172, whereby the visible image on the sheet is fixed. The sheet after the fixing process is drawn into the discharge roller pair 176 and proceeds in the direction of arrow F. In the case of double-sided printing, after most of the sheet passes through the paper discharge roller pair 176, the paper discharge roller pair 176 is rotated in the reverse direction and introduced into the double-sided printing conveyance path 175 as indicated by an arrow G. The Then, the visible image is transferred to the other surface of the sheet by the secondary transfer roller 171, the fixing process is performed again by the fixing device 172, and then the sheet is discharged by the discharge roller pair 176.

  Since the image printing apparatus illustrated in FIGS. 12 and 13 uses the light emitting element P as an exposure unit, the apparatus can be made smaller than when a laser scanning optical system is used. Note that the exposure head of the present invention can also be employed in electrophotographic image printing apparatuses other than those exemplified above. For example, the exposure head according to the present invention can be applied to an image printing apparatus that directly transfers a visible image from a photosensitive drum to a sheet without using an intermediate transfer belt, and an image printing apparatus that forms a monochrome image. Is possible.

  The image forming apparatus to which the exposure head according to the present invention is applied is not limited to an image printing apparatus. For example, the exposure head of the present invention is also used as a lighting device in various electronic devices. Examples of such electronic devices include facsimile machines, copiers, multifunction machines, and printers. In these electronic apparatuses, an exposure head in which a plurality of light emitting elements are arranged in a planar shape is suitably employed.

1 is a perspective view showing a partial configuration of an image printing apparatus using an exposure head according to a first embodiment of the present invention. It is explanatory drawing which shows typically arrangement | positioning of a light emitting element. It is a block diagram which shows the electrical structure of an exposure head. It is a circuit diagram which shows the circuit structure of the process unit in an exposure head. It is a graph which shows the ratio of exposure power. It is a circuit diagram which shows the circuit structure of the processing unit which concerns on 2nd Embodiment. It is a graph which shows the ratio of exposure power. It is a block diagram which shows the electrical structure of the exposure head which concerns on 3rd Embodiment. It is a circuit diagram which shows the circuit structure of the process unit in an exposure head. It is a graph which shows the ratio of exposure power. It is a figure which concerns on a modification. It is a longitudinal cross-sectional view which shows the structure of the image printing apparatus using the exposure head which concerns on this invention. It is a longitudinal cross-sectional view which shows the structure of the other image printing apparatus using the exposure head which concerns on this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10,10A ... Exposure head, 15 ... Condensing lens array, 20, 20A ... Control circuit (control means), 110 ... Photosensitive drum (image carrier), C, C1, C11, C12 ... Correction circuit, Cv ... correction value, d ... gradation signal, DR ... drive circuit, DR11 ... first drive circuit, DR12, DR12A ... second drive circuit, GND ... ground potential, Iv1, Iv2, Ic1, Ic2, Ic3 ... current, Ic, IcA ... correction current, Ip1 ... first drive current, Ip2 ... second drive current, Ivr ... inverter, M, MA ... memory circuit, M11, M12, M13: Correction value memory, M11a, M12a, M13a: Analog memory, Nc: Node, P: Light emitting element, Tr11, Tr21, TrC1, TrC2, TrC3: Drive transistor, Tr12, Tr22, TrC4 TrC5, TrC6 ...... select transistor (switching element), TrG ...... transfer gate, U, UA ...... processing unit, VEL ...... supply voltage, VREF ...... reference voltage.

Claims (8)

By irradiating light emitted from each of the first and second light emitting elements to one exposure position of the image carrier at different timings, it is possible to form an image corresponding to the gradation designated at the exposure position. Exposure head,
A first drive circuit that generates a first drive current and supplies the first drive current to the first light emitting element;
One memory circuit for storing a correction value set so that a total amount of light emitted from the first and second light emitting elements is equal to a light amount corresponding to the gradation;
One correction circuit for generating a correction current according to the correction value supplied from the memory circuit;
A second drive circuit that generates a predetermined current and combines it with the correction current to supply the second light-emitting element as a second drive current;
Comprising
An exposure head in which the first light emitting element outputs an emitted light with a light amount corresponding to the first drive current, and the second light emitting element outputs an emitted light with a light amount according to the second drive current. The correction value is obtained by supplying only the correction current to the second light emitting element, so that the second light emitting element subtracts the light quantity of the light emitted from the first light emitting element from the light quantity corresponding to the gradation. The amount of light
The exposure head according to claim 1, wherein the second drive circuit supplies the correction current as the second drive current to the second light emitting element without generating the predetermined current. By irradiating light emitted from each of the first and second light emitting elements to one exposure position of the image carrier at different timings, it is possible to form an image corresponding to the gradation designated at the exposure position. Exposure head,
The sum of the amounts of light emitted from the first and second light emitting elements is set to be equal to the amount of light corresponding to the gradation, and a correction value common to the first and second light emitting elements is stored. One memory circuit to
A first correction circuit that generates a first correction current corresponding to the correction value supplied from the memory circuit and supplies the first correction current to the first drive circuit;
A second correction circuit that generates a second correction current corresponding to the correction value supplied from the memory circuit and supplies the second correction current to the second drive circuit;
A first drive circuit that generates a first current and combines it with the first correction current to supply the first light-emitting element as a first drive current;
A second drive circuit that generates a second current and combines it with the second correction current to supply the second light-emitting element as a second drive current substantially equal to the first drive current;
Comprising
An exposure head in which the first light emitting element outputs an emitted light with a light amount corresponding to the first drive current, and the second light emitting element outputs an emitted light with a light amount according to the second drive current.   4. The correction circuit according to claim 1, wherein the correction circuit includes a plurality of current generation circuits having different weights, and generates the correction current by combining currents output from the current generation circuits. The exposure head described. The first drive circuit includes a first switching element that is provided in a path for supplying the first drive current to the first light emitting element and is controlled to be turned on and off.
The second drive circuit includes a second switching element that is provided in a path for supplying the second drive current to the second light emitting element and is controlled to be turned on and off.
5. The exposure head according to claim 1, further comprising a control unit configured to turn on the first and second switching elements for a time corresponding to the designated gradation at different timings. 6. An exposure head according to any one of claims 1 to 5,
An image carrier on which an image is formed by light emitted from each of the first and second light emitting elements;
An image forming apparatus comprising: An exposure method for forming an image corresponding to the gradation designated at the exposure position by irradiating light emitted from each of the first and second light emitting elements to one exposure position of the image carrier at different timings. There,
Generating a correction current according to a correction value set so that a total amount of light emitted from the first and second light emitting elements is equal to a light amount according to the designated gradation;
Generating a first driving current and supplying the first driving current to the first light emitting element to cause the first light emitting element to emit light;
An exposure method in which a second driving current corrected by the correction current is supplied to the second light emitting element to cause the second light emitting element to emit light. An exposure method for forming an image corresponding to the gradation designated at the exposure position by irradiating light emitted from each of the first and second light emitting elements to one exposure position of the image carrier at different timings. There,
The sum of the amounts of light emitted from the first and second light emitting elements is set to be equal to the amount of light corresponding to the gradation, and the correction value is common to the first and second light emitting elements. In response, a first correction current is generated,
Generating a first driving current obtained by combining the first current and the first correction current and supplying the first driving current to the first light emitting element to cause the first light emitting element to emit light;
Generating a second correction current according to the common correction value;
An exposure method in which a second drive current obtained by combining a second current and the second correction current is generated and supplied to the second light emitting element to cause the second light emitting element to emit light.

Images