JP2009135453A5 - - Google Patents
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- JP2009135453A5 JP2009135453A5 JP2008273215A JP2008273215A JP2009135453A5 JP 2009135453 A5 JP2009135453 A5 JP 2009135453A5 JP 2008273215 A JP2008273215 A JP 2008273215A JP 2008273215 A JP2008273215 A JP 2008273215A JP 2009135453 A5 JP2009135453 A5 JP 2009135453A5
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- Prior art keywords
- single crystal
- crystal semiconductor
- region
- pulsed laser
- manufacturing
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- 239000004065 semiconductor Substances 0.000 claims 35
- 239000013078 crystal Substances 0.000 claims 20
- 239000000758 substrate Substances 0.000 claims 15
- 238000000034 method Methods 0.000 claims 12
- 238000004519 manufacturing process Methods 0.000 claims 11
- 230000001678 irradiating effect Effects 0.000 claims 4
- 230000008018 melting Effects 0.000 claims 4
- 238000002844 melting Methods 0.000 claims 4
- 238000001069 Raman spectroscopy Methods 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 230000007547 defect Effects 0.000 claims 2
- 150000002500 ions Chemical class 0.000 claims 2
- 230000003746 surface roughness Effects 0.000 claims 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 239000004020 conductor Substances 0.000 claims 1
- 239000012212 insulator Substances 0.000 claims 1
- 150000001282 organosilanes Chemical class 0.000 claims 1
Claims (12)
前記単結晶半導体基板の主表面に絶縁層を形成し、
前記絶縁層と、ベース基板とを接合させ、
前記単結晶半導体基板を、前記損傷領域において分離させることにより、前記ベース基板上に単結晶半導体層を形成し、
前記単結晶半導体層の一部の領域にパルスレーザー光を照射することにより、前記単結晶半導体層の欠陥を低減し、且つ、表面の平坦性を向上させ、
前記パルスレーザー光の端部以外における光強度は、前記単結晶半導体層が完全溶融する光強度未満、且つ、完全溶融と部分溶融との境界となる光強度の８５％以上であり、
前記パルスレーザー光の端部における光強度は、前記境界となる光強度の８５％未満であり、
前記パルスレーザー光の端部以外が照射された領域の前記単結晶半導体層を用いて半導体素子のチャネル形成領域を形成することを特徴とする半導体装置の作製方法。 Irradiating ions to the main surface of the single crystal semiconductor substrate to form a damaged region,
Forming an insulating layer on the main surface of the single crystal semiconductor substrate;
Bonding the insulating layer and the base substrate;
Forming the single crystal semiconductor layer on the base substrate by separating the single crystal semiconductor substrate in the damaged region;
By irradiating a part of the single crystal semiconductor layer with pulsed laser light, the defects of the single crystal semiconductor layer are reduced, and the surface flatness is improved.
The light intensity at other than the end of the pulse laser beam is less than the light intensity at which the single crystal semiconductor layer is completely melted, and is 85% or more of the light intensity at the boundary between complete melting and partial melting,
The light intensity at the end of the pulsed laser light is less than 85% of the light intensity serving as the boundary,
A method for manufacturing a semiconductor device, wherein a channel formation region of a semiconductor element is formed using the single crystal semiconductor layer in a region irradiated with a region other than an end portion of the pulsed laser light.
ベース基板上に絶縁層を形成し、
前記単結晶半導体基板の前記主表面と、前記絶縁層とを接合させ、
前記単結晶半導体基板を、前記損傷領域において分離させることにより、前記ベース基板上に単結晶半導体層を形成し、
前記単結晶半導体層の一部の領域にパルスレーザー光を照射することにより、前記単結晶半導体層の欠陥を低減し、且つ、表面の平坦性を向上させ、
前記パルスレーザー光の端部以外における光強度は、前記単結晶半導体層が完全溶融する光強度未満、且つ、完全溶融と部分溶融との境界となる光強度の８５％以上であり、
前記パルスレーザー光の端部における光強度は、前記境界となる光強度の８５％未満であり、
前記パルスレーザー光の端部以外が照射された領域の前記単結晶半導体層を用いて半導体素子のチャネル形成領域を形成することを特徴とする半導体装置の作製方法。 Irradiating ions to the main surface of the single crystal semiconductor substrate to form a damaged region,
Forming an insulating layer on the base substrate;
Bonding the main surface of the single crystal semiconductor substrate and the insulating layer;
Forming the single crystal semiconductor layer on the base substrate by separating the single crystal semiconductor substrate in the damaged region;
By irradiating a part of the single crystal semiconductor layer with pulsed laser light, the defects of the single crystal semiconductor layer are reduced, and the surface flatness is improved.
The light intensity at other than the end of the pulse laser beam is less than the light intensity at which the single crystal semiconductor layer is completely melted, and is 85% or more of the light intensity at the boundary between complete melting and partial melting,
The light intensity at the end of the pulsed laser light is less than 85% of the light intensity serving as the boundary,
A method for manufacturing a semiconductor device, wherein a channel formation region of a semiconductor element is formed using the single crystal semiconductor layer in a region irradiated with a region other than an end portion of the pulsed laser light.
前記パルスレーザー光の端部以外が照射された領域の前記単結晶半導体層表面の平均面粗さは１．５ｎｍ未満であり、二乗平方根粗さは２ｎｍ未満であり、
前記パルスレーザー光の端部が照射された領域の前記単結晶半導体層表面の平均面粗さは１．５ｎｍ以上であり、二乗平方根粗さは２ｎｍ以上であることを特徴とする半導体装置の作製方法。 In claim 1 or 2 ,
The average surface roughness of the surface of the single crystal semiconductor layer in the region irradiated with an area other than the edge of the pulsed laser light is less than 1.5 nm, and the square root roughness is less than 2 nm.
The average surface roughness of the surface of the single crystal semiconductor layer in the region irradiated with the edge of the pulsed laser light is 1.5 nm or more, and the square root roughness is 2 nm or more. Method.
前記パルスレーザー光の端部以外が照射された領域の前記単結晶半導体層のラマンピークの波数は５２０．４ｃｍ−１以上であり、
前記パルスレーザー光の端部が照射された領域の前記単結晶半導体層のラマンピークの波数は５２０．４ｃｍ−１未満であることを特徴とする半導体装置の作製方法。 In any one of Claims 1 thru | or 3 ,
The wave number of the Raman peak of the single crystal semiconductor layer in the region irradiated with a portion other than the end of the pulse laser beam is 520.4 cm −1 or more,
A method for manufacturing a semiconductor device, wherein a wave number of a Raman peak of the single crystal semiconductor layer in a region irradiated with an end portion of the pulsed laser light is less than 520.4 cm −1 .
前記ベース基板は、絶縁体でなる絶縁性基板であることを特徴とする半導体装置の作製方法。The method for manufacturing a semiconductor device, wherein the base substrate is an insulating substrate made of an insulator.
前記ベース基板は、導電体でなる導電性基板、または半導体でなる半導体基板であることを特徴とする半導体装置の作製方法。The method for manufacturing a semiconductor device, wherein the base substrate is a conductive substrate made of a conductor or a semiconductor substrate made of a semiconductor.
前記パルスレーザー光の端部以外が照射された領域は、前記パルスレーザー光が１回のみ照射された領域であることを特徴とする半導体装置の作製方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein the region other than the end portion of the pulsed laser beam is irradiated with the pulsed laser beam only once.
前記パルスレーザー光の端部以外が照射された領域は、前記パルスレーザー光の端部以外が複数回照射された領域であることを特徴とする半導体装置の作製方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein the region other than the end portion of the pulse laser beam is irradiated with a region irradiated with a plurality of portions other than the end portion of the pulse laser beam.
前記絶縁層は、有機シランガスを用いて化学気相成長法により形成される絶縁層を含むことを特徴とする半導体装置の作製方法。 Oite to any one of claims 1 to 8,
The method for manufacturing a semiconductor device, wherein the insulating layer includes an insulating layer formed by chemical vapor deposition using an organosilane gas.
前記絶縁層は、積層構造で形成されることを特徴とする半導体装置の作製方法。 In any one of Claims 1 thru | or 9 ,
The method for manufacturing a semiconductor device, wherein the insulating layer has a stacked structure.
前記パルスレーザー光は、エキシマレーザー光であることを特徴とする半導体装置の作製方法。 In any one of Claims 1 thru | or 10 ,
The method for manufacturing a semiconductor device, wherein the pulsed laser light is excimer laser light.
前記パルスレーザー光は、線状の形状を有することを特徴とする半導体装置の作製方法。 In any one of Claims 1 thru | or 11 ,
The method for manufacturing a semiconductor device, wherein the pulsed laser light has a linear shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008273215A JP2009135453A (en) | 2007-10-30 | 2008-10-23 | Method for manufacturing semiconductor device, semiconductor device, and electronic device |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007281631 | 2007-10-30 | ||
| JP2008273215A JP2009135453A (en) | 2007-10-30 | 2008-10-23 | Method for manufacturing semiconductor device, semiconductor device, and electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2009135453A JP2009135453A (en) | 2009-06-18 |
| JP2009135453A5 true JP2009135453A5 (en) | 2011-11-17 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008273215A Withdrawn JP2009135453A (en) | 2007-10-30 | 2008-10-23 | Method for manufacturing semiconductor device, semiconductor device, and electronic device |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US8435871B2 (en) |
| JP (1) | JP2009135453A (en) |
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| JP5503876B2 (en) * | 2008-01-24 | 2014-05-28 | 株式会社半導体エネルギー研究所 | Manufacturing method of semiconductor substrate |
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| DE102011002236A1 (en) * | 2011-04-21 | 2012-10-25 | Dritte Patentportfolio Beteiligungsgesellschaft Mbh & Co.Kg | Process for producing a polycrystalline layer |
| KR102040242B1 (en) * | 2011-05-12 | 2019-11-05 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Light-emitting device and electronic device using the light-emitting device |
| JP5464192B2 (en) * | 2011-09-29 | 2014-04-09 | 株式会社デンソー | Manufacturing method of semiconductor device |
| US9472776B2 (en) | 2011-10-14 | 2016-10-18 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing sealed structure including welded glass frits |
| JP2013101923A (en) | 2011-10-21 | 2013-05-23 | Semiconductor Energy Lab Co Ltd | Method of heating dispersion composition and method of forming glass pattern |
| JP6175294B2 (en) * | 2012-06-25 | 2017-08-02 | 株式会社半導体エネルギー研究所 | Method for manufacturing functional substrate and method for manufacturing semiconductor device |
| JP2014107393A (en) * | 2012-11-27 | 2014-06-09 | Mitsubishi Heavy Ind Ltd | Normal temperature bonding device, wafer having normal temperature bonding device and normal temperature bonding method |
| TWI695525B (en) * | 2014-07-25 | 2020-06-01 | 日商半導體能源研究所股份有限公司 | Separation method, light-emitting device, module, and electronic device |
| WO2016081367A1 (en) | 2014-11-18 | 2016-05-26 | Sunedison Semiconductor Limited | HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED BY He-N2 CO-IMPLANTATION |
| WO2016081356A1 (en) | 2014-11-18 | 2016-05-26 | Sunedison Semiconductor Limited | High resistivity semiconductor-on-insulator wafer and a method of manufacturing |
| US10283402B2 (en) | 2015-03-03 | 2019-05-07 | Globalwafers Co., Ltd. | Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress |
| WO2016196011A1 (en) | 2015-06-01 | 2016-12-08 | Sunedison Semiconductor Limited | A method of manufacturing silicon germanium-on-insulator |
| CN108780776B (en) | 2015-11-20 | 2023-09-29 | 环球晶圆股份有限公司 | Manufacturing method for flattening semiconductor surface |
| JP6416140B2 (en) * | 2016-02-12 | 2018-10-31 | 信越化学工業株式会社 | Polycrystalline silicon rod and method for selecting polycrystalline silicon rod |
| US10573550B2 (en) * | 2016-03-07 | 2020-02-25 | Globalwafers Co., Ltd. | Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof |
| US11848227B2 (en) * | 2016-03-07 | 2023-12-19 | Globalwafers Co., Ltd. | Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment |
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| KR102439602B1 (en) | 2016-06-08 | 2022-09-01 | 글로벌웨이퍼스 씨오., 엘티디. | Single-crystal silicon ingots with high resistivity and wafers with improved mechanical strength |
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-
2008
- 2008-10-23 JP JP2008273215A patent/JP2009135453A/en not_active Withdrawn
- 2008-10-27 US US12/259,241 patent/US8435871B2/en not_active Expired - Fee Related
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