JP2009123298A - 半導体集積回路装置 - Google Patents

半導体集積回路装置 Download PDF

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Publication number
JP2009123298A
JP2009123298A JP2007297479A JP2007297479A JP2009123298A JP 2009123298 A JP2009123298 A JP 2009123298A JP 2007297479 A JP2007297479 A JP 2007297479A JP 2007297479 A JP2007297479 A JP 2007297479A JP 2009123298 A JP2009123298 A JP 2009123298A
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JP
Japan
Prior art keywords
cpu
address
data
signal
semiconductor memory
Prior art date
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Pending
Application number
JP2007297479A
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English (en)
Japanese (ja)
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JP2009123298A5 (enExample
Inventor
Shinya Kajiyama
新也 梶山
Yutaka Shinagawa
裕 品川
Makoto Mizuno
真 水野
Hideo Kasai
秀男 葛西
Takao Watabe
隆夫 渡部
Riichiro Takemura
理一郎 竹村
Tomonori Sekiguchi
知紀 関口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2007297479A priority Critical patent/JP2009123298A/ja
Priority to US12/269,098 priority patent/US7848177B2/en
Priority to CN2008101814389A priority patent/CN101436430B/zh
Priority to EP08253714A priority patent/EP2065893B1/en
Publication of JP2009123298A publication Critical patent/JP2009123298A/ja
Publication of JP2009123298A5 publication Critical patent/JP2009123298A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Read Only Memory (AREA)
  • Memory System (AREA)
JP2007297479A 2007-11-16 2007-11-16 半導体集積回路装置 Pending JP2009123298A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2007297479A JP2009123298A (ja) 2007-11-16 2007-11-16 半導体集積回路装置
US12/269,098 US7848177B2 (en) 2007-11-16 2008-11-12 Semiconductor integrated circuit device
CN2008101814389A CN101436430B (zh) 2007-11-16 2008-11-13 半导体集成电路装置
EP08253714A EP2065893B1 (en) 2007-11-16 2008-11-13 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007297479A JP2009123298A (ja) 2007-11-16 2007-11-16 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JP2009123298A true JP2009123298A (ja) 2009-06-04
JP2009123298A5 JP2009123298A5 (enExample) 2010-08-19

Family

ID=40303728

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007297479A Pending JP2009123298A (ja) 2007-11-16 2007-11-16 半導体集積回路装置

Country Status (4)

Country Link
US (1) US7848177B2 (enExample)
EP (1) EP2065893B1 (enExample)
JP (1) JP2009123298A (enExample)
CN (1) CN101436430B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8576638B2 (en) 2010-04-29 2013-11-05 Samsung Electronics Co., Ltd. Non-volatile memory device and non-volatile memory system having the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201225529A (en) * 2010-12-03 2012-06-16 Fortune Semiconductor Corp Test mode controller and electronic apparatus with self-testing thereof
US8593878B2 (en) 2011-11-17 2013-11-26 Macronix International Co., Ltd. Program method and flash memory using the same
CN103514956B (zh) * 2012-06-15 2016-04-13 晶豪科技股份有限公司 半导体存储器元件及其测试方法
US9190172B2 (en) * 2013-01-24 2015-11-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP6359491B2 (ja) * 2015-06-12 2018-07-18 東芝メモリ株式会社 半導体記憶装置
US11048583B1 (en) * 2015-09-11 2021-06-29 Green Mountain Semiconductor Inc. Flexible, low-latency error correction architecture for semiconductor memory products
DE102015221064A1 (de) * 2015-10-28 2017-05-04 Robert Bosch Gmbh Anordnung aus wenigstens zwei Mikrocontrollern und Verfahren zur Herstellung einer solchen Anordnung
KR102557324B1 (ko) * 2016-02-15 2023-07-20 에스케이하이닉스 주식회사 메모리 장치
KR102682253B1 (ko) * 2016-11-29 2024-07-08 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작방법
US9997212B1 (en) * 2017-04-24 2018-06-12 Micron Technology, Inc. Accessing data in memory
US10347307B2 (en) * 2017-06-29 2019-07-09 SK Hynix Inc. Skew control circuit and interface circuit including the same
JP2019040646A (ja) * 2017-08-22 2019-03-14 東芝メモリ株式会社 半導体記憶装置
US11360704B2 (en) 2018-12-21 2022-06-14 Micron Technology, Inc. Multiplexed signal development in a memory device
CN111489773B (zh) * 2019-01-29 2023-04-07 合肥格易集成电路有限公司 一种读取数据的电路、非易失存储器以及读取数据的方法
US11676657B2 (en) * 2020-04-16 2023-06-13 Mediatek Inc. Time-interleaving sensing scheme for pseudo dual-port memory
US11443823B2 (en) * 2020-10-29 2022-09-13 SambaNova Systems, Inc. Method and circuit for scan dump of latch array
US12321262B2 (en) * 2020-12-28 2025-06-03 Kioxia Corporation Memory system which orders data fetching from a latch circuit during execution of a read operation
JP7614966B2 (ja) * 2021-07-14 2025-01-16 キオクシア株式会社 半導体記憶装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2855633B2 (ja) 1989-02-03 1999-02-10 ミノルタ株式会社 マルチプロセッサシステムにおけるデュアルポートメモリの故障診断装置
JP2830594B2 (ja) 1992-03-26 1998-12-02 日本電気株式会社 半導体メモリ装置
US5375089A (en) 1993-10-05 1994-12-20 Advanced Micro Devices, Inc. Plural port memory system utilizing a memory having a read port and a write port
JP2001306307A (ja) 2000-04-25 2001-11-02 Hitachi Ltd ファームウェアの処理方法。
JP4704541B2 (ja) * 2000-04-27 2011-06-15 エルピーダメモリ株式会社 半導体集積回路装置
US6246634B1 (en) 2000-05-01 2001-06-12 Silicon Storage Technology, Inc. Integrated memory circuit having a flash memory array and at least one SRAM memory array with internal address and data bus for transfer of signals therebetween
JP4331966B2 (ja) 2003-04-14 2009-09-16 株式会社ルネサステクノロジ 半導体集積回路
US7349285B2 (en) 2005-02-02 2008-03-25 Texas Instruments Incorporated Dual port memory unit using a single port memory core
JP2007297479A (ja) 2006-04-28 2007-11-15 Hitachi Chem Co Ltd 樹脂組成物及び電気機器絶縁物の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8576638B2 (en) 2010-04-29 2013-11-05 Samsung Electronics Co., Ltd. Non-volatile memory device and non-volatile memory system having the same

Also Published As

Publication number Publication date
CN101436430B (zh) 2012-02-29
EP2065893A1 (en) 2009-06-03
EP2065893B1 (en) 2012-06-06
US7848177B2 (en) 2010-12-07
CN101436430A (zh) 2009-05-20
US20090129173A1 (en) 2009-05-21

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