JP2009111311A - Multilayered printed wiring board, and manufacturing method of multilayered printed wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve thermal resistance and thermal shock resistance by raising adhesion between the pattern of an inner layer and the insulating material of an outer layer. <P>SOLUTION: When manufacturing the inner layer 10a of a multilayered printed wiring board having three or more pattern layers in its thickness direction, following treatments are performed. A current carrying layer 13 made of a metal coat is formed on the surface of a base material 11 made of the insulating material. Subsequently, a plated resist 21a is formed in a portion other than a pattern forming portion on the current carrying layer. Then, a pattern 14 is formed in the pattern forming portion other than the plated resist 21a by electrolytic plating using the current carrying layer 13. A rough coat 15 is formed on the surface of the pattern 14 formed by a pattern forming process by forming a dendritic electrodeposition layer and a mat plated layer in turn, The plated resist 21a and the current carrying layer 13 below the plated resist 21a are removed. The inner layer 10a is thus manufacture. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a multilayer printed wiring board, and more particularly to a multilayer printed wiring board excellent in solder heat resistance and thermal shock resistance and a method for manufacturing the same.

  The multilayer printed wiring board is a printed wiring board having three or more pattern layers in order to increase the density, and is used in various devices such as a mobile phone and a portable information terminal.

Such a multilayer printed wiring board is manufactured through a process as shown in FIG. In the illustrated example, a multilayer printed wiring board 101 having four layers is shown.
First, a through hole 103 is formed in a copper clad laminate 102 (see FIG. 6A) in which a copper foil 102b is laminated on both surfaces of a resin plate 102a (see FIG. 6B), and then the inner wall of the through hole 103 is formed. Through-hole plating 104 is performed by electroless plating and electrolytic plating so that both surfaces of the copper-clad laminate 102 can be energized (see FIG. 6C). This portion finally becomes an inner through hole 103a for energizing the inner layer (see FIG. 6G).

  Subsequently, although illustration is omitted, an etching resist is formed only on a portion where a pattern is to be formed by a well-known means, and then etching is performed to leave a copper foil 102b on the portion where the etching resist is formed. Then, the etching resist is removed to expose the pattern 105 (see FIG. 6D).

  Next, a blackening process is performed on the pattern 105 (see FIG. 6E). This is for increasing the adhesion between the pattern 105 made of copper foil and the insulating material, and is a process for forming a cuprous oxide film 105 a on the surface of the pattern 105.

  Thereafter, in order to form the outer layer on both surfaces of the patterned base material 106 which is the inner layer, a laminate of the prepreg 107 and the copper foil 108 is stacked (see FIG. 6F) and hot-pressed (FIG. 6G). )reference). Next, after opening the through hole 109 (see FIG. 6 (h)), the outer layer is formed through the same process as described above (see FIGS. 6 (h), (i), (j)). In the figure, 111 is a through-hole plating for energizing between the inner and outer layers, 109a is a through-hole, and 112 is a pattern.

  Finally, the surface of the outer layer pattern is roughened by buffing, blackening, or the like, and then solder resist processing such as solder resist coating, semi-cure, exposure, and development is performed to form a solder resist 113 (FIG. 6). (See (k)).

  That is, the inner layer pattern 105 is formed by removing unnecessary portions of the copper foil 102b. Further, the roughening process on the surface of the inner layer pattern 105 is performed by a blackening process.

  As described above, since the surface of the inner layer pattern 105 is roughened, sufficient adhesion to the insulating material is likely to be obtained, but good adhesion is not necessarily obtained. When the multilayer printed wiring board 101 manufactured as described above was subjected to an evaluation test (3000 cycle thermal shock test (−80 to 120 ° C.)) required as an in-vehicle component, delamination and resist peeling were observed.

As a cause of this, firstly, since the roughening of the pattern of the inner and outer layers is performed by blackening treatment or buffing, it is considered that the anchor effect is weak.
Second, it is considered that the pattern is formed by removing unnecessary portions from the copper foil. That is, as shown in FIG. 7A, after forming an etching resist 114 on the copper foil 102a, etching is performed and the etching resist 114 is removed (see FIG. 7B). (See FIG. 7C). In the etching, since the etching depth differs between the front surface side and the lower surface side of the copper foil 102a, as shown in FIG. 7D, a trapezoidal cross section having a draft is formed.

  As disclosed in Patent Document 1 below, a method is disclosed in which after a plating resist is formed on an insulating layer, a conductive layer is formed on the insulating layer by electroless plating.

  Also, as disclosed in Patent Document 2 below, in the copper foil surface roughening treatment method, a dendritic copper electrodeposition layer is formed and then the dendritic copper is changed to bumpy copper by electrolytic treatment. Has been.

JP-A-8-148808 JP 2005-353920 A

  However, in the method of Patent Document 1, it is said that the adhesion strength of a conductive layer formed by electroless plating can be improved, but the adhesion with an insulating layer further laminated on this conductive layer is disclosed. Not. Moreover, although the method of patent document 2 describes the method of roughening the surface of copper foil by performing electrolytic treatment after forming a dendritic copper electrodeposition layer, this removed the copper foil by etching. This is to prevent the residual copper phenomenon from occurring on the resin base material, and it does not improve adhesion to the insulating layer laminated on the copper foil and prevent delamination or the like.

  Accordingly, an object of the present invention is to improve the solder heat resistance and thermal shock resistance by improving the adhesion between the inner layer pattern and the outer insulating material by a novel process.

  A means therefor is a method for producing an inner layer of a multilayer printed wiring board having three or more pattern layers in the thickness direction, and at least a surface of a base material made of an insulating material is provided with a conductive layer made of a metal film. An electroplating layer forming step, a plating resist forming step for forming a plating resist on a portion other than the pattern forming portion on the energizing layer, and an electrolysis using the above energizing layer for a pattern forming portion other than the plating resist. A pattern forming step for forming a pattern by plating, and a rough surface coating for forming a rough surface coating by sequentially forming a dendritic electrodeposition layer and a matte plating layer on the surface of the pattern formed by the pattern forming step Multilayer printed wiring having a forming step, the plating resist, and a removing step for removing the conductive layer in the plating resist forming portion Which is the inner layer of the manufacturing method.

  Another means is a method for producing a multilayer printed wiring board having three or more pattern layers in the thickness direction, and at least the surface is formed with a conductive layer made of a metal film on the surface of a base material made of an insulating material. An electroplating layer forming step, a plating resist forming step for forming a plating resist on a portion other than the pattern forming portion on the energizing layer, and an electroplating using the above energizing layer on a pattern forming portion other than the plating resist A pattern forming step for forming a pattern, and a rough surface film forming step for forming a rough surface film by forming a dendritic electrodeposition layer and a matte plating layer in order on the surface of the pattern formed by the pattern forming step And a method for producing a multilayer printed wiring board, comprising: a plating resist; and a removal step of removing the conductive layer in the plating resist forming portion A.

  The method for producing a multilayer printed wiring board includes an insulating layer coating step in which an insulating plate made of an insulating material is laminated and heat-pressed after the removing step, and a metal film is formed on the surface of the insulating layer coated in the insulating layer coating step. An outer layer forming energizing layer forming step for forming an energizing layer, an outer layer forming plating resist forming step for forming a plating resist on portions other than the pattern forming portion on the energizing layer, and pattern formation on portions other than the plating resist A pattern forming process for an outer layer in which a pattern is formed by electrolytic plating using the above-described current-carrying layer, and a dendritic electrodeposition layer and a matte layer which are sequentially formed on the surface of the pattern formed by the pattern forming process for the outer layer In the outer surface rough surface film forming step of forming a rough surface film by forming the plating layer, the plating resist, and the plating resist forming portion And an outer layer forming removal step of removing the conductive layer, may in which the solder resist forming step of forming a solder resist are performed.

Still another means is an inner layer of the multilayer printed wiring board, which is provided with a knurled unevenness on the surface of the pattern.
In the inner layer of this multilayer printed wiring board, it is preferable that the side surface of the pattern has a substantially vertical shape.

  Another means is a multilayer printed wiring board having an inner layer of the multilayer printed wiring board.

  As described above, according to the present invention, a pattern is formed by the current-carrying portion and the plating resist, and a rough surface film is formed on the formed pattern by the dendritic electrodeposition layer and the matte plating. Since the resist and unnecessary current-carrying portions are removed, the side surfaces of the pattern stand vertically or substantially vertically, and the rough surface film has knurled irregularities.

  For this reason, the adhesion strength between the pattern and the insulating layer stacked on the pattern can be improved, the occurrence of delamination and the like can be suppressed, and high solder heat resistance and thermal shock resistance can be obtained.

  Moreover, since the pattern is formed by plating, an etching process for etching the copper foil can be omitted. As a result, it is possible to reduce the cost for the equipment required for manufacturing the multilayer printed wiring board.

An embodiment for carrying out the present invention will be described below with reference to the drawings.
FIG. 1 is an explanatory view showing a main part of a method for manufacturing a multilayer printed wiring board and a method for manufacturing an inner layer of the multilayer printed wiring board, and FIG. 2 is a schematic diagram showing a cross-sectional structure of a rough coating formed on the surface of the pattern. FIGS. 3 and 3 are schematic views showing the formation of the rough surface coating of the inner layer pattern and its action state, and FIG. 4 is an explanatory view showing the process of forming the outer layer.

As shown in these drawings, for the purpose of improving the adhesion between the pattern 14 of the inner layer 10a and the insulating material and improving the solder heat resistance and thermal shock resistance, at least the surface of the base material 11 made of the insulating material is used. A conductive layer forming step (see FIG. 1C) for forming a conductive layer 13 made of a metal coating on the surface, and a plating resist forming step for forming a plating resist 21a on a portion other than the pattern forming portion on the conductive layer 13 (See FIG. 1 (e)), and a pattern forming step (see FIG. 1 (f)) for forming a pattern 14 on the pattern forming portion other than the plating resist 21a by electrolytic plating using the above-described conductive layer 13. The rough coating 15 is formed on the surface of the pattern 14 formed by the pattern formation step by forming a dendritic copper electrodeposition layer and a matte plating layer sequentially. The surface coating formation process (see FIG. 1 (g)), was achieved by the method having the above-described plating resist 21a, and a removal step of removing the energization layer 13 in the plating resist formation portion (see FIG. 1 (h)).
The substrate 11 may be a patterned substrate on which a pattern is formed.

  In addition, after the above-described removal step, an insulating layer coating step (see FIGS. 4A and 4B) in which the prepreg 16a is stacked and hot pressed, and the surface of the insulating layer 16 coated in the insulating layer coating step are applied. An outer layer forming energization layer forming step (see FIG. 4D) for forming an energization layer 19 made of a metal coating, and an outer layer formation for forming a plating resist 23a on a portion other than the pattern forming portion on the energization layer 19 Pattern formation for the outer layer in which the pattern 17 is formed by electrolytic plating using the above-described conductive layer 19 on the pattern formation portion other than the plating resist 23a in the plating resist formation step (see FIGS. 4E and 4F). A rough surface is formed by sequentially forming a dendritic copper electrodeposition layer and a dull plating layer on the surface of the pattern 17 formed by the step (see FIG. 4G) and the pattern forming step for the outer layer. A rough surface film forming step for forming the film 15 (see FIG. 4 (h)), a plating resist 23a, and an outer layer forming removing step for removing the conductive layer 19 in the plating resist forming portion (see FIG. 4 (i)). If the solder resist forming step (see FIG. 4J) for forming the solder resist 20 is performed, the multilayer printed wiring board 10 can be formed.

Hereinafter, a four-layer multilayer printed wiring board 10 will be described as an example.
As shown in FIG. 1A, a resin plate having an insulating property is used for the base material 11, and a through hole is formed at a position where the inner through hole 12a is to be formed in the base material 11 by a known appropriate means. 12 is formed (refer to through-hole forming step, FIG. 1B). The base material 11 should just consist of an insulating material at least on both surfaces, and can also use what has a copper plate and an aluminum plate as a core.

  Next, the conductive layer 13 is formed by performing electroless plating after desmearing, surface roughening, or the like, if necessary (conductive layer forming step, see FIG. 1C). The conductive layer 13 (electroless plating) can be formed thinly and uniformly. The thickness may be about 0.2 μm, for example.

  Subsequently, the plating resist 21 and the exposure film 22 are overlapped on both surfaces of the base material 13, and exposure / development is performed to form a plating resist 21a for pattern formation in a portion other than the portion where the pattern is to be formed. (Plating resist forming process, FIGS. 1D and 1E). The plating resist 21a for pattern formation can be formed by a known appropriate method, for example, a dry film resist may be used. A portion of the plating resist 21 that is not cured by exposure is peeled off by development. The exposure film can be either a negative type or a positive type.

  Then, the conductive layer 13 is exposed at the portion where the pattern is to be formed, and subsequently, copper is deposited on the exposed portion of the conductive layer by performing electrolytic copper plating using the conductive layer 13. 14 is formed (see a pattern forming step, see FIG. 1F). Since the pattern 14 is formed by electrodeposition, as shown in FIG. 3A, the pattern 14 can be formed in a cross-sectional shape in which the side faces are vertical or substantially vertical. In addition, since the conductive layer 13 is also formed on the inner wall of the through hole 12 in the previous conductive layer forming step, electrodeposition occurs on the inner wall of the through hole 12. Therefore, both sides can be made energized without separate through-hole plating as in the prior art. This portion will later become the inner through hole 12a.

  Thereafter, with the plating resist 21a provided, a dendritic copper electrodeposition layer 15a is formed on the surface of the pattern 14 as shown in FIG. 2, and a matte plating layer 15b is further formed thereon to form a copper A rough surface film 15 is obtained (see rough surface film formation step, FIG. 1 (g)). The matte plating is performed by a known method, but can also be performed by an electrodeposition method of a matte copper coating. The dendritic copper electrodeposition layer 15a is formed by electrolytic treatment by a well-known method, and becomes a dendritic deep state. On this, a matte plating layer, that is, a plating layer with fine crystal grains is formed by increasing the deposition rate.

  Then, as shown in FIG. 2, the deep surface having a dendritic shape is covered, resulting in smooth and continuous bumpy irregularities. As a hump-like unevenness, a hump head larger than the root is also generated, and a higher anchor effect is obtained.

  After the rough surface film 15 is formed in this way (see FIG. 3B), as shown in FIG. 3C, the plating resist 21a remaining in the region other than the pattern forming portion, and this In order to remove the current-carrying layer 13 located under the plating resist 21a, peeling and entire etching are performed (removal process, see FIG. 1 (h)). For example, the peeling is performed by immersing in caustic soda, and the entire surface etching is performed by immersing in sulfuric acid. As described above, when the current-carrying layer is 0.2 μm, the entire surface etching is preferably, for example, about 0.3 μm.

  The whole surface etching removes the current-carrying layer and also slightly removes the surface of the hump-like unevenness, but the shape of the hump does not change so much.

  In addition, when the dendritic plating is not sufficiently adhered to the current-carrying layer, the portion that was not sufficiently covered even with the matte plating may be peeled off in a powder form later. This part can be removed in advance, and it will not be peeled off in the subsequent coating process of the insulating layer.

  Through these steps, the inner layer 10a of the four-layer multilayer printed wiring board 10 having the patterns 14 on both sides can be formed (see FIGS. 1 (h) and 4 (j)).

  Here, the inner layer 10a is a layer other than the layer closest to the surface among the patterns made of a plurality of layered metals in the multilayer printed wiring board 10.

  Since the outer side of the inner layer 10a thus obtained needs to be insulated from the conductive pattern made of another metal layer formed on the outer side, the insulating layer 16 is formed in close contact, and the A pattern 17 is formed thereon (see FIG. 4J). The formation of the outer layer 10b can be performed in the same manner as the formation of the inner layer 10a described above, and can also be performed by a conventional method or the like.

  First, after explaining the former example (see FIG. 4) performed in the same manner as the formation of the inner layer 10a, the latter example (see FIG. 5) will be explained.

  As shown in FIG. 4A, the prepreg 16a and the release paper 25 are laminated on both surfaces of the inner layer 10a, and hot-pressed (see FIG. 4B) (insulating layer coating step). The prepreg 16a is for forming the insulating layer 16, and the release paper 25 is for preventing the resins of the prepreg 16a from sticking to each other when hot pressing is performed. This is because the hot pressing is performed simultaneously by stacking a plurality of layers laminated as described above.

  Next, after the through-hole 18 is made in a necessary location (through-hole forming step, see FIG. 4C), the electroconductive layer 19 is subjected to electroless plating after desmearing or surface roughening as necessary. (Refer to FIG. 4D). The conductive layer 19 (electroless plating) can be formed thinly and uniformly. The thickness may be about 0.2 μm, for example.

  Subsequently, the plating resist 23 and the exposure film 24 are overlapped on both surfaces where the conductive layer 19 is exposed, and exposure / development is performed. A plating resist 23a for pattern formation is formed on a portion other than the portion where the pattern is to be formed. (Plating resist forming process, see FIGS. 4E and 4F).

  Then, the conductive layer 19 is exposed at the portion where the pattern is to be formed, and subsequently, by performing electrolytic copper plating using the conductive layer 19, copper is electrodeposited on the portion where the conductive layer 19 is exposed. 17 is formed (see a pattern forming step, see FIG. 4G). Since the pattern 14 is formed by electrodeposition, it can be formed in a cross-sectional shape with sharp side surfaces. Further, since the conductive layer 19 is also formed on the inner wall of the through hole 18 in the previous conductive layer forming step, electrodeposition occurs on the inner wall of the through hole 18. Therefore, both sides can be made energized without separate through-hole plating as in the prior art. This portion is a portion that later becomes the through hole 18a.

  Thereafter, with the plating resist 23a provided, a dendritic copper electrodeposition layer 15a is formed on the surface of the pattern 17 as shown in FIG. 2, and a matte plating layer 15b is further formed thereon. A rough surface film 15 is obtained (see rough surface film forming step, see FIG. 4H).

  After the rough surface film 15 is formed in this way, peeling and whole surface etching are performed in order to remove the plating resist 23a remaining in the portion other than the pattern forming portion and the conductive layer 19 located under the plating resist 23a. (Removal step, see FIG. 4I).

  Finally, a solder resist 20 is formed by a known method (solder resist coating, semi-cure, exposure, development) (solder resist forming step, see FIG. 4 (j)). Prior to the formation of the solder resist 20, it is not necessary to roughen the surface of the pattern 17.

  Thereafter, necessary processing such as guide hole processing and end face shaping is performed.

  In the latter example, as shown in FIG. 5A, the prepreg 16a and the copper foil 17a are laminated on both surfaces of the inner layer 10a. Then, they are integrated by performing a hot press (insulating layer coating step, see FIGS. 5A and 5B). Thereafter, after the through hole 18 is opened (through hole forming step, see FIG. 5C), necessary work such as desmear is appropriately performed, and through hole plating 18b is performed so that both surfaces can be energized (through). Hole plating process, see FIG. 5 (d)). This portion will later become the through hole 18a (see FIGS. 5H to 5J).

  Subsequently, an etching resist 26 and an exposure film 27 are overlapped on both surfaces where the copper foil 17a is exposed (see FIG. 5E), and exposure and development are performed. 26a (see FIG. 5F) is formed (etching resist forming step).

  Thereafter, etching is performed to remove the portion of the copper foil 17a not covered with the etching resist 26a (see the etching process, FIG. 5G).

  Next, the etching resist 26a is peeled off (see the peeling step, FIG. 5H). Peeling is performed by dipping in caustic soda.

  Thereafter, both surfaces are roughened by buffing or the like (roughening step, see FIG. 5 (i)), and finally, a solder resist treatment is performed to form a solder resist 20 (solder resist forming step, FIG. 5 (j)).

  In the inner layer 10a of the multilayer printed wiring board 10 manufactured through the above processes, as shown in FIG. 3C, the pattern 14 has a shape in which the side surfaces are vertically or substantially vertically cut. And the rough surface film 15 which has a knurled unevenness | corrugation is formed in the upper surface. For this reason, as shown in FIG. 3D, when the insulating layer 16 is coated later, the resin of the prepreg enters the gap of the pattern 14 and the anchor effect with the rough surface coating 15 of the pattern 14. Is obtained. In addition, since the pattern 14 is electrodeposited in order from below, it is formed in a layer shape, so that an anchor effect can be obtained even with the resin (insulating layer 16) that has entered between the patterns 14.

  For this reason, the adhesion strength between the pattern 14 of the inner layer 10a and the insulating layer 16 superimposed on the pattern 14 can be improved. As a result, in the multilayer printed wiring board 10 manufactured using such an inner layer 10a, the occurrence of delamination between the pattern 14 of the inner layer 10a and the insulating layer 16 is suppressed, and high solder heat resistance and thermal shock are achieved. Sex can be obtained.

  When an evaluation test (3000 cycle thermal shock test (−80 to 120 ° C.)) required as an in-vehicle component was performed on the multilayer printed wiring board 10 manufactured by the method shown in FIGS. 1 and 4, delamination No resist peeling was confirmed.

  Further, it is possible to eliminate the need for through-hole plating and copper foil etching, and it is possible to reduce the manufacturing cost.

  Further, since the conventional blackening process is not required, it is not necessary to remove the coating from the outer layer 10b where copper is exposed such as lands and pads, thereby improving workability.

  As shown in FIG. 4, when the outer layer 10b is manufactured through the same steps as the inner layer 10a, it is possible to completely eliminate the need for through-hole plating or copper foil etching during the manufacturing process, thereby reducing the manufacturing cost, etc. Further effects can be obtained in this respect. Further, due to the synergistic effect of the shape of the pattern 17 of the outer layer 10b and the rough surface coating 15 on the upper surface, the adhesion with the solder resist 20 is also improved, and product defects can be eliminated.

In correspondence between the configuration of the present invention and the configuration of the above-described one form,
The dendritic electrodeposition layer of the present invention corresponds to the above-mentioned dendritic copper electrodeposition layer 15a,
The insulating plate corresponds to the prepreg 16a,
The present invention is not limited to the above configuration, and other forms can be adopted.
For example, if a substrate having a plurality of pattern layers is used as a substrate, a multilayer printed wiring board having more than the above four layers can be obtained.

Explanatory drawing which shows the principal part of the manufacturing process of the inner layer of a multilayer printed wiring board. The schematic diagram which shows the cross-section of the rough surface film formed in the surface of a pattern. The schematic diagram which shows formation of the rough surface film of the pattern of an inner layer, and its action state. Explanatory drawing which shows the process of forming the outer layer of a multilayer printed wiring board. Explanatory drawing which shows the process of forming the outer layer of a multilayer printed wiring board. Explanatory drawing which shows the manufacturing process of the conventional multilayer printed wiring board. Explanatory drawing which shows the conventional pattern part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Multilayer printed wiring board 10a ... Inner layer 10b ... Outer layer 11 ... Base material 13 ... Current supply layer 14 ... Pattern 15 ... Rough surface coating 15a ... Dendritic copper electrodeposition layer 15b ... Matte plating layer 16 ... Insulating layer 16a ... Prepreg 17 ... Pattern 19 ... Conducting layer 20 ... Solder resist 21a, 23a ... Plating resist

Claims (6)

A method for producing an inner layer of a multilayer printed wiring board having three or more pattern layers in the thickness direction,
An energization layer forming step of forming an energization layer made of a metal film on the surface of the base material made of an insulating material at least on the surface;
A plating resist forming step of forming a plating resist on a portion other than the pattern forming portion on the conductive layer;
A pattern forming step of forming a pattern by electrolytic plating using the above-described energization layer on a pattern forming portion other than a plating resist,
A rough surface film forming step of forming a rough surface film by forming a dendritic electrodeposition layer and a matte plating layer sequentially performed on the surface of the pattern formed by the pattern forming step;
The manufacturing method of the inner layer of the multilayer printed wiring board which has the removal process which removes the said electrically-conductive layer in a plating resist and the plating resist formation part. A method for producing a multilayer printed wiring board having three or more pattern layers in the thickness direction,
An energization layer forming step of forming an energization layer made of a metal film on the surface of the base material made of an insulating material at least on the surface;
A plating resist forming step of forming a plating resist on a portion other than the pattern forming portion on the conductive layer;
A pattern forming step of forming a pattern by electrolytic plating using the above-described energization layer on a pattern forming portion other than a plating resist,
A rough surface film forming step of forming a rough surface film by forming a dendritic electrodeposition layer and a matte plating layer sequentially performed on the surface of the pattern formed by the pattern forming step;
The manufacturing method of the multilayer printed wiring board which has the removal process which removes the said electrically-conductive layer in the said plating resist and a plating resist formation part. After the removing step, an insulating layer covering step of laminating an insulating plate made of an insulating material and hot pressing,
An outer layer forming energization layer forming step of forming an energization layer made of a metal film on the surface of the insulating layer coated in the insulating layer coating step;
A plating resist forming step for forming an outer layer for forming a plating resist on a portion other than the pattern forming portion on the conductive layer;
A pattern forming step for an outer layer that forms a pattern by electrolytic plating using the above-described energization layer on a pattern forming portion other than a plating resist,
On the surface of the pattern formed by the outer layer pattern forming step, a rough surface film forming step for outer layer that forms a rough surface film by forming a dendritic electrodeposition layer and a matte plating layer sequentially performed,
The plating resist, and the outer layer forming removal step for removing the energization layer in the plating resist forming portion,
The manufacturing method of the multilayer printed wiring board of Claim 2 which has the soldering resist formation process which forms a soldering resist. An inner layer of a multilayer printed wiring board, wherein the inner surface of the multilayer printed wiring board is provided with bumpy irregularities on the surface of the pattern. The inner layer of the multilayer printed wiring board according to claim 4, wherein a side surface of the pattern is formed in a substantially vertical shape. A multilayer printed wiring board comprising an inner layer of the multilayer printed wiring board according to claim 4 or 5.

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