JP2010028107A - Printed circuit board, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-density printed circuit board which uses an inexpensive inter-layer insulating base material and has high adhesion secured between electroless plating and the inter-layer insulating base material and allows microwire formation using a semi-additive method, in order to make a mobile device small in size, thin in thickness, light in weight, high in definition, multiple in function or the like. <P>SOLUTION: With respect to the printed circuit board, a resin layer which has irregularities having a maximum height roughness Rz of 1 to 7 μm and has a composition different from that of the inter-layer insulating base material is formed on at least one surface of the inter-layer insulating base material, and a conductor layer is formed on the resin layer by electroless plating. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a high-density printed wiring board widely used in various electronic devices such as personal computers, mobile communication telephones, and video cameras.

  In recent years, electronic devices are strongly demanded to be small, thin, lightweight, high definition, multi-functional, etc. Along with this, printed wiring boards on which various components are mounted are desired to be further miniaturized, multilayered, and miniaturized. Yes. As a method for forming a fine wiring, a thin conductive layer (hereinafter referred to as a seed layer) is formed on an insulating resin by electroless plating, an image is formed with a photoresist, a plated wiring is formed by electrolytic copper plating, and then a resist is formed. A semi-additive method is known in which fine wiring is formed by peeling and etching the seed layer.

  Hereinafter, a printed wiring board using a conventional semi-additive method will be described with reference to FIG. FIG. 5 is a cross-sectional view for explaining a method of manufacturing a printed wiring board using a conventional semi-additive method.

  In FIG. 5, an interlayer insulation made of, for example, a glass woven epoxy material is formed on both surfaces of the core substrate 1 in which copper wiring is formed on both surfaces as shown in FIG. The base material 3 and the copper foil 2 are prepared (FIG. 5B), and bonded together using a hot press (FIG. 5C). Next, the copper foil 2 is dissolved by etching (FIG. 5D), and then the blind via hole 4 is formed by a laser (FIG. 5E). Next, the resin residue by the laser is removed by a desmear process, and then a seed layer 5 is formed by electroless copper plating of 0.1 to 1 μm (FIG. 5F). Further, after laminating a dry film 6 and forming an image with a photoresist in an area where a conductor pattern is not formed through exposure and development (FIG. 5G), copper wiring formation and blind via plating are performed by electrolytic copper plating. Conductive pattern 7 is formed (FIG. 5H). Thereafter, the dry film 6 is peeled off (FIG. 5 (i)), and the seed layer 5 is etched to obtain a printed wiring board (FIG. 5 (j)).

  For example, Patent Documents 1 to 4 are known as prior art document information related to the application of the present invention.

JP 2001-192844 A JP 2007-273615 A JP 2007-273615 A JP 11-298121 A

  However, in the conventional method, there is a problem that the adhesion between the interlayer insulating base material 3 and the seed layer 5 is weak, the conductor pattern 7 is peeled off during the manufacturing process, and the holding strength of the components to be mounted is weak. This is because it is difficult to form fine irregularities on the interlayer insulating base material 3 serving as a base for electroless plating, and a sufficient anchor effect between the electroless plating and the base material cannot be obtained. there were.

  In order to solve the above problems, a semi-additive method-dedicated interlayer insulating base material that can uniformly form fine irregularities has been developed. However, since the base material is expensive, it is only used for some semiconductor package substrates. Therefore, it was difficult to apply to a general printed wiring board.

  In addition, in order to ensure adhesion between the substrate and the conductor pattern, there is a method of using a hot-pressed ultrathin copper foil (1.5 to 5 μm) instead of electroless copper plating as the seed layer. However, since it is thicker than electroless plating, etching to remove the seed layer is difficult, and there is a problem that it is not suitable for forming fine wiring.

  The present invention has been made in view of the above problems, uses an inexpensive interlayer insulating base material, ensures high adhesion between the electroless plating and the interlayer insulating base material, and uses a semi-additive method for fine wiring An object is to provide a printed wiring board that can be formed.

  In order to achieve the above object, the present invention provides a first resin layer provided with a first unevenness having a maximum height roughness Rz of 1 μm or more and 7 μm or less on at least one surface, and on the first unevenness. A second resin layer provided on the second resin layer, a second unevenness having a smaller Rz than the first unevenness, and a conductor layer provided on the second unevenness; The printed wiring board having

  With such a configuration, the first resin layer and the second resin layer are formed by using the first unevenness with the maximum height roughness Rz = 1 to 7 μm provided on the surface of the first resin layer as an anchor. Increase adhesion between the two.

  Further, by providing the second resin layer with the second unevenness having a maximum height roughness Rz smaller than the maximum height roughness Rz of the first unevenness, the conductor layer and the second resin layer Strong adhesion can be obtained.

  As described above, according to the present invention, it is possible to form a fine wiring using a semi-additive method using an inexpensive interlayer insulating base material, thereby realizing a small size, a thin shape, a light weight, a high definition, a multi-functionality, and the like. Therefore, it is possible to provide a high-density printed wiring board necessary for this purpose at a low cost.

Sectional drawing which shows the printed wiring board in embodiment of this invention The expanded sectional view which explains typically the unevenness | corrugation in the interface of the 1st resin layer, a conductor pattern, and the 2nd resin layer provided in the meantime Sectional drawing which shows an example of the manufacturing process of the high-density printed wiring board of embodiment of this invention Sectional drawing which shows an example of the manufacturing process of the high-density printed wiring board of embodiment of this invention Sectional drawing explaining the manufacturing method of the printed wiring board using the conventional semi-additive method

(Embodiment)
Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1A is a cross-sectional view of a high-density printed wiring board according to an embodiment of the present invention, and FIG. 1B is an enlarged cross-sectional view.

  In FIG. 1, 11 is a first resin layer, 12 is a first unevenness, 13 is a second resin layer, 14 is a second unevenness, 15 is a seed layer, 16 is a conductor pattern, 17 is a conductor layer, 18 Is a core substrate, and 19 is a printed wiring board.

  As shown in FIG. 1A, in the high-density printed wiring board according to the embodiment of the present invention, the first resin layer 11, the second resin layer 13, the seed layer 15, etc. are provided on the surface of the core substrate 18. Thus, a pattern composed of the conductor pattern 16 is formed on the outermost layer.

  FIG. 1B is an enlarged cross-sectional view showing a state where the first resin layer 11 and the conductor pattern 16 are in close contact with each other through the second resin layer 13 and the seed layer 15.

  As shown in FIGS. 1A and 1B, the first unevenness 12 is provided on at least one surface of the first resin layer 11. A second resin layer 13 is provided on the first irregularities 12 provided on the surface of the first resin layer 11. A conductor layer 17 including a seed layer 15 and a conductor pattern 16 is provided on the second unevenness 14 provided on the surface of the second resin layer 13.

  1A and 1B, the conductor layer 17 is formed of the seed layer 15 and the conductor pattern 16, but it is not necessary to limit to this configuration.

  In addition, as shown in FIG. 1B, the second unevenness 14 is finer than the first unevenness 12, that is, the maximum height Ra is reduced or the unevenness pitch is reduced. This is to increase the strength, and will be described later with reference to FIG. Here, the maximum height roughness Rz of the first unevenness 12 is preferably 1 μm or more and 7 μm or less. When Rz of the first unevenness 12 is less than 1 μm, the anchor effect at the interface between the first resin layer 11 and the second resin layer 13 may be affected. Moreover, when Rz of the 1st unevenness | corrugation 12 exceeds 7 micrometers, the thickness of the 2nd resin layer 13 may be affected. On the other hand, if Rz exceeds 7 μm, the adhesive force (or anchor effect) between the second resin layer 13 and the conductor layer 17 may be affected.

  In the printed wiring board 19 of the present invention, if necessary, a solder resist may be formed on the outermost layer, and nickel, gold plating or the like may be applied on the outermost layer wiring.

  The first resin layer 11 serving as an interlayer insulating base material of the present invention is, for example, a general prepreg in which a glass fiber woven fabric is impregnated with an epoxy resin, but organic fiber, BT resin, or the like may be used. .

  In the present invention, in order to form the first unevenness 12 with Rz = 1 μm or more and 7 μm or less at the interface between the second resin layer 13 and the first resin layer 11, the first resin serving as an interlayer insulating base material The layer 11 is laminated on the surface on which the second resin layer 13 is formed using a copper foil having Rz roughened to 1 μm or more and 7 μm or less in advance. It is useful to previously form a thin second resin layer 13 having a composition different from that of the first resin layer 11 serving as an interlayer insulating base material on the roughened surface of the roughened copper foil. .

  The second resin layer 13 has a function of adhering the first resin layer 11 serving as an interlayer insulating base and the conductor pattern 16 (or the seed layer 15 provided on the surface of the conductor pattern 16), The resin alone or an inorganic filler made of silica, alumina, aluminum hydroxide, barium titanate or the like may be included.

  In addition, as for the thickness of the 2nd resin layer 13, 0.5 micrometer or more and 4.0 micrometers or less are desirable. When the thickness exceeds 4.0 μm, the physical properties of the second resin layer 13 affect the interlayer insulating base material and the like, and the physical properties as the insulating material of the substrate are deteriorated, or the thinning of the multilayer substrate is hindered. There is a case. If the thickness is less than 0.5 μm, sufficient adhesion to the electroless plating by the second unevenness 14 formed on the surface of the second resin layer 13 and finer than the first unevenness 12 may not be obtained. is there.

  Next, referring to FIG. 2, the first unevenness 12a, 12b, 12c provided on the surface of the first resin layer 11 and the conductor layer 17 side of the second resin layer 13 (or of the first resin layer 11). The relationship between the second irregularities 14a, 14b, and 14c provided on the surface opposite to the surface will be described.

  FIG. 2 is an enlarged cross-sectional view schematically illustrating irregularities at the interface of the first resin layer 11, the conductor pattern 16, and the second resin layer 13 provided therebetween.

  In FIG. 2, at least one surface of the first resin layer 11 is formed with first irregularities 12a, 12b, and 12c having a maximum height roughness Rz of 1 μm or more and 7 μm or less. The first unevenness 12a schematically indicates the height (or Rz) of the first unevenness 12. Further, 12b indicated by an arrow is a typical pitch (or distance) between the valleys of the first unevenness 12, and 12c indicated by an arrow is a typical pitch (or distance) between the peaks of the first unevenness 12, respectively. It shows.

  A second resin layer 13 is provided on the upper side of the first unevenness 12. On the upper side of the second resin layer 13, second irregularities 14 a, 14 b, and 14 c that are finer than the first irregularities 12 are formed. A conductor layer 17 is formed on the upper side of the second irregularities 14a, 14b, and 14c. The second unevenness 14a schematically indicates the height (or Rz) of the second unevenness 14. Further, 14b indicated by an arrow schematically represents the pitch (or distance) between the peaks and peaks of the second irregularities 14, and 14c indicated by an arrow schematically represents the pitch (or distance) between the valleys and valleys of the second irregularities 14. It shows.

  As shown in FIG. 2, the first unevenness (one or more of 12a, 12b, 12c) is made larger than the second unevenness (any one or more of 14a, 14b, 14c). Increase adhesion.

  Note that the height of the second unevenness 14 (for example, Rz, 14a) is shown based on the height of the first unevenness 12 in FIG. 2 (for example, schematically shown in FIG. 2 as the maximum height roughness Rz, 12a). 2 is schematically shown), that is, it is desirable to make the second unevenness 14a, 14b, 14c finer than the first unevenness 12a, 12b, 12c. In this way, mutual adhesion is increased. When it is difficult to measure the surface roughness at the interface, the sample cross-section is observed with a microscope, SEM (scanning electron microscope), etc., and the first irregularities 12a, 12b, 12c are observed with the interface shape (for example, cross-sectional photographs). The size and shape of the second unevenness 14a, 14b, 14c may be compared. Further, surface roughness such as Rz, pitch, distance, and the like may be calculated based on data obtained from the cross-sectional photograph. The second irregularities 14a, 14b, and 14c provided on the surface of the second resin layer 13 may be evaluated at the interface between the second resin 13 and the seed layer 15, but it is difficult to detect the seed layer 15. In this case, the evaluation may be performed at the interface between the second resin layer 13 and the conductor pattern 16 (or the conductor layer 17 including the seed layer 15).

  In FIG. 2, the first unevenness 12 and the second unevenness 14 are described substantially parallel to each other, but it is not necessary to limit to this. For example, as described in FIGS. 1A and 1B, a shape in which a plurality of concave and convex portions of the second concave and convex portion 14 are included in one concave portion of the first concave and convex portion 12 may be used. Further, as shown in FIGS. 1A and 1B, the first unevenness 12 may be curved (or three-dimensional), and a plurality of unevenness including the second unevenness 14 may be inserted therein.

  Next, an example of the manufacturing process of the high-density printed wiring board according to the present embodiment will be described in detail with reference to FIGS.

  3 and 4 are sectional views showing an example of a manufacturing process of the high-density printed wiring board according to the embodiment of the present invention. 3 and 4, 20 is a wiring pattern, 21 is through-hole plating, 22 is a prepreg, 23 is a roughened copper foil, 24 is a blind via, 25 is a dry film, 26 is an electrolytic plating layer (an electroplating layer and Sometimes called).

  First, in order to produce the core substrate 18 (for example, an insulating material having a thickness of 0.6 mm and a copper foil having a thickness of 18 μm), a hole having a diameter of, for example, 0.3 mmΦ is formed with an NC drill, and through-hole plating 21 is performed. A double-sided wiring board on which the wiring pattern 20 is formed using the active method is prepared (FIG. 3A). Next, in order to produce a build-up layer, a prepreg 22 (for example, 60 μm thickness) as an interlayer insulating base material which is a general glass fiber epoxy base material and first unevenness 12 in advance are formed on both surfaces of the core substrate 18. A roughened surface for forming (Rz = 1 to 7 μm) and a roughened copper foil 23 (for example, 12 μm thickness) in which the second resin layer 13 is formed on this roughened surface are prepared (see FIG. 3 (B)), for example, the pressure was kept at 5 MPa and the temperature was kept at 200 ° C. for 2 hours, and hot pressing was performed (FIG. 3C). Thus, the prepreg 22 is cured and insolubilized to form the first resin layer 11, and then cooled to room temperature and treated with an iron chloride etchant at a temperature of 40 ° C. for 1 minute, for example. 23) is dissolved, and first irregularities 12 with Rz = 1 to 7 μm are formed on the first resin layer 11. Thus, a substrate having the second resin layer 13 transferred onto the first unevenness 12 is obtained (FIG. 3D).

  Next, after forming the blind via 24 at a predetermined position with a carbon dioxide laser, swelling (for example, 60 ° C., 5 minutes), roughening (for example, 80 ° C., 10 minutes), neutralization (for example, 45 ° C., 5 minutes) Perform desmear processing.

  By this desmear process, the surface of the second resin layer 13 formed on the surface of the first unevenness 12 is finely etched. In this way, for example, by performing a desmear process, the surface of the second resin layer 13 is etched, and the second unevenness 14 that is finer than the first unevenness 12 is formed as shown in FIG. It is formed on the surface of the resin layer 13 (FIG. 3E).

  Next, electroless copper plating (for example, 40 ° C., 20 minutes) is performed to obtain a thin copper plating seed layer 15 having a thickness of 0.5 μm (FIG. 4A). Next, a dry film 25 (for example, 25 μm thickness) is laminated as a plating resist using a thermal laminator, for example, at a temperature of 110 ° C., a pressure of 0.5 MPa, and a conveyance speed of 2 m / min, and then a desired fineness of 40 μm pitch. After the pattern image is exposed to ultraviolet light, it is developed with a 1% sodium carbonate solution at 30 ° C. for 20 seconds to form a desired image in a region where the electroplating layer to be the conductor pattern 16 is not formed (FIG. 4B). ).

Next, for example, after plating by electrolytic copper plating for via filling at a current density of 1 A / dm ² for 90 minutes to form an electrolytic plating layer 26 by plating on the wiring and via filling plating (FIG. 4C), for example, The dry film 25 was peeled off with a 3% sodium hydroxide solution (for example, 45 ° C., 50 seconds) (FIG. 4D).

  Next, in order to remove the exposed seed layer 15, the conductive pattern 16 is formed by treating with a quick etching solution, for example, at 30 ° C. for 2 minutes to obtain a fine printed wiring board 19 by the semi-additive method of the present invention. (FIG. 4E).

  In the present embodiment, the configuration and the manufacturing method of the printed wiring board 19 having the core substrate 18 have been described. However, a configuration without the core substrate 18 may be used.

  In order to evaluate the adhesion between the copper wiring and the base material on the printed wiring board 19 of the present invention and the conventional board, a copper pattern having a width of 5 mm was measured by a 90-degree peel strength test.

  In the conventional substrate, the adhesion strength was 0.4 kN / m, but in the printed wiring board 19 according to the present invention, an adhesion strength of 0.9 kN / m, which is almost twice that of the conventional one, could be obtained. This is because the seed layer 15 formed by electroless copper plating is deposited on the second resin layer 13 on which the second unevenness 14 formed by the desmear process is formed. An anchor effect will increase and it has the effect that it leads to the improvement of adhesiveness.

  As described above, the first resin layer 11 provided with the first unevenness 12 having the maximum height roughness Rz of 1 μm or more and 7 μm or less on at least one surface, and the first resin layer 11 provided on the first unevenness 12, Two resin layers 13, a second unevenness 14 having an Rz smaller than the first unevenness 12, and a conductor layer provided on the second unevenness 14. 17, the adhesion between the second resin layer 13 and the conductor layer 17 can be increased.

  Further, a part or more of the conductor layer 17 is formed by any one or more of electroless plating, sputtering, and vapor deposition, so that the details of the second unevenness 14 provided on the surface of the second resin layer 13 are as follows. A part or more of the conductor layer 17 can be provided, and the anchor effect of the conductor layer 17 with respect to the second resin layer 13 can be enhanced.

  Note that it is desirable that one or more of the first resin layer 11 and the second resin layer 13 be different from each other in the resin, filler, resin or filler component ratio (which differs by 1 wt% or more). This is because a composition ratio of less than 1 wt% is easily affected by variations (for example, segregation, dispersion variations, etc.) of the constituent members in the first resin layer 11 and the second resin layer 13. When the resin, filler, resin, or filler itself is changed between the first resin layer 11 and the second resin layer 13, it is not necessary to change the component ratio. Thus, by making the second unevenness 14 provided in the second resin layer 13 finer than the first unevenness provided in the first resin layer 11, the second resin layer 13 and Adhesion with the conductor layer 17 can be increased.

  The thickness of the second resin layer 13 is in the range of 0.5 μm or more and 4.0 μm or less, so that the first unevenness 12 provided in the first resin layer 11 and the second resin layer 13 Interference with the provided second unevenness 14 can be reduced and the printed wiring board can be made thinner.

  A part or more of the conductor layer 17 is formed by electroless plating, and the electroless plating is made of at least one or a plurality of metals of copper, nickel, and palladium. A part or more of the seed layer 15 or the conductor layer 17 can be provided up to the details of the second unevenness 14 provided on the surface of the resin layer 13, and the anchor effect of the conductor layer 17 on the second resin layer 13 is enhanced. be able to.

  Further, the second unevenness 14 provided at the interface between the second resin layer 13 and the conductor layer 17 is determined by the pitch of the first unevenness 12 provided at the interface between the first resin layer 11 and the second resin layer 13. By reducing the pitch, the second unevenness 14 can be reliably miniaturized rather than the first unevenness 12, and the adhesion between the second resin layer 13 and the conductor layer 17 can be increased.

  1st resin layer 11, copper foil (for example, roughened copper foil 23) which has unevenness | corrugation of maximum height roughness Rz = 1 micrometer or more and 7 micrometers or less, and the 2nd resin layer provided in the surface of this copper foil 13, a step of laminating the first resin layer 11 and the copper foil by hot pressing, a step of dissolving the copper foil by etching, and the second resin layer 13. The method of forming the printed wiring board 19 including at least the step of forming the second unevenness 14 on the surface and the step of forming the conductor layer 17 on the surface of the second resin layer 13, the embodiment, etc. The printed wiring board 19 described in the above can be manufactured.

  The step of forming the fine second irregularities 14 on the surface of the second resin layer 13 includes at least one of desmear treatment, plasma treatment, acid treatment, and alkali treatment. The second unevenness 14 provided on the surface of the second resin layer 13 can be more surely made finer than the first unevenness 12 provided on the surface of the first resin layer 11, and the second resin layer 13 and the conductor layer 17 can be reduced. It is possible to increase the adhesive strength with.

  The printed wiring board according to the present invention enables the formation of fine wiring using a semi-additive method using an inexpensive interlayer insulating base material, thus realizing small size, thinness, light weight, high definition, multi-functionality, etc. Therefore, it is possible to provide a high-density printed wiring board necessary for this purpose at a low cost.

DESCRIPTION OF SYMBOLS 11 1st resin layer 12 1st unevenness | corrugation 13 2nd resin layer 14 2nd unevenness | corrugation 15 Seed layer 16 Conductive pattern 17 Conductive layer 18 Core substrate 19 Printed wiring board 20 Wiring pattern 21 Through-hole plating 22 Prepreg 23 Rough surface Copper foil 24 Blind via 25 Dry film 26 Electroplating layer

Claims (8)

A first resin layer having at least one surface provided with first irregularities having a maximum height roughness Rz of 1 μm or more and 7 μm or less;
A second resin layer provided on the first unevenness;
A second unevenness provided on the second resin layer and having a smaller Rz than the first unevenness;
A conductor layer provided on the second unevenness;
A printed wiring board. The printed wiring board according to claim 1, wherein at least a part of the conductor layer is formed by any one or more of electroless plating, sputtering, and vapor deposition. 2. The printed wiring board according to claim 1, wherein the first resin layer and the second resin layer differ in at least one of resin, filler, resin, or filler by at least 1 wt%. 2. The printed wiring board according to claim 1, wherein the thickness of the second resin layer is 0.5 μm or more and 4.0 μm or less. The printed wiring board according to claim 2, wherein the electroless plating is made of at least one of copper, nickel, and palladium, or a plurality of metals. The print according to claim 1, wherein the pitch of the second unevenness provided at the interface between the second resin and the conductor layer is smaller than the pitch of the first unevenness provided at the interface between the first resin and the second resin. Wiring board. A first insulating layer;
A step of providing a second resin layer on the concavo-convex surface of a copper foil having a concavo-convex surface having a maximum height roughness Rz of 1 μm or more and 7 μm or less;
Laminating the first resin layer and the second resin surface of the copper foil by hot pressing;
Removing the copper foil by etching;
Forming second irregularities on the second resin surface;
Forming a conductor layer on the surface of the second resin layer;
A method of manufacturing a printed wiring board comprising at least The process for forming fine irregularities on the surface of the second resin includes at least one or more of desmear treatment, plasma treatment, acid treatment, and alkali treatment. Method.

Images