JP5049803B2 - Multilayer printed wiring board manufacturing method, multilayer printed wiring board - Google Patents
Multilayer printed wiring board manufacturing method, multilayer printed wiring board Download PDFInfo
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- JP5049803B2 JP5049803B2 JP2008013099A JP2008013099A JP5049803B2 JP 5049803 B2 JP5049803 B2 JP 5049803B2 JP 2008013099 A JP2008013099 A JP 2008013099A JP 2008013099 A JP2008013099 A JP 2008013099A JP 5049803 B2 JP5049803 B2 JP 5049803B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 48
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 226
- 229920005989 resin Polymers 0.000 claims description 191
- 239000011347 resin Substances 0.000 claims description 191
- 229910052802 copper Inorganic materials 0.000 claims description 126
- 239000010949 copper Substances 0.000 claims description 126
- 238000007747 plating Methods 0.000 claims description 107
- 239000000758 substrate Substances 0.000 claims description 105
- 239000011889 copper foil Substances 0.000 claims description 100
- 238000000034 method Methods 0.000 claims description 64
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 48
- 239000004020 conductor Substances 0.000 claims description 37
- 238000005530 etching Methods 0.000 claims description 35
- 239000007788 liquid Substances 0.000 claims description 23
- 238000000059 patterning Methods 0.000 claims description 23
- 239000003054 catalyst Substances 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 18
- JYLNVJYYQQXNEK-UHFFFAOYSA-N 3-amino-2-(4-chlorophenyl)-1-propanesulfonic acid Chemical compound OS(=O)(=O)CC(CN)C1=CC=C(Cl)C=C1 JYLNVJYYQQXNEK-UHFFFAOYSA-N 0.000 claims description 16
- 238000010438 heat treatment Methods 0.000 claims description 15
- 239000003513 alkali Substances 0.000 claims description 12
- 230000004580 weight loss Effects 0.000 claims description 10
- 239000003365 glass fiber Substances 0.000 claims description 6
- 239000011256 inorganic filler Substances 0.000 claims description 5
- 229910003475 inorganic filler Inorganic materials 0.000 claims description 5
- 238000003825 pressing Methods 0.000 claims description 5
- 238000007788 roughening Methods 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims 1
- 239000003822 epoxy resin Substances 0.000 description 31
- 229920000647 polyepoxide Polymers 0.000 description 31
- 239000011521 glass Substances 0.000 description 30
- 238000012545 processing Methods 0.000 description 15
- 229910000679 solder Inorganic materials 0.000 description 14
- 230000000052 comparative effect Effects 0.000 description 13
- 238000009713 electroplating Methods 0.000 description 8
- 238000012423 maintenance Methods 0.000 description 7
- 238000012360 testing method Methods 0.000 description 7
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000013585 weight reducing agent Substances 0.000 description 6
- 238000001816 cooling Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- ZMLDXWLZKKZVSS-UHFFFAOYSA-N palladium tin Chemical compound [Pd].[Sn] ZMLDXWLZKKZVSS-UHFFFAOYSA-N 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000001569 carbon dioxide Substances 0.000 description 3
- 229910002092 carbon dioxide Inorganic materials 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- 230000008961 swelling Effects 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000012286 potassium permanganate Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011342 resin composition Substances 0.000 description 1
- 208000024891 symptom Diseases 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
本発明は、配線パターンである銅配線の接着力、部品実装時のはんだ耐熱性、微細配線形成性に優れる多層プリントン配線板の製造方法、多層プリント配線板に関する。 The present invention relates to a multilayer printed circuit board manufacturing method and a multilayer printed wiring board excellent in adhesive strength of copper wiring as a wiring pattern, solder heat resistance during component mounting, and fine wiring formability.
以下、代表的な多層プリント配線板の製造方法を述べる。
ガラス繊維等で強化されたエポキシ樹脂系のプリプレグシートの表面に厚さが９μｍから３５μｍの範囲の電解銅箔を重ね合わせて加圧加熱し銅張積層板を製造する。この銅張り積層板の所望の個所にドリルを用いて貫通孔をあける。次に無電解銅めっきを約０．３μｍ施し、次いで電気銅めっきを約１５〜２０μｍ施す。電気銅めっき後の銅張積層板に所望の銅パターンのエッチングレジストを形成し、銅エッチング液と接触させてエッチングレジストが形成されていない個所の銅を除去することによって両面配線板を作製する。この両面配線板の外側にプリプレグと電解銅箔を重ね合わせて加圧加熱して表面が銅箔で被覆された多層基板を作製する。
Hereinafter, a representative method for producing a multilayer printed wiring board will be described.
An electrolytic copper foil having a thickness in the range of 9 μm to 35 μm is superposed on the surface of an epoxy resin prepreg sheet reinforced with glass fiber or the like, and heated under pressure to produce a copper clad laminate. A through-hole is drilled in a desired portion of the copper-clad laminate using a drill. Next, electroless copper plating is applied at about 0.3 μm, and then electrolytic copper plating is applied at about 15-20 μm. An etching resist having a desired copper pattern is formed on the copper-clad laminate after the electrolytic copper plating, and a double-sided wiring board is produced by contacting with a copper etching solution to remove the copper where the etching resist is not formed. A prepreg and an electrolytic copper foil are superimposed on the outside of the double-sided wiring board and heated under pressure to produce a multilayer substrate whose surface is coated with the copper foil.
このようにして作製された多層基板では前記の両面配線板が内層コア基板になっている。この多層基板の所望の個所に炭酸ガスレーザ等で非貫通孔をあける。この非貫通孔の底部は内層コア基板の表層の銅パターン表面になっている。一般にレーザ加工した孔の底部には樹脂残渣があり、めっきによる電気的な接続の障害になる。そこで過マンガン酸カリウム等によるデスミア処理によって樹脂残渣が溶解除去される。次に無電解銅めっきを約０．３μｍ施し、次いで電気銅めっきを約１５〜２０μｍ施す。
次いで、電気銅めっき後の多層基板の銅表面に所望のパターンのエッチングレジストを形成し、銅エッチング液と接触させてエッチングレジストが形成されていない個所の銅を除去することによって多層配線板が製造される。
更に層数の多い多層板を作製する場合には前記の多層化の工程が繰り返される。
上記の多層プリント配線板の製造に使用される電解銅箔は、プリプレグ樹脂との接着力確保のために、その表面がミクロンからサブミクロンサイズの凹凸が形成された粗面とされたものが使用される。
In the multilayer substrate thus manufactured, the double-sided wiring board is an inner core substrate. A non-through hole is formed in a desired portion of the multilayer substrate by a carbon dioxide laser or the like. The bottom of the non-through hole is the surface of the copper pattern on the surface of the inner core substrate. In general, there is a resin residue at the bottom of the laser processed hole, which is an obstacle to electrical connection by plating. Therefore, the resin residue is dissolved and removed by desmear treatment with potassium permanganate or the like. Next, electroless copper plating is applied at about 0.3 μm, and then electrolytic copper plating is applied at about 15-20 μm.
Next, an etching resist having a desired pattern is formed on the copper surface of the multilayer substrate after electrolytic copper plating, and a multilayer wiring board is manufactured by removing the copper where the etching resist is not formed by contacting with a copper etching solution. Is done.
Further, in the case of producing a multilayer board having a large number of layers, the above-mentioned multilayering process is repeated.
The electrolytic copper foil used in the production of the above multilayer printed wiring board is used with a rough surface with irregularities of micron to submicron size formed to ensure adhesion with prepreg resin. Is done.
ところで、電子機器の小型化、軽量化のために多層プリント配線板の配線微細化の要求が強まっている。配線の微細化はエッチングする銅層の厚さが薄くなるほど有利である。
上記の一般的な多層プリント配線板の主面の銅層は電解銅箔とめっき銅の２層構造になっている。しかしながら、貫通孔内面や非貫通孔ではめっき銅層のみである。貫通孔や非貫通孔のめっき銅層の電気的な接続信頼性の確保の点からめっき銅層の厚さを減らすことは困難である。
そこでプリプレグ樹脂に電解銅箔を加圧加熱した後に電解銅箔を全面エッチングする方法が提案されている（例えば特許文献１、２）。この方法では、プリプレグ樹脂が硬化した表面には銅箔の粗面形状が転写されるため、エッチングにより電解銅箔が除去されると、銅箔の粗面形状が転写された樹脂層（プリプレグ樹脂が硬化したもの）の表面（粗面）が露出される。この粗面に無電解銅めっきおよび電気銅めっきを行えば銅めっき層の接着力が確保されるだけでなく、銅層の厚さを薄くできる。この結果、微細な配線形成が有利になる。
The copper layer on the main surface of the general multilayer printed wiring board has a two-layer structure of electrolytic copper foil and plated copper. However, the inner surface of the through hole or the non-through hole is only a plated copper layer. It is difficult to reduce the thickness of the plated copper layer from the viewpoint of ensuring the electrical connection reliability of the plated copper layer of the through hole or the non-through hole.
Thus, a method has been proposed in which the electrolytic copper foil is entirely heated after being pressed and heated on the prepreg resin (for example, Patent Documents 1 and 2). In this method, since the rough surface shape of the copper foil is transferred to the surface where the prepreg resin is cured, when the electrolytic copper foil is removed by etching, the resin layer (prepreg resin in which the rough surface shape of the copper foil is transferred) is transferred. The surface (rough surface) is exposed. By performing electroless copper plating and electrolytic copper plating on this rough surface, not only the adhesion of the copper plating layer is ensured, but also the thickness of the copper layer can be reduced. As a result, fine wiring formation is advantageous.
電解銅箔をエッチング除去する前記の多層プリント配線板の製造方法ではビア孔の樹脂残渣除去のために過マンガン酸カリウム等によるデスミア処理が行われる。このデスミア処理は銅箔を除去した絶縁樹脂表面の粗面転写表面も処理される。その結果、銅箔の粗面形状を転写することによって銅めっきとの高い接着力が得られた表面形状が変化し、銅めっきとの密着力が低下すると言う問題があった。
上記の特許文献１ではこの問題を解決するために薄く銅めっきした後に、この薄い銅めっきを保護膜としてデスミア処理を行う方法が開示されている。しかしながら、薄い銅めっきの後にレーザビア加工およびデスミア処理が行われるために、これらの作業工程で薄い銅めっき膜表面が汚染されたり、傷つくなどの問題がある。
引用文献２の方法は絶縁樹脂層を２層にすると言う方法である。銅箔の粗面形状が転写される主面部分の樹脂層はデスミアに溶解しない樹脂組成とし、この樹脂層にデスミアに溶解する樹脂層を積層すると言う方法である。この絶縁樹脂構造ではビア孔底部の樹脂層はデスミアに溶解する樹脂層となるのでビア孔底部の樹脂残渣の除去性にも問題がない。しかし絶縁樹脂層を２層にする方法は材料の製造工程が複雑になりコストの点で不利である。
In the method for manufacturing a multilayer printed wiring board in which the electrolytic copper foil is removed by etching, desmearing with potassium permanganate or the like is performed to remove resin residues in via holes. In this desmear treatment, the rough transfer surface of the insulating resin surface from which the copper foil has been removed is also treated. As a result, there was a problem in that the surface shape obtained by transferring the rough surface shape of the copper foil changed the surface shape from which high adhesive strength with the copper plating was obtained, and the adhesive strength with the copper plating was reduced.
In the above-mentioned Patent Document 1, a method for performing desmear treatment using thin copper plating as a protective film after thin copper plating is disclosed in order to solve this problem. However, since laser via processing and desmear processing are performed after thin copper plating, there is a problem that the surface of the thin copper plating film is contaminated or damaged in these work steps.
The method of the cited document 2 is a method of having two insulating resin layers. In this method, the resin layer of the main surface portion onto which the rough surface shape of the copper foil is transferred has a resin composition that does not dissolve in desmear, and a resin layer that dissolves in desmear is laminated on this resin layer. In this insulating resin structure, since the resin layer at the bottom of the via hole becomes a resin layer that dissolves in desmear, there is no problem in the removability of the resin residue at the bottom of the via hole. However, the method of forming two insulating resin layers is disadvantageous in terms of cost because the manufacturing process of the material becomes complicated.
本発明は、前記課題に鑑みて、電解銅箔の粗面を転写した樹脂表面をマスクする必要がなく、また絶縁樹脂層を２層構造にしなくても、絶縁樹脂層のデスミアによる樹脂の溶解量と銅めっきの接着力、ビア底部のデスミア性、部品実装時のはんだ耐熱性を良好に確保できる多層プリント配線板の製造方法、多層プリント配線板の提供を目的としている。 In view of the above problems, the present invention eliminates the need to mask the resin surface to which the rough surface of the electrolytic copper foil is transferred, and even if the insulating resin layer does not have a two-layer structure, the resin is dissolved by desmearing of the insulating resin layer. The object is to provide a multilayer printed wiring board and a method for producing a multilayer printed wiring board capable of ensuring good amounts and adhesion of copper plating, desmearing properties at the bottom of the via, and solder heat resistance during component mounting.
上記課題を解決するため、本発明は、両面もしくは片面に配線パターンが形成された内層コア基板の両側もしくは片側に半硬化状態の絶縁樹脂層を重ね、さらにその外側に銅箔の粗化処理された面を重ね合わせて加圧・加熱し、この加圧・加熱により硬化させた前記絶縁樹脂層と前記銅箔とを前記内層コア基板に一体化した後、前記銅箔をエッチングによって除去することによって前記絶縁樹脂層の外表面に凹凸を形成する粗面化積層板形成工程と、この粗面化積層板形成工程の完了後に、前記絶縁樹脂層の外表面から前記内層コア基板の配線パターンに到達するビア穴を加工し、過マンガン酸アルカリを含む液によってデスミア処理を行い、無電解銅めっき触媒処理を行った後、無電解銅めっきおよび電気銅めっきを行うことによって導体を形成する導体層形成工程、とを具備する多層プリント配線板の製造方法において、前記絶縁樹脂層として、その形成樹脂が前記デスミア処理にて過マンガン酸アルカリを含む液に溶解可能な樹脂材料のみであり、デスミア処理の処理条件が過マンガン酸ナトリウム濃度６０ｇ／ｌ、ＮａＯＨ濃度４５ｇ／ｌ、液温８０℃、処理時間２０分における重量減少量が１ｇ／ｍ２以上、５ｇ／ｍ２以下である絶縁樹脂層を用いることを特徴とする多層プリント配線板の製造方法を提供する。
前記デスミア処理の処理条件での絶縁樹脂層の重量減少量が１ｇ／ｍ２以上であれば、ビア穴の底部に露出する有機物残渣であるスミアの除去を効率良く行える。また絶縁樹脂層の重量減少量が５ｇ／ｍ２以下であれば、銅箔の粗化面が転写された絶縁樹脂表面の形状の変化が少なく、はんだによる部品実装時の加熱によって銅めっき膜（無電解銅めっきの膜、及び、電気銅めっきの膜）が膨れると言う問題がない。この条件を満足する絶縁樹脂層を用いることによってビア穴の高い接続信頼性およびはんだ耐熱性の高い多層プリント配線板の製造が可能である。
In order to solve the above-mentioned problems, the present invention provides a semi-cured insulating resin layer on both sides or one side of an inner core substrate on which a wiring pattern is formed on both sides or one side, and further roughening copper foil on the outside. The insulating resin layer and the copper foil cured by pressing and heating are integrated with the inner core substrate, and then the copper foil is removed by etching. After the completion of the roughened laminate forming step for forming irregularities on the outer surface of the insulating resin layer and the roughened laminate forming step, the wiring pattern of the inner core substrate is formed from the outer surface of the insulating resin layer. Conductor by processing via holes that reach, desmear treatment with liquid containing alkali permanganate, electroless copper plating catalyst treatment, electroless copper plating and electrolytic copper plating Conductor layer forming step of forming, in the method for manufacturing a multilayer printed wiring board having a city, as the insulating resin layer, only a resin material soluble in a liquid containing the alkaline permanganate at its forming resin is the desmear treatment Yes , the desmear treatment conditions are sodium permanganate concentration 60 g / l, NaOH concentration 45 g / l, liquid temperature 80 ° C., and weight loss in a treatment time of 20 minutes is 1 g / m 2 or more and 5 g / m 2 or less. Provided is a method for producing a multilayer printed wiring board using an insulating resin layer.
When the weight reduction amount of the insulating resin layer under the desmear treatment conditions is 1 g / m 2 or more, it is possible to efficiently remove the smear that is an organic residue exposed at the bottom of the via hole. If the weight reduction amount of the insulating resin layer is 5 g / m 2 or less, there is little change in the shape of the surface of the insulating resin onto which the roughened surface of the copper foil is transferred, and the copper plating film ( There is no problem that the electroless copper plating film and the electrolytic copper plating film) swell. By using an insulating resin layer that satisfies this condition, it is possible to produce a multilayer printed wiring board having high connection reliability of via holes and high solder heat resistance.
また、本発明は、前記内層コア基板の前記絶縁樹脂層として、デスミア処理を行わなかった時の銅めっきのピール強度が０．７ｋＮ／ｍ以上であり、デスミア処理の処理条件が過マンガン酸ナトリウム濃度６０ｇ／ｌ、ＮａＯＨ濃度４５ｇ／ｌ、液温８０℃、処理時間２０分における前記銅めっきのピール強度が前記デスミア処理を行わなかった場合を１００とした時の８０％以上である絶縁樹脂層を用いることを特徴とする多層プリント配線板の製造方法を提供する。
この条件を満足する絶縁樹脂層を用いることによってビア穴の接続信頼性、はんだ耐熱性と共にピール強度の高い多層プリント配線板の製造が可能である。
Further, according to the present invention, the peel strength of the copper plating when the desmear treatment is not performed as the insulating resin layer of the inner core substrate is 0.7 kN / m or more, and the desmear treatment condition is sodium permanganate. Insulating resin layer having a concentration of 60 g / l, a NaOH concentration of 45 g / l, a liquid temperature of 80 ° C., and a peel strength of the copper plating at a treatment time of 20 minutes is 80% or more when the case where the desmear treatment is not performed is 100 A method for producing a multilayer printed wiring board is provided.
By using an insulating resin layer that satisfies this condition, it is possible to manufacture a multilayer printed wiring board having high peel strength as well as via hole connection reliability and solder heat resistance.
また、本発明は、前記導体層形成工程の完了後、この導体層形成工程にて得られた導体をパターニングして配線パターンを形成するパターニング工程を行い、前記パターニング工程の完了によって得られた多層プリント配線板を内層コア基板として機能させて、前記粗面化積層板形成工程と前記導体層形成工程とパターニング工程とを繰り返すことによって多層プリント配線板の層数を増やすことを特徴とする多層プリント配線板の製造方法を提供する。この方法によって高多層プリント配線板の製造が可能である。
また、本発明は、前記内層コア基板に半硬化状態の絶縁樹脂層を重ねさらにその外側に銅箔の粗化処理された面を重ね合わせて加圧・加熱する代わりに、前記内層コア基板に、銅箔の粗化処理された面に半硬化状態の絶縁樹脂層を有する樹脂付き銅箔を重ね合わせて加圧・加熱しても良く、この場合も同様の効果を得ることができる。
本発明に係る絶縁樹脂層としてはガラス繊維およびまたは無機充填材を含ませたものを用いることが可能であり、これによって剛性の向上、熱膨張率の低減が可能である。
本発明で使用する無電解銅めっき触媒としては、パラジウム−スズコロイド系のめっき触媒よりもアルカリシーダの使用が望ましい。また、無電解銅めっきの膜厚は０．１μｍ〜１．０μｍ、あるいはそれ以下であることが望ましい。アルカリシーダを用いることによってパラジウム−スズコロイド系触媒よりもめっき銅のピール強度が高い値が得られる。無電解銅めっきの膜厚を上記の範囲にすることによって高いピール強度が得られる。
また、本発明は、両面もしくは片面に配線パターンが形成された内層コア基板と、この内層コア基板の両側もしくは片側に積層された絶縁樹脂層と、この絶縁樹脂層の前記内層コア基板側とは反対の外面に形成された配線パターンと、前記絶縁樹脂層の外面から前記内層コア基板の配線パターンに到達するビア配線部とを有し、前記配線パターンは、前記絶縁樹脂層の粗面とされている前記外面に形成されており、前記絶縁樹脂層は、その形成樹脂が前記デスミア処理にて過マンガン酸アルカリを含む液に溶解可能な樹脂材料のみであり、過マンガン酸ナトリウム濃度６０ｇ／ｌ、ＮａＯＨ濃度４５ｇ／ｌ、液温８０℃、処理時間２０分の処理条件でデスミア処理を行ったときの重量減少量が１ｇ／ｍ２以上、５ｇ／ｍ２以下であることを特徴とする多層プリント配線板を提供する。
また、本発明は、前記内層コア基板の両側もしくは片側に、複数の前記絶縁樹脂層と、各絶縁樹脂層の前記内層コア基板側とは反対の外面である粗面に形成された配線パターンとが積層され、前記配線パターンを介して隣り合う絶縁樹脂層の内、前記内層コア基板から遠い側の絶縁樹脂層に、その外面から前記内層コア基板側の絶縁樹脂層の外面に形成された配線パターンに到達するビア配線部が形成されていることを特徴とする多層プリント配線板を提供する。
また、本発明は、前記絶縁樹脂層がガラス繊維および／または無機充填材を含むことを特徴とする多層プリント配線板を提供する。
In addition, the present invention performs a patterning step of forming a wiring pattern by patterning the conductor obtained in the conductor layer forming step after completion of the conductor layer forming step, and the multilayer obtained by completing the patterning step A multilayer printed circuit characterized in that the number of layers of the multilayer printed wiring board is increased by causing the printed wiring board to function as an inner layer core substrate and repeating the roughened laminated board forming step, the conductor layer forming step, and the patterning step. A method for manufacturing a wiring board is provided. By this method, it is possible to produce a high multilayer printed wiring board.
In addition, the present invention provides a method in which a semi-cured insulating resin layer is stacked on the inner layer core substrate and a roughened surface of the copper foil is stacked on the outer side, and pressure and heating are performed instead of pressing and heating. The copper foil with resin having the semi-cured insulating resin layer may be superposed on the roughened surface of the copper foil and pressed and heated. In this case, the same effect can be obtained.
As the insulating resin layer according to the present invention, it is possible to use a glass fiber and / or an inorganic filler, which can improve the rigidity and reduce the thermal expansion coefficient.
As the electroless copper plating catalyst used in the present invention, it is desirable to use an alkali seeder rather than a palladium-tin colloidal plating catalyst. The film thickness of the electroless copper plating is desirably 0.1 μm to 1.0 μm or less. By using an alkali seeder, a value having a higher peel strength of the plated copper than that of the palladium-tin colloidal catalyst can be obtained. By setting the film thickness of the electroless copper plating within the above range, high peel strength can be obtained.
The present invention also includes an inner layer core substrate having a wiring pattern formed on both sides or one side, an insulating resin layer laminated on both sides or one side of the inner layer core substrate, and the inner layer core substrate side of the insulating resin layer. It has a wiring pattern formed on the opposite outer surface and a via wiring portion that reaches the wiring pattern of the inner core board from the outer surface of the insulating resin layer, and the wiring pattern is a rough surface of the insulating resin layer. The insulating resin layer is formed only of a resin material whose resin is soluble in a liquid containing alkali permanganate by the desmear treatment, and has a sodium permanganate concentration of 60 g / l. , NaOH concentration 45 g / l, solution temperature 80 ° C., weight loss when subjected to desmear treatment with treatment conditions of processing time of 20 minutes is 1 g / m 2 or more, that is 5 g / m 2 or less To provide a multilayer printed circuit board according to symptoms.
Further, the present invention provides a plurality of the insulating resin layers on both sides or one side of the inner layer core substrate, and a wiring pattern formed on a rough surface which is an outer surface opposite to the inner layer core substrate side of each insulating resin layer; Of the insulating resin layers adjacent to each other through the wiring pattern, and the wiring formed on the outer surface of the insulating resin layer on the inner core substrate side from the outer surface thereof Provided is a multilayer printed wiring board characterized in that a via wiring portion reaching a pattern is formed.
Moreover, this invention provides the multilayer printed wiring board characterized by the said insulating resin layer containing glass fiber and / or an inorganic filler.
本発明によれば、微細配線形成性、ビア穴接続信頼性、はんだ耐熱性およびピール強度に優れる多層プリント配線板を低コストで得ることができる。 According to the present invention, a multilayer printed wiring board excellent in fine wiring formability, via hole connection reliability, solder heat resistance and peel strength can be obtained at low cost.
以下、本発明を実施した多層プリント配線板の製造方法、多層プリント配線板について、図面を参照して説明する。
図１（ａ）〜（ｅ）は多層プリント配線板の製造に用いる内層コア基板１１０（図１（ｅ）参照）の製造工程の一例を示す図、図２〜７は図１（ｅ）の内層コア基板１１０を用いて本発明にかかる多層プリント配線板１００（図７参照）を製造する工程（多層プリント配線板の製造方法）を説明する図である。
Hereinafter, a multilayer printed wiring board manufacturing method and a multilayer printed wiring board embodying the present invention will be described with reference to the drawings.
FIGS. 1A to 1E are diagrams showing an example of a manufacturing process of an inner layer core substrate 110 (see FIG. 1E) used for manufacturing a multilayer printed wiring board, and FIGS. 2 to 7 are views of FIG. It is a figure explaining the process (manufacturing method of a multilayer printed wiring board) which manufactures the multilayer printed wiring board 100 (refer FIG. 7) concerning this invention using the inner layer core board | substrate 110. FIG.
図７に示す多層プリント配線板１００は、電気絶縁性の樹脂層１の両面に配線６（配線パターン）が形成された内層コア基板１１０と、この内層コア基板１１０の両側に積層された絶縁樹脂層８と、この絶縁樹脂層８の前記内層コア基板１１０側とは反対の外面８１に形成された配線１３（配線パターン）と、前記絶縁樹脂層８の外面８１から前記内層コア基板１１０の配線６に到達する非貫通孔であるビア穴８２内の銅めっきであるビア配線部８３とを有して構成されている。
ビア配線部８３は、内層コア基板１１０の配線６と、絶縁樹脂層８の外面８１の配線１３とを電気的に接続する。
A multilayer printed wiring board 100 shown in FIG. 7 includes an inner layer core substrate 110 in which wirings 6 (wiring patterns) are formed on both surfaces of an electrically insulating resin layer 1, and an insulating resin laminated on both sides of the inner layer core substrate 110. Layer 8, wiring 13 (wiring pattern) formed on the outer surface 81 of the insulating resin layer 8 opposite to the inner core substrate 110 side, and wiring of the inner core substrate 110 from the outer surface 81 of the insulating resin layer 8 6 and a via wiring portion 83 which is copper plating in a via hole 82 which is a non-through hole reaching 6.
The via wiring portion 83 electrically connects the wiring 6 of the inner core substrate 110 and the wiring 13 of the outer surface 81 of the insulating resin layer 8.
前記絶縁樹脂層８は、ガラスエポキシ樹脂等の電気絶縁性の樹脂材料（熱硬化性樹脂）によって形成されている。この絶縁樹脂層８の形成材料としては、デスミア処理の処理条件が、過マンガン酸ナトリウム濃度６０ｇ／ｌ、ＮａＯＨ濃度４５ｇ／ｌ、液温８０℃、処理時間２０分において、重量減少量が１ｇ／ｍ２以上、５ｇ／ｍ２以下である材料を用いる。この絶縁樹脂層８は、形成樹脂中に、ガラス繊維および／または無機充填材を含むものであることが好ましく、この点、既述のガラスエポキシ樹脂が好適である。 The insulating resin layer 8 is formed of an electrically insulating resin material (thermosetting resin) such as glass epoxy resin. As a material for forming the insulating resin layer 8, the desmear treatment condition is a sodium permanganate concentration of 60 g / l, an NaOH concentration of 45 g / l, a liquid temperature of 80 ° C., and a treatment time of 20 minutes. A material having m 2 or more and 5 g / m 2 or less is used. The insulating resin layer 8 preferably contains glass fibers and / or an inorganic filler in the forming resin, and the glass epoxy resin described above is preferable in this respect.
また、絶縁樹脂層８の外面８１は、ミクロンからサブミクロンサイズの凹凸が形成された粗面とされている。これにより、外面８１に形成された銅めっき膜である配線１３には、絶縁樹脂層８に対する高い密着性が確保されており、はんだによる部品実装時の加熱によって銅めっき膜（配線１３）が膨れるといった不都合を抑えることができる。
この粗面は、後述のように、半硬化状態の絶縁樹脂層８に一体化した銅箔９（電解銅箔）の粗化処理された面の形状の転写によって形成できる。銅めっき膜は、銅箔９の除去によって露出させた外面８１（粗面）に形成される。
Further, the outer surface 81 of the insulating resin layer 8 is a rough surface on which irregularities of micron to submicron size are formed. Thereby, the wiring 13 which is a copper plating film formed on the outer surface 81 has high adhesion to the insulating resin layer 8, and the copper plating film (wiring 13) expands due to heating during component mounting by solder. Such an inconvenience can be suppressed.
As will be described later, this rough surface can be formed by transferring the shape of the roughened surface of the copper foil 9 (electrolytic copper foil) integrated with the semi-cured insulating resin layer 8. The copper plating film is formed on the outer surface 81 (rough surface) exposed by removing the copper foil 9.
ここで採用する絶縁樹脂層８の条件である前記「重量減少量」は、粗面を形成していない状態において、過マンガン酸ナトリウム濃度６０ｇ／ｌ、ＮａＯＨ濃度４５ｇ／ｌ、液温８０℃、処理時間２０分の条件でデスミア処理を行ったときの重量減少量を指す。また、本発明に係る多層プリント配線板の製造方法では、熱硬化性樹脂材料からなる絶縁樹脂層を半硬化状態で内層コア基板に重ねてから加熱硬化させるが、前記「重量減少量」は、硬化状態において上記条件でのデスミア処理を行ったときの重量減少量を指す。
そして、本発明では、この重量減少量が、１ｇ／ｍ２以上、５ｇ／ｍ２以下である樹脂材料を絶縁樹脂層として用いる。
The “weight loss”, which is a condition of the insulating resin layer 8 adopted here, is a sodium permanganate concentration of 60 g / l, a NaOH concentration of 45 g / l, a liquid temperature of 80 ° C., in a state where no rough surface is formed. It refers to the amount of weight reduction when desmear treatment is performed under the condition of a treatment time of 20 minutes. Moreover, in the method for producing a multilayer printed wiring board according to the present invention, the insulating resin layer made of a thermosetting resin material is heat cured after being superimposed on the inner layer core substrate in a semi-cured state. The amount of weight loss when the desmear treatment is performed under the above conditions in the cured state.
And in this invention, the resin material whose weight reduction amount is 1 g / m < 2 > or more and 5 g / m < 2 > or less is used as an insulating resin layer.
絶縁樹脂層８として、ビア穴８２内面のデスミア処理の処理条件が、過マンガン酸ナトリウム濃度６０ｇ／ｌ、ＮａＯＨ濃度４５ｇ／ｌ、液温８０℃、処理時間２０分において、重量減少量が１ｇ／ｍ２以上、５ｇ／ｍ２以下である樹脂材料からなる絶縁樹脂層を採用することは、多層プリント配線板１００の製造工程において、ビア穴８２を加工した基板（図４の積層基板１３０を参照）のデスミア処理の際に、ビア穴８２の底部に露出する有機物残渣であるスミアの除去を効率良く行える。しかも、デスミア処理による絶縁樹脂層８の外面８１の粗面の平滑化を抑えることができ、配線１３の、絶縁樹脂層８に対する密着性の確保に有効に寄与する。 As the insulating resin layer 8, the desmear treatment conditions for the inner surface of the via hole 82 are as follows: sodium permanganate concentration 60 g / l, NaOH concentration 45 g / l, liquid temperature 80 ° C., treatment time 20 minutes, and weight loss 1 g / l. Employing an insulating resin layer made of a resin material of m 2 or more and 5 g / m 2 or less means that the substrate in which the via hole 82 is processed in the manufacturing process of the multilayer printed wiring board 100 (see the laminated substrate 130 in FIG. 4). ), It is possible to efficiently remove the smear that is an organic residue exposed at the bottom of the via hole 82. In addition, the smoothing of the rough surface of the outer surface 81 of the insulating resin layer 8 due to the desmear process can be suppressed, and this contributes effectively to securing the adhesion of the wiring 13 to the insulating resin layer 8.
図１（ａ）〜（ｅ）に示すように、内層コア基板１１０は、例えば、ガラスエポキシ樹脂等の電気絶縁性の樹脂材料からなる樹脂層１（以下、樹脂基板とも言う）の両面に銅箔２が被着されてなる銅張積層板１１１（図１（ａ）参照）に貫通穴４を形成（図１（ｂ）参照）し、両面の銅箔２をエッチングによって完全に除去（図１（ｃ）参照）した後、樹脂基板１の表面（貫通穴４内面を含む）に無電解銅めっきのための触媒処理を行い、貫通穴４内面を含む全表面に無電解銅めっき（図１中図示略。図８中、符号５ａ参照）及び電気銅めっき５を施し（図１（ｄ）参照）、次いで、エッチングレジストの形成を含む周知のエッチング法により両主面の銅層（無電解銅めっき５ａ及び電気銅めっき５）をパターニングして配線６を形成した（図１（ｅ）参照）ものである。 As shown in FIGS. 1A to 1E, an inner core substrate 110 is formed of copper on both surfaces of a resin layer 1 (hereinafter also referred to as a resin substrate) made of an electrically insulating resin material such as a glass epoxy resin. A through-hole 4 is formed in the copper clad laminate 111 (see FIG. 1A) to which the foil 2 is applied (see FIG. 1B), and the copper foils 2 on both sides are completely removed by etching (see FIG. 1). 1 (c)), the surface of the resin substrate 1 (including the inner surface of the through hole 4) is subjected to a catalyst treatment for electroless copper plating, and the entire surface including the inner surface of the through hole 4 is subjected to electroless copper plating (see FIG. 1 (see reference numeral 5a in FIG. 8) and electrolytic copper plating 5 (see FIG. 1 (d)), and then copper layers (nothing on both main surfaces) by a well-known etching method including formation of an etching resist. The wiring 6 was formed by patterning the electrolytic copper plating 5a and the electrolytic copper plating 5). 1 (e) refer) it is intended.
また、この実施形態では、内層コア基板１１０として、貫通穴４に穴埋め樹脂７を印刷法等で充填したものを用いる。但し、本発明は、貫通穴４に穴埋め樹脂７を充填していない内層コア基板１１０を用いることを排除しない。
また、内層コア基板１１０としては、両面を研磨したものを用いることが好ましい。
In this embodiment, as the inner core substrate 110, the through hole 4 filled with the hole filling resin 7 by a printing method or the like is used. However, the present invention does not exclude the use of the inner layer core substrate 110 in which the through hole 4 is not filled with the hole filling resin 7.
Further, as the inner layer core substrate 110, it is preferable to use a substrate whose both surfaces are polished.
図１（ａ）に示す銅張積層板１１１としては、樹脂基板１の表面に銅箔２の粗面３が密着状態に接触されたものを用いて、銅箔２をエッチングによって完全に除去（図１（ｃ）参照）したときに、銅箔２の粗面３の凹凸の転写によってミクロンサイズからサブミクロンサイズの凹凸が形成された樹脂基板１表面（粗面）が露出されることが好ましい。これにより、貫通穴４内面を含む全表面に施す無電解銅めっき５ａ及び電気銅めっき５の樹脂基板１に対する密着性を高めることができる。 As the copper-clad laminate 111 shown in FIG. 1 (a), the copper foil 2 is completely removed by etching using a surface of the resin substrate 1 in which the rough surface 3 of the copper foil 2 is in close contact ( When the unevenness of the rough surface 3 of the copper foil 2 is transferred, the surface (rough surface) of the resin substrate 1 on which the unevenness of the micron size to the submicron size is formed is preferably exposed. . Thereby, the adhesiveness with respect to the resin substrate 1 of the electroless copper plating 5a performed on the whole surface including the through-hole 4 inner surface and the electrolytic copper plating 5 can be improved.
次に、上述の内層コア基板１１０を用いた多層プリント配線板１００の製造方法について説明する。
ここで説明する多層プリント配線板の製造方法は、図２、図３に示すように、内層コア基板１１０の両側（両面）に半硬化状態の絶縁樹脂層８と銅箔９とを重ね合わせて一体化した後、エッチングによって前記銅箔９を除去して前記銅箔９の粗化処理された面の凹凸が転写された絶縁樹脂層８表面（外表面。外面８１）を露出させる粗面化積層板形成工程と、この粗面化積層板形成工程の後、前記絶縁樹脂層８にビア穴８２を加工（図４）して、デスミア処理及び無電解銅めっき触媒処理を行った後、無電解銅めっきおよび電気銅めっきを行うことによって導体を形成する導体層形成工程と、この導体層形成工程にて形成した導体（図７、図８参照。導体層１５及びビア配線部８３）の内、絶縁樹脂層８の外面８１側を覆うめっき層（導体層１５）をパターニングして配線１３（図７参照）を形成するパターニング工程とを具備する。
Next, a manufacturing method of the multilayer printed wiring board 100 using the above-described inner layer core substrate 110 will be described.
2 and 3, the multilayer printed wiring board manufacturing method described here is obtained by superposing the semi-cured insulating resin layer 8 and the copper foil 9 on both sides (both sides) of the inner layer core substrate 110. As shown in FIG. After the integration, the copper foil 9 is removed by etching to roughen the surface of the insulating resin layer 8 (outer surface, outer surface 81) to which the unevenness of the roughened surface of the copper foil 9 has been transferred. After the laminated plate forming step and the roughened laminated plate forming step, via holes 82 are processed in the insulating resin layer 8 (FIG. 4), and after desmear treatment and electroless copper plating catalyst treatment, Conductor layer forming step of forming a conductor by performing electrolytic copper plating and electrolytic copper plating, and conductors formed in this conductor layer forming step (see FIGS. 7 and 8; conductor layer 15 and via wiring portion 83) The plating layer (conductor layer) covering the outer surface 81 side of the insulating resin layer 8 5) by patterning the wiring 13 (including a patterning step of forming a reference Figure 7).
（粗面化積層板形成工程）
粗面化積層板形成工程は、まず、図２に示すように、内層コア基板１１０の両側（両面）に、絶縁樹脂層８と銅箔９とをこの順序で重ね合わせ、加圧、加熱して一体化する。これにより、内層コア基板１１０に、絶縁樹脂層８と銅箔９とが一体化された銅箔付き積層基板１２０が得られる。
(Roughening laminate forming process)
In the roughened laminate forming step, first, as shown in FIG. 2, the insulating resin layer 8 and the copper foil 9 are superposed in this order on both sides (both sides) of the inner layer core substrate 110, and pressed and heated. And integrate. Thereby, the laminated substrate 120 with a copper foil in which the insulating resin layer 8 and the copper foil 9 are integrated with the inner layer core substrate 110 is obtained.
絶縁樹脂層８としては、既述のように、ガラスエポキシ樹脂等の熱硬化性樹脂材料からなるものを採用するが、絶縁樹脂層８は、内層コア基板１１０に、加熱硬化前の半硬化状態で重ね合わせた後、加圧、加熱によって硬化させるとともに、内層コア基板１１０に一体化する。絶縁樹脂層８の硬化によって、絶縁樹脂層８、内層コア基板１１０に対する銅箔９の一体化も実現される。 As described above, the insulating resin layer 8 is made of a thermosetting resin material such as glass epoxy resin, but the insulating resin layer 8 is formed on the inner core substrate 110 in a semi-cured state before heat curing. After being superposed, they are cured by pressurization and heating, and integrated with the inner layer core substrate 110. By curing the insulating resin layer 8, integration of the copper foil 9 with the insulating resin layer 8 and the inner core substrate 110 is also realized.
また、半硬化状態の絶縁樹脂層８には、銅箔９の粗化処理された面（粗面１０）を圧接させ、粗面１０の形状を絶縁樹脂層８の表面（内層コア基板１１０とは反対の側の面。外面８１）に転写する。 The semi-cured insulating resin layer 8 is brought into pressure contact with the roughened surface (rough surface 10) of the copper foil 9, and the shape of the rough surface 10 is changed to the surface of the insulating resin layer 8 (with the inner core substrate 110). Is transferred to the opposite surface (outer surface 81).
また、本発明は、内層コア基板１１０に半硬化状態の絶縁樹脂層８を重ねた後、この絶縁樹脂層８の外側に銅箔９を重ね合わせることに限定されず、銅箔９の粗化処理された面に半硬化状態の絶縁樹脂層を有する樹脂付き銅箔を前記内層コア基板１１０に重ね合わせても良い。この場合も、樹脂付き銅箔を前記内層コア基板１１０に重ね合わせた後、加圧・加熱によって、半硬化状態の絶縁樹脂層の硬化、絶縁樹脂層及び銅箔の内層コア基板１１０に対する一体化を行うことで、内層コア基板１１０に半硬化状態の絶縁樹脂層８を重ねた後、この絶縁樹脂層８の外側に銅箔９を重ね合わせた場合と同様に、銅箔付き積層基板１２０が得られることは言うまでも無い。 In addition, the present invention is not limited to superimposing the copper foil 9 on the outer side of the insulating resin layer 8 after the semi-cured insulating resin layer 8 is superimposed on the inner core substrate 110, and roughening the copper foil 9. A resin-coated copper foil having a semi-cured insulating resin layer on the treated surface may be superimposed on the inner core substrate 110. Also in this case, after the resin-coated copper foil is superposed on the inner core substrate 110, the insulating resin layer in a semi-cured state is cured by pressing and heating, and the insulating resin layer and the copper foil are integrated with the inner core substrate 110. In the same manner as in the case where the semi-cured insulating resin layer 8 is overlaid on the inner layer core substrate 110 and then the copper foil 9 is overlaid on the outside of the insulating resin layer 8, the laminated substrate 120 with the copper foil is formed. Needless to say, it can be obtained.
次に、図３に示すように、銅箔付き積層基板１２０の両面の銅箔９を、エッチングによって完全に除去する。これにより、銅箔９の粗面１０の転写によって粗面化された絶縁樹脂層８表面（外面８１）を露出させる。
以下、銅箔付き積層基板１２０から銅箔９を除去したものを積層基板１３０とも言う。
Next, as shown in FIG. 3, the copper foils 9 on both surfaces of the laminated substrate 120 with the copper foil are completely removed by etching. Thereby, the surface (outer surface 81) of the insulating resin layer 8 roughened by the transfer of the rough surface 10 of the copper foil 9 is exposed.
Hereinafter, what removed the copper foil 9 from the laminated substrate 120 with a copper foil is also called the laminated substrate 130.
銅箔９の除去によって露出された絶縁樹脂層８表面（外面８１）には、銅箔９の粗面１０形状が転写されたミクロンからサブミクロンサイズの凹凸が形成されている。
銅箔９としては、粗面１０の表面粗さが、Ｒａ＝０．８〜１．４μｍ、Ｒｚ＝４．０〜８．０μｍのものを採用することが好ましい。絶縁樹脂層８表面（外面８１）にも、銅箔９の粗面１０と同じ表面粗さの粗面が形成される。
On the surface (outer surface 81) of the insulating resin layer 8 exposed by the removal of the copper foil 9, irregularities having a micron to submicron size are formed on which the shape of the rough surface 10 of the copper foil 9 is transferred.
As the copper foil 9, it is preferable to employ one having a rough surface 10 with a surface roughness of Ra = 0.8 to 1.4 μm and Rz = 4.0 to 8.0 μm. A rough surface having the same surface roughness as the rough surface 10 of the copper foil 9 is also formed on the surface of the insulating resin layer 8 (outer surface 81).
（導体層形成工程）
次に、図４に示すように、積層基板１３０の絶縁樹脂層８にビア穴８２を加工する。
このビア穴８２は、例えば、炭酸ガスレーザを用いたレーザ加工によって、絶縁樹脂層８の外面８１側から内層コア基板１１０の配線６に達するように形成する。
但し、本発明は、切削加工等の機械加工を排除するものでは無い。
(Conductor layer forming process)
Next, as shown in FIG. 4, a via hole 82 is processed in the insulating resin layer 8 of the multilayer substrate 130.
The via hole 82 is formed so as to reach the wiring 6 of the inner core substrate 110 from the outer surface 81 side of the insulating resin layer 8 by, for example, laser processing using a carbon dioxide laser.
However, the present invention does not exclude machining such as cutting.
次いで、デスミア処理を行う。
このデスミア処理は、例えば、積層基板１３０のビア穴８２内面を含む全外表面に、過マンガン酸ナトリウム濃度６０±１０ｇ/ｌ、ＮａＯＨ濃度４５±１０ｇ/ｌを含む液を、液温７０〜８０℃で、３〜１２分（より好ましくは５〜１０分）接触させる。
過マンガン酸ナトリウム濃度６０ｇ／ｌ、ＮａＯＨ濃度４５ｇ／ｌを含む液を、液温８０℃で、３〜１２分（より好ましくは５〜１０分）接触させて処理することも勿論可能である。
Next, desmear processing is performed.
In this desmear treatment, for example, a liquid containing a sodium permanganate concentration of 60 ± 10 g / l and a NaOH concentration of 45 ± 10 g / l is applied to the entire outer surface including the inner surface of the via hole 82 of the laminated substrate 130 at a liquid temperature of 70-80. The contact is made at 3 ° C. for 3 to 12 minutes (more preferably 5 to 10 minutes).
It is of course possible to treat a liquid containing a sodium permanganate concentration of 60 g / l and a NaOH concentration of 45 g / l at a liquid temperature of 80 ° C. for 3 to 12 minutes (more preferably 5 to 10 minutes).
次に、積層基板１３０のビア穴８２内面を含む全表面に無電解銅めっき用触媒処理を行った後、図５に示すように、ビア穴８２内面を含む全表面に無電解銅めっきを施し、次いで、ビアフィリングタイプの電気銅めっきを施す。これにより、積層基板１３０の両面（両側の絶縁樹脂層８の外面８１）を覆う導体層１５と、ビア穴８２内のビア配線部８３とを形成する。
図８に示すように、導体層１５は、無電解銅めっきのめっき膜（無電解銅めっき層１４）の内の絶縁樹脂層８の外面８１（外表面）を覆うように形成された部分と、これに積層するようにして形成された電気銅めっき層１２とで構成される。また、ビア配線部８３は、無電解銅めっき層１４の内のビア穴８２内面に形成された部分と、電気銅めっきの内のビア穴８２内に充填された部分とによって構成される。
Next, after the electroless copper plating catalyst treatment is performed on the entire surface including the inner surface of the via hole 82 of the multilayer substrate 130, the entire surface including the inner surface of the via hole 82 is subjected to electroless copper plating as shown in FIG. Then, via filling type electrolytic copper plating is performed. Thereby, the conductor layer 15 covering both surfaces of the multilayer substrate 130 (the outer surfaces 81 of the insulating resin layers 8 on both sides) and the via wiring portion 83 in the via hole 82 are formed.
As shown in FIG. 8, the conductor layer 15 includes a portion formed so as to cover the outer surface 81 (outer surface) of the insulating resin layer 8 in the electroless copper plating film (electroless copper plating layer 14). And an electrolytic copper plating layer 12 formed so as to be laminated thereon. The via wiring portion 83 is constituted by a portion formed on the inner surface of the via hole 82 in the electroless copper plating layer 14 and a portion filled in the via hole 82 in the electrolytic copper plating.
本発明で使用する無電解銅めっき触媒としては、パラジウム−スズコロイド系のめっき触媒よりもアルカリシーダの使用が望ましい。また、無電解銅めっきの膜厚は０．１μｍ〜１．０μｍ、あるいはそれ以下であることが望ましい。アルカリシーダを用いることによってパラジウム−スズコロイド系触媒よりもめっき銅のピール強度が高い値が得られる。また、無電解銅めっきの膜厚を上記の範囲にする（つまり、膜厚を大きくしない）ことによって、高いピール強度が得られる。 As the electroless copper plating catalyst used in the present invention, it is desirable to use an alkali seeder rather than a palladium-tin colloidal plating catalyst. The film thickness of the electroless copper plating is desirably 0.1 μm to 1.0 μm or less. By using an alkali seeder, a value having a higher peel strength of the plated copper than that of the palladium-tin colloidal catalyst can be obtained. Further, by setting the film thickness of the electroless copper plating in the above range (that is, not increasing the film thickness), a high peel strength can be obtained.
（パターニング工程）
次に、この導体層形成工程にて形成した導体層１５をパターニングして配線１３を形成するパターニング工程を行う。
このパターニング工程では、図６に示すエッチングレジスト１６の形成を含む周知のエッチング法によって配線１３を形成する。
パターニング工程が完了することで、図７の多層プリント配線板１００が得られる。
(Patterning process)
Next, a patterning step for patterning the conductor layer 15 formed in this conductor layer forming step to form the wiring 13 is performed.
In this patterning step, the wiring 13 is formed by a known etching method including the formation of the etching resist 16 shown in FIG.
By completing the patterning step, the multilayer printed wiring board 100 of FIG. 7 is obtained.
この多層プリント配線板の製造方法によれば、絶縁樹脂層８として、デスミア処理の処理条件が、過マンガン酸ナトリウム濃度６０ｇ／ｌ、ＮａＯＨ濃度４５ｇ／ｌ、液温８０℃、処理時間２０分において、重量減少量が１ｇ／ｍ２以上、５ｇ／ｍ２以下である樹脂材料からなる絶縁樹脂層を採用することにより、多層プリント配線板１００の製造工程において、ビア穴８２を加工した積層基板１３０（図４参照）のデスミア処理の際に、ビア穴８２の底部に露出する有機物残渣であるスミアの除去を効率良く行える。しかも、デスミア処理による絶縁樹脂層８の外面８１の粗面の平滑化を抑えることができ、配線１３の、絶縁樹脂層８に対する密着性の確保に有効に寄与する。その結果、多層プリント配線板１００について、はんだによる部品実装時の加熱によって銅めっき膜（無電解銅めっきの膜、及び、電気銅めっきの膜）が膨れると言う問題がない。
つまり、デスミア処理の処理条件（以下、デスミア条件とも言う）が、過マンガン酸ナトリウム濃度６０ｇ／ｌ、ＮａＯＨ濃度４５ｇ／ｌ、液温８０℃、処理時間２０分において、重量減少量が１ｇ／ｍ２以上、５ｇ／ｍ２以下である樹脂材料からなる絶縁樹脂層８の採用によって、ビア穴の高い接続信頼性およびはんだ耐熱性の高い多層プリント配線板の製造が可能である。
According to this method for producing a multilayer printed wiring board, as the insulating resin layer 8, the desmear treatment conditions are as follows: sodium permanganate concentration 60 g / l, NaOH concentration 45 g / l, liquid temperature 80 ° C., treatment time 20 minutes. By adopting an insulating resin layer made of a resin material having a weight reduction amount of 1 g / m 2 or more and 5 g / m 2 or less, the multilayer substrate 130 in which the via hole 82 is processed in the manufacturing process of the multilayer printed wiring board 100. In the desmear process of FIG. 4 (see FIG. 4), it is possible to efficiently remove smear that is an organic residue exposed at the bottom of the via hole 82. In addition, the smoothing of the rough surface of the outer surface 81 of the insulating resin layer 8 due to the desmear process can be suppressed, and this contributes effectively to securing the adhesion of the wiring 13 to the insulating resin layer 8. As a result, there is no problem with the multilayer printed wiring board 100 that the copper plating film (electroless copper plating film and electrolytic copper plating film) swells due to heating during component mounting with solder.
That is, when the desmear treatment condition (hereinafter also referred to as desmear condition) is sodium permanganate concentration 60 g / l, NaOH concentration 45 g / l, liquid temperature 80 ° C., treatment time 20 minutes, the weight loss is 1 g / m. By employing the insulating resin layer 8 made of a resin material of 2 or more and 5 g / m 2 or less, it is possible to manufacture a multilayer printed wiring board having high connection reliability with via holes and high solder heat resistance.
図９〜図１３は、図７の多層プリント配線板１００に、さらに、絶縁樹脂層８、配線１３を積層して、内層コア基板１１０の両側（両面）にそれぞれ、絶縁樹脂層８、配線１３を複数層積層した構成の多層プリント配線板１４０（図１３参照）、及び、その製造方法を説明する図である。
図１３に示す多層プリント配線板１４０は、内層コア基板１１０の両側（両面）に、絶縁樹脂層８、配線１３がそれぞれ２層ずつ積層された構成になっている。
9 to 13, the insulating resin layer 8 and the wiring 13 are further laminated on the multilayer printed wiring board 100 of FIG. 7, and the insulating resin layer 8 and the wiring 13 are respectively formed on both sides (both sides) of the inner layer core substrate 110. It is a figure explaining the multilayer printed wiring board 140 (refer FIG. 13) of the structure which laminated | stacked two or more layers, and its manufacturing method.
A multilayer printed wiring board 140 shown in FIG. 13 has a configuration in which two layers of the insulating resin layer 8 and the wiring 13 are laminated on both sides (both sides) of the inner layer core substrate 110.
この多層プリント配線板１４０は、多層プリント配線板１００を組み立てた後、この多層プリント配線板１００の両面に、半硬化状態の絶縁樹脂層８（多層プリント配線板１００の絶縁樹脂層８との区別のため、図中、符号８Ａを付す）及び銅箔９を重ねて加圧、加熱により一体化してから銅箔９を除去する粗面化積層板形成工程と、前記絶縁樹脂層８Ａにビア穴を加工して、デスミア処理及び無電解銅めっき触媒処理を行った後、無電解銅めっきおよび電気銅めっきを行うことによって導体を形成する導体層形成工程と、この導体層形成工程にて形成した導体（図１２参照。導体層１５及びビア配線部８３）の内、絶縁樹脂層８Ａの内層コア基板１１０側とは反対の外面８１側を覆うめっき層（導体層１５）をパターニングして配線１３（図１３参照）を形成するパターニング工程とを行うことで製造できる。
つまり、いわば、多層プリント配線板１００を内層コア基板として機能させて、粗面化積層板形成工程と、導体層形成工程と、パターニング工程とを行う。
After the multilayer printed wiring board 100 is assembled, the multilayer printed wiring board 140 is formed on both surfaces of the multilayer printed wiring board 100 with the semi-cured insulating resin layer 8 (the distinction from the insulating resin layer 8 of the multilayer printed wiring board 100). Therefore, a roughened laminate forming step of removing the copper foil 9 after the copper foil 9 is integrated by pressurization and heating, and a via hole is formed in the insulating resin layer 8A. After conducting desmear treatment and electroless copper plating catalyst treatment, a conductor layer forming step of forming a conductor by performing electroless copper plating and electrolytic copper plating, and this conductor layer forming step Of the conductor (see FIG. 12, conductor layer 15 and via wiring portion 83), the plating layer (conductor layer 15) covering the outer surface 81 side opposite to the inner core substrate 110 side of the insulating resin layer 8A is patterned to form the wiring 13. ( 13 reference) can be produced by performing a patterning step of forming a.
In other words, the multilayer printed wiring board 100 is caused to function as an inner layer core substrate, and a roughened laminated board forming process, a conductor layer forming process, and a patterning process are performed.
図９〜図１３を参照して、多層プリント配線板１４０の製造方法を説明する。
まず、図９に示すように、多層プリント配線板１００の両面（両側）に、半硬化状態の絶縁樹脂層８Ａ及び銅箔９を、銅箔９が絶縁樹脂層８の内層コア基板１１０側とは反対の外面８１側となるように重ねて加圧、加熱により一体化する。また、これにより絶縁樹脂層８Ａが硬化される。多層プリント配線板１００に半硬化状態の絶縁樹脂層８Ａ及び銅箔９を積層する手法は、既述の多層プリント配線板１００の製造方法と同様の手法を採用できる。つまり、多層プリント配線板１００に半硬化状態の絶縁樹脂層を重ねた後に銅箔９を重ねる手法、または、樹脂付き銅箔を重ねる手法、のいずれも採用可能である。
次いで、銅箔９を、エッチングによって完全に除去する（図１０）。これにより、銅箔９の粗面１０の転写によって粗面化された絶縁樹脂層８Ａ表面（外面８１。粗面）を露出させる。
A method for manufacturing the multilayer printed wiring board 140 will be described with reference to FIGS.
First, as shown in FIG. 9, the semi-cured insulating resin layer 8 </ b> A and the copper foil 9 are provided on both surfaces (both sides) of the multilayer printed wiring board 100, and the copper foil 9 is connected to the inner core substrate 110 side of the insulating resin layer 8. Are stacked so as to be on the opposite outer surface 81 side and integrated by pressurization and heating. This also cures the insulating resin layer 8A. As a method of laminating the semi-cured insulating resin layer 8A and the copper foil 9 on the multilayer printed wiring board 100, a method similar to the method for manufacturing the multilayer printed wiring board 100 described above can be adopted. That is, it is possible to employ either a method of overlapping the copper foil 9 after the semi-cured insulating resin layer is stacked on the multilayer printed wiring board 100 or a method of stacking the resin-coated copper foil.
Next, the copper foil 9 is completely removed by etching (FIG. 10). Thereby, the surface (outer surface 81. rough surface) of the insulating resin layer 8A roughened by the transfer of the rough surface 10 of the copper foil 9 is exposed.
次いで、前記絶縁樹脂層８Ａにビア穴８２を加工（図１１）し、デスミア処理及び無電解銅めっき触媒処理を行った後、絶縁樹脂層８Ａの全面に無電解銅めっきおよび電気銅めっきを施して、導体（図１２参照。導体層１５及びビア配線部８３）を形成する。
ビア穴８２は、絶縁樹脂層８Ａの外面８１から、該外面８１とは反対の内面側に接合されている絶縁樹脂層８の外面に形成された配線１３に到達させて形成する。ビア配線部８３は、パターニング工程にて絶縁樹脂層８Ａの外面８１側に形成される配線１３と、絶縁樹脂層８Ａの内面側の絶縁樹脂層８の配線１３とを電気的に接続する。
デスミア条件、無電解銅めっき触媒処理は、既述の多層プリント配線板１００の製造方法と同様である。また、既述の多層プリント配線板１００の製造方法と同様に、無電解銅めっきの膜厚は０．１μｍ〜１．０μｍ、あるいはそれ以下とする。
Next, via holes 82 are processed in the insulating resin layer 8A (FIG. 11), desmear treatment and electroless copper plating catalyst treatment are performed, and then electroless copper plating and electrolytic copper plating are applied to the entire surface of the insulating resin layer 8A. Then, a conductor (see FIG. 12, the conductor layer 15 and the via wiring portion 83) is formed.
The via hole 82 is formed by reaching the wiring 13 formed on the outer surface of the insulating resin layer 8 joined to the inner surface opposite to the outer surface 81 from the outer surface 81 of the insulating resin layer 8A. The via wiring part 83 electrically connects the wiring 13 formed on the outer surface 81 side of the insulating resin layer 8A in the patterning step and the wiring 13 of the insulating resin layer 8 on the inner surface side of the insulating resin layer 8A.
The desmear conditions and the electroless copper plating catalyst treatment are the same as those in the method for manufacturing the multilayer printed wiring board 100 described above. Moreover, the film thickness of electroless copper plating shall be 0.1 micrometer-1.0 micrometer or less similarly to the manufacturing method of the multilayer printed wiring board 100 as stated above.
次に、図１３に示すように、エッチングレジスト１６の形成を含む周知のエッチング法を用いて、絶縁樹脂層８Ａの外面８１側を覆うめっき層（導体層１５）をパターニングして配線１３を形成する。 Next, as shown in FIG. 13, by using a known etching method including the formation of the etching resist 16, the wiring layer 13 is formed by patterning the plating layer (conductor layer 15) covering the outer surface 81 side of the insulating resin layer 8A. To do.
図１３に例示した多層プリント配線板１４０は、図２〜図１３に示すように、内層コア基板１１０について、粗面化積層板形成工程と、導体層形成工程と、パターニング工程とからなる多層化工程を２回実施することで得られる。
但し、本発明はこれに限定されず、多層化工程を３回以上繰り返し実施して、さらなる多層化を実現しても良い。
As shown in FIGS. 2 to 13, the multilayer printed wiring board 140 illustrated in FIG. 13 has a multilayer structure including a roughened laminated board forming step, a conductor layer forming step, and a patterning step. It is obtained by carrying out the process twice.
However, the present invention is not limited to this, and the multilayering process may be repeated three or more times to realize further multilayering.
なお、本発明では、必ずしも内層コア基板１１０の両側に同数の絶縁樹脂層８、配線１３を積層する構成に限定されない。
本発明は、例えば、内層コア基板１１０の片側（片面）のみに、絶縁樹脂層８、配線１３を積層して、多層プリント配線板を得ることも含む。
また、内層コア基板１１０の一方の側における絶縁樹脂層８、配線１３の積層数が、他方の側における積層数よりも多くした構成を含む。
The present invention is not necessarily limited to the configuration in which the same number of insulating resin layers 8 and wirings 13 are stacked on both sides of the inner core substrate 110.
The present invention includes, for example, obtaining the multilayer printed wiring board by laminating the insulating resin layer 8 and the wiring 13 only on one side (one side) of the inner layer core substrate 110.
In addition, the number of stacked layers of the insulating resin layer 8 and the wiring 13 on one side of the inner core substrate 110 is larger than the number of stacked layers on the other side.
以下、本発明に係る実施例１、２、比較例１、２を用いて、本発明の効果を対比説明する。 Hereinafter, the effects of the present invention will be described in comparison with Examples 1 and 2 and Comparative Examples 1 and 2 according to the present invention.
（実施例１）
図１（ａ）に示す厚さ０．４ｍｍのガラスエポキシ樹脂銅張積層板１１１を準備した。この銅張積層板１１１はガラスエポキシ樹脂層１（樹脂基板）の表面に厚さ１２μｍの銅箔２の粗面３が樹脂層に接触するように積層したものである。
次に図１（ｂ）に示すようにドリルで貫通穴４をあけた。次に図１（ｃ）に示すように表面の銅箔２をエッチングによって完全に除去した。次に積層基板１３０の表面に無電解銅めっきのための触媒処理を行った後、図１（ｄ）に示すように、積層基板１３０の貫通穴４を含む全表面に無電解銅めっきを０．３μｍ施し、更に厚さ１５μｍｍの電気銅めっき５を施した。次に図１（ｅ）に示すように周知の工法でエッチングレジストを形成し、内層配線板を作製した。次に貫通穴に穴埋め樹脂７を印刷法で充填し、表面を研磨することによって内層コア基板１１０を作製した。
Example 1
A glass epoxy resin copper-clad laminate 111 having a thickness of 0.4 mm shown in FIG. The copper-clad laminate 111 is laminated on the surface of the glass epoxy resin layer 1 (resin substrate) so that the rough surface 3 of the copper foil 2 having a thickness of 12 μm is in contact with the resin layer.
Next, as shown in FIG.1 (b), the through-hole 4 was drilled. Next, as shown in FIG. 1C, the surface copper foil 2 was completely removed by etching. Next, after the catalyst treatment for electroless copper plating is performed on the surface of the multilayer substrate 130, electroless copper plating is applied to the entire surface including the through holes 4 of the multilayer substrate 130 as shown in FIG. Then, 3 μm was applied, and further 15 μm thick electrolytic copper plating 5 was applied. Next, as shown in FIG.1 (e), the etching resist was formed by the well-known construction method, and the inner-layer wiring board was produced. Next, the filling resin 7 was filled in the through holes by a printing method, and the inner layer core substrate 110 was produced by polishing the surface.
次に図２に示すように、厚さ０．０５ｍｍのガラスエポキシ樹脂系絶縁層８（絶縁樹脂層）と厚さ１２μｍの銅箔９をこの順序でコア基板の両側に重ね合わせて加圧・加熱積層した。銅箔９の粗面１０がガラスエポキシ樹脂絶縁層８と接触するように重ね合わせた。このガラスエポキシ樹脂系絶縁層８としては日立化成工業株式会社製Ｅ−６７９Ｆを用いた。デスミア処理による重量減少量は３．２ｇ/ｍ２であった。デスミア処理条件は過マンガン酸ナトリウム濃度６０ｇ／ｌ、ＮａＯＨ濃度４５ｇ／ｌ、液温８０℃、処理時間２０分である。 Next, as shown in FIG. 2, a glass epoxy resin insulating layer 8 (insulating resin layer) having a thickness of 0.05 mm and a copper foil 9 having a thickness of 12 μm are stacked in this order on both sides of the core substrate, Heat lamination was performed. The copper foil 9 was laminated so that the rough surface 10 was in contact with the glass epoxy resin insulating layer 8. As this glass epoxy resin-based insulating layer 8, E-679F manufactured by Hitachi Chemical Co., Ltd. was used. The amount of weight reduction due to desmear treatment was 3.2 g / m 2 . The desmear treatment conditions are a sodium permanganate concentration of 60 g / l, a NaOH concentration of 45 g / l, a liquid temperature of 80 ° C., and a treatment time of 20 minutes.
銅箔９は、日鉱金属株式会社製「ＪＴＣ」を用いた。
銅箔の厚さは１２μｍである。表面粗さを測定したところ、Ｒａ：０．８４μｍ（３０箇所の平均値）、Ｒｚ：４．７６μｍ（３０箇所の平均値）であった。粗さ測定装置として、株式会社小坂研究所製ＳＥ−３Ｃ（触針式粗さ測定装置）を用いた。
測定条件は、カットオフ：０．２５ｍｍ、基準長さ：０．８ｍｍ、測定速度：０．１ｍｍ／ｓ、触針先端の大きさ：２μｍである。
As the copper foil 9, “JTC” manufactured by Nikko Metal Co., Ltd. was used.
The thickness of the copper foil is 12 μm. When the surface roughness was measured, they were Ra: 0.84 μm (average value at 30 locations) and Rz: 4.76 μm (average value at 30 locations). SE-3C (stylus roughness measuring device) manufactured by Kosaka Laboratory Ltd. was used as the roughness measuring device.
The measurement conditions are cut-off: 0.25 mm, reference length: 0.8 mm, measurement speed: 0.1 mm / s, and stylus tip size: 2 μm.
次に図３に示すように表面の銅箔９をエッチングによって完全に除去した。
銅箔９が完全に除去されたガラスエポキシ樹脂絶縁層８表面には銅箔９の粗面形状が転写されている。
次に図４に示すように炭酸ガスレーザによって穴径６０μｍのビア穴８２の加工を行った。次にデスミア処理を行った。デスミア条件は過マンガン酸ナトリウム濃度６０ｇ／ｌ、ＮａＯＨ濃度４５ｇ／ｌ、液温８０℃、処理時間２０分である。
Next, as shown in FIG. 3, the copper foil 9 on the surface was completely removed by etching.
The rough surface shape of the copper foil 9 is transferred to the surface of the glass epoxy resin insulating layer 8 from which the copper foil 9 has been completely removed.
Next, as shown in FIG. 4, a via hole 82 having a hole diameter of 60 μm was processed by a carbon dioxide laser. Next, desmear treatment was performed. The desmear conditions are a sodium permanganate concentration of 60 g / l, an NaOH concentration of 45 g / l, a liquid temperature of 80 ° C., and a treatment time of 20 minutes.
次にビア穴８２内壁面を含む積層基板１３０の全表面に無電解銅めっき用触媒であるアルカリシーダ処理を行った後、積層基板１３０の全表面に、厚さ０．４μｍの無電解銅めっきを施し、更に図５に示すように、厚さ２０μｍのビアフィリングタイプの電解銅めっきを行い、導体層１５及びビア配線部８３を形成した。
次に図６、図７に示すように、エッチング法によって最小配線幅が４５μｍの配線１３を形成し、多層プリント配線板１００を得た。
Next, the entire surface of the multilayer substrate 130 including the inner wall surface of the via hole 82 is subjected to alkali seeding treatment as an electroless copper plating catalyst, and then the entire surface of the multilayer substrate 130 is electroless copper plated with a thickness of 0.4 μm. Further, as shown in FIG. 5, via filling type electrolytic copper plating with a thickness of 20 μm was performed to form the conductor layer 15 and the via wiring portion 83.
Next, as shown in FIGS. 6 and 7, a wiring 13 having a minimum wiring width of 45 μm was formed by an etching method, and a multilayer printed wiring board 100 was obtained.
配線１３のピール強度は０．８５ｋＮ/ｍであった。
また、上記図４の条件のデスミア処理を行わなかった場合のピール強度は０．９２ｋＮ/ｍであった。
ピール強度の試験方法は、ＪＩＳ Ｃ６４８１である。
The peel strength of the wiring 13 was 0.85 kN / m.
Further, the peel strength when the desmear treatment under the condition of FIG. 4 was not performed was 0.92 kN / m.
The test method for peel strength is JIS C6481.
また、実施例１について、デスミア処理の処理時間を６分３０秒とし他は同じ条件として多層プリント配線板を作成し、この多層プリント配線板について、基板のはんだ耐熱性を評価するために、２６０℃の溶融はんだにフローとさせて表面の銅箔が剥離するまでの時間を測定した。その結果、１８００秒後でもめっき銅が膨れないことが確認された。
この時の試験片サイズは１００ｍｍ角であり、両面はめっき銅で被覆されたものを使用した。上記の特性結果を表１の「実施例１」欄にまとめて示した。
In Example 1, a multilayer printed wiring board was prepared under the same conditions except that the desmear processing time was 6 minutes and 30 seconds, and in order to evaluate the solder heat resistance of the substrate for this multilayer printed wiring board, 260 The time until the copper foil on the surface was peeled off was measured by allowing the molten solder at 0 ° C. to flow. As a result, it was confirmed that the plated copper did not swell even after 1800 seconds.
The test piece size at this time was 100 mm square, and both sides were coated with plated copper. The above characteristic results are summarized in the “Example 1” column of Table 1.
また上記のようにデスミア処理の処理時間を６分３０秒として作成した多層プリント配線板について、上述の工程にて形成した１０００個のビア穴について冷熱サイクル試験を行いシリーズ抵抗値を測定した。前記冷熱サイクル試験は−６５℃での維持時間３０分、１２５℃での維持時間３０分を１サイクルとして行い、冷熱サイクル試験の前後の抵抗測定値から抵抗変化率（増加率）を測定した。その結果、抵抗変化率は１０％以下であった。 Moreover, about the multilayer printed wiring board produced by setting the processing time of a desmear process as 6 minutes and 30 seconds as mentioned above, the thermal cycle test was done about 1000 via holes formed in the above-mentioned process, and the series resistance value was measured. The cooling / heating cycle test was performed with a maintenance time of −65 ° C. for 30 minutes and a maintenance time of 125 ° C. for 30 minutes as one cycle, and the resistance change rate (increase rate) was measured from resistance measurement values before and after the cooling / heating cycle test. As a result, the resistance change rate was 10% or less.
（実施例２）
ガラスエポキシ樹脂系絶縁層として日立化成工業株式会社製Ｅ−６７９ＦＧを用いた。このガラスエポキシ樹脂系絶縁層のデスミア処理による重量減少量は２．２ｇ/ｍ２であった。ガラスエポキシ樹脂系絶縁層の材質以外は、全て実施例１と同じ条件で行った。
このガラスエポキシ樹脂系絶縁層のデスミア処理を行わなかった場合のピール強度は０．９３ｋＮ/ｍであった。またデスミア処理後のピール強度は同じく０．９３ｋＮ/ｍであった。
実施例２について、デスミア処理の処理時間を６分３０秒とし他は同じ条件として多層プリント配線板を作成し、この多層プリント配線板について、実施例１と同様にはんだ耐熱性を調べた所、１８００秒後でも膨れが発生しなかった。この特性結果を表１の「実施例２」欄にまとめて示した。
(Example 2)
E-679FG manufactured by Hitachi Chemical Co., Ltd. was used as the glass epoxy resin insulating layer. The weight loss due to desmear treatment of this glass epoxy resin insulating layer was 2.2 g / m 2 . Except for the material of the glass epoxy resin insulating layer, all the conditions were the same as in Example 1.
The peel strength when this glass epoxy resin insulating layer was not desmeared was 0.93 kN / m. The peel strength after desmear treatment was 0.93 kN / m.
About Example 2, the processing time of the desmear process was 6 minutes and 30 seconds, and a multilayer printed wiring board was created under the same conditions, and the solder heat resistance was examined in the same manner as in Example 1 for this multilayer printed wiring board. No swelling occurred even after 1800 seconds. The characteristic results are collectively shown in the “Example 2” column of Table 1.
また、上記のようにデスミア処理の処理時間を６分３０秒として作成した多層プリント配線板について、上述の工程にて形成した１０００個のビア穴について冷熱サイクル試験を行いシリーズ抵抗値を測定した。前記冷熱サイクル試験は−６５℃での維持時間３０分、１２５℃での維持時間３０分を１サイクルとして行い、冷熱サイクル試験の前後の抵抗測定値から抵抗変化率（増加率）を測定した。その結果、抵抗変化率は１０％以下であった。 Moreover, about the multilayer printed wiring board produced by setting the processing time of a desmear process as 6 minutes and 30 seconds as mentioned above, the thermal cycle test was performed about 1000 via holes formed in the above-mentioned process, and the series resistance value was measured. The cooling / heating cycle test was performed with a maintenance time of −65 ° C. for 30 minutes and a maintenance time of 125 ° C. for 30 minutes as one cycle, and the resistance change rate (increase rate) was measured from resistance measurement values before and after the cooling / heating cycle test. As a result, the resistance change rate was 10% or less.
（比較例１）
ガラスエポキシ樹脂系絶縁層として日立化成工業株式会社製Ｅ−６７を用いた。このガラスエポキシ樹脂系絶縁層のデスミア処理による重量減少量は９．８ｇ/ｍ２であった。ガラスエポキシ樹脂系絶縁層の材質以外は、全て実施例１と同じ条件で行った。
このガラスエポキシ樹脂系絶縁層のデスミア処理を行わなかった場合のピール強度は０．９８ｋＮ/ｍであった。またデスミア処理後のピール強度は同じく０．７０ｋＮ/ｍであった。比較例１について、デスミア処理の処理時間を６分３０秒とし他は同じ条件として多層プリント配線板を作成し、この多層プリント配線板について、実施例１と同様にはんだ耐熱性を調べた所、２０秒後に膨れが発生した。この特性結果を表１の「比較例１」欄にまとめて示した。
(Comparative Example 1)
E-67 manufactured by Hitachi Chemical Co., Ltd. was used as the glass epoxy resin insulating layer. The weight loss due to desmearing of this glass epoxy resin insulating layer was 9.8 g / m 2 . Except for the material of the glass epoxy resin insulating layer, all the conditions were the same as in Example 1.
The peel strength when this glass epoxy resin insulating layer was not desmeared was 0.98 kN / m. The peel strength after desmear treatment was also 0.70 kN / m. About the comparative example 1, the processing time of the desmear process was made into 6 minutes and 30 seconds, and the multilayer printed wiring board was created on the same conditions as the others, and the solder heat resistance was examined in the same manner as in Example 1 for this multilayer printed wiring board. Swelling occurred after 20 seconds. The characteristic results are summarized in the “Comparative Example 1” column of Table 1.
（比較例２）
ガラスエポキシ樹脂系絶縁層として松下電工株式会社製Ｒ１５１５Ｂを用いた。このガラスエポキシ樹脂系絶縁層のデスミア処理による重量減少量は７．５ｇ/ｍ２であった。ガラスエポキシ樹脂系絶縁層の材質以外は、全て実施例１と同じ条件で行った。
このガラスエポキシ樹脂系絶縁層のデスミア処理を行わなかった場合のピール強度は０．７５ｋＮ/ｍであった。またデスミア処理後のピール強度は同じく０．４５ｋＮ/ｍであった。比較例２について、デスミア処理の処理時間を６分３０秒とし他は同じ条件として多層プリント配線板を作成し、この多層プリント配線板について、実施例１と同様にはんだ耐熱性を調べた所、２０秒後に膨れが発生した。この特性結果を表１の「比較例２」欄にまとめて示した。
(Comparative Example 2)
R1515B manufactured by Matsushita Electric Works, Ltd. was used as the glass epoxy resin insulating layer. The amount of weight loss due to the desmear treatment of this glass epoxy resin insulating layer was 7.5 g / m 2 . Except for the material of the glass epoxy resin insulating layer, all the conditions were the same as in Example 1.
The peel strength when this glass epoxy resin insulating layer was not desmeared was 0.75 kN / m. The peel strength after desmear treatment was also 0.45 kN / m. For Comparative Example 2, a multilayer printed wiring board was prepared under the same conditions except that the desmear treatment time was 6 minutes and 30 seconds, and for this multilayer printed wiring board, the solder heat resistance was examined in the same manner as in Example 1. Swelling occurred after 20 seconds. The characteristic results are summarized in the “Comparative Example 2” column of Table 1.
表１において、「ピール強度維持率」は、「デスミア無しピール強度（ｋＮ／ｍ）」をＡ、「デスミア後のピール強度（ｋＮ／ｍ）」をＢとしたときに、Ｂ／Ａ×１００で算出されるものである。
表１の結果から、実施例１、２は、いずれも、はんだ耐熱性及びピール強度維持率が、比較例１、２に比べて格段に高いことが明らかである。また、実施例１、２は、「デスミア後のピール強度（ｋＮ／ｍ）」自体が、比較例１、２に比べて高い数値となっている。
In Table 1, “peel strength maintenance ratio” is B / A × 100, where “peel strength without desmear (kN / m)” is A and “peel strength after desmear (kN / m)” is B. It is calculated by.
From the results shown in Table 1, it is clear that both Examples 1 and 2 have remarkably higher solder heat resistance and peel strength maintenance ratio than Comparative Examples 1 and 2. In Examples 1 and 2, “peel strength after desmear (kN / m)” itself is higher than those in Comparative Examples 1 and 2.
図１４、図１５は、実施例１にて採用したガラスエポキシ樹脂系絶縁層８（日立化成工業株式会社製Ｅ−６７９Ｆ）から銅箔９を除去した表面（外面８１）のＳＥＭ写真であり、図１４（ａ）、（ｂ）は外面８１に垂直の方向から撮影したもの、図１５（ａ）、（ｂ）は外面８１に対して４５度傾斜した方向から撮影したものである。図１４（ａ）、図１５（ａ）は、銅箔９を除去した後（デスミア処理前）、図１４（ｂ）、図１５（ｂ）は、実施例１に示す条件でデスミア処理を３回行った後の状態を示す。
図１６、図１７は、比較例１にて採用したガラスエポキシ樹脂系絶縁層（日立化成工業株式会社製Ｅ−６７）から銅箔９を除去した表面（外面８１）のＳＥＭ写真であり、図１６（ａ）、（ｂ）は外面８１に垂直の方向から撮影したもの、図１７（ａ）、（ｂ）は外面８１に対して４５度傾斜した方向から撮影したものである。図１６（ａ）、図１７（ａ）は、銅箔９を除去した後（デスミア処理前）、図１６（ｂ）、図１７（ｂ）は、実施例１に示す条件でデスミア処理を３回行った後の状態を示す。
14 and 15 are SEM photographs of the surface (outer surface 81) obtained by removing the copper foil 9 from the glass epoxy resin insulating layer 8 (E-679F manufactured by Hitachi Chemical Co., Ltd.) employed in Example 1. 14A and 14B are taken from a direction perpendicular to the outer surface 81, and FIGS. 15A and 15B are taken from a direction inclined 45 degrees with respect to the outer surface 81. FIG. 14 (a) and 15 (a) show the state after removing the copper foil 9 (before the desmear treatment), and FIG. 14 (b) and FIG. 15 (b) show the desmear treatment 3 under the conditions shown in the first embodiment. Shows the state after the trip.
16 and 17 are SEM photographs of the surface (outer surface 81) obtained by removing the copper foil 9 from the glass epoxy resin insulating layer (E-67 manufactured by Hitachi Chemical Co., Ltd.) employed in Comparative Example 1. 16 (a) and 16 (b) are taken from a direction perpendicular to the outer surface 81, and FIGS. 17 (a) and 17 (b) are taken from a direction inclined 45 degrees with respect to the outer surface 81. 16 (a) and 17 (a) show the state after removing the copper foil 9 (before the desmear treatment), and FIG. 16 (b) and FIG. 17 (b) show the desmear treatment 3 under the conditions shown in the first embodiment. Shows the state after the trip.
図１６（ａ）、（ｂ）、図１７（ａ）、（ｂ）を参照して判るように、比較例１にて採用したガラスエポキシ樹脂系絶縁層の場合は、デスミア処理を行うことで、表面の穴が拡げられ、表面の凹凸形状が変化する。
これに対して、図１４（ａ）、（ｂ）、図１５（ａ）、（ｂ）に示すように、実施例１にて採用したガラスエポキシ樹脂系絶縁層８は、デスミア処理の前後で表面形状に殆ど変化が見られない。この表面形状の安定性が、高いピール強度維持率の確保に寄与しているものと考えられる。
As can be seen with reference to FIGS. 16 (a), 16 (b), 17 (a) and 17 (b), in the case of the glass epoxy resin insulating layer employed in Comparative Example 1, the desmear treatment is performed. The hole on the surface is expanded, and the uneven shape on the surface changes.
In contrast, as shown in FIGS. 14 (a), 14 (b), 15 (a), and 15 (b), the glass epoxy resin insulating layer 8 employed in Example 1 is used before and after the desmear treatment. There is almost no change in the surface shape. It is considered that the stability of the surface shape contributes to securing a high peel strength maintenance rate.
（多層プリント配線板の製造方法の別態様）
本発明の多層プリント配線板の製造方法は通常のエッチング法よりも更に微細な配線の形成に有利なセミアディティブ法配線板にも適用が可能である。
図１８にその適用工程例を示す。
(Another aspect of the method for producing a multilayer printed wiring board)
The method for producing a multilayer printed wiring board of the present invention can also be applied to a semi-additive method wiring board that is more advantageous for forming finer wiring than a normal etching method.
FIG. 18 shows an example of the application process.
図２から図４のビア穴８２の加工までは既述の実施形態と同様の工程で加工する。次に、デスミア処理及び無電解銅めっき用アルカリシーダ処理を行った後、図１８（ａ）に示すように、無電解銅めっきを施す。
ここで形成される無電解銅めっき層１４の厚さは、０．１μｍ〜１．０μｍ、あるいはそれ以下であることが好ましく、例えば０．４μｍである。
The processing up to the processing of the via hole 82 in FIGS. 2 to 4 is performed in the same process as in the above-described embodiment. Next, after performing a desmear process and the alkali seeder process for electroless copper plating, as shown to Fig.18 (a), electroless copper plating is given.
The thickness of the electroless copper plating layer 14 formed here is preferably 0.1 μm to 1.0 μm or less, for example, 0.4 μm.
次に図１８（ｂ）に示すように、パターン電気めっき用レジスト１７（以下、単に電気めっき用レジストとも言う）を周知のフォト法で形成した後、ビアフィリングタイプの電気銅めっきを行い、絶縁樹脂層８の外面８１の無電解銅めっき層１４に電気めっき用レジスト１７によってパターン化された電気銅めっき層１２を積層するとともに、ビア穴８２内のビア配線部８３を形成する。 Next, as shown in FIG. 18B, after forming a pattern electroplating resist 17 (hereinafter also simply referred to as an electroplating resist) by a well-known photo method, via filling type electro copper plating is performed to insulate. The electrolytic copper plating layer 12 patterned with the electroplating resist 17 is laminated on the electroless copper plating layer 14 on the outer surface 81 of the resin layer 8, and the via wiring portion 83 in the via hole 82 is formed.
次に図１８（ｃ）に示すように電気めっき用レジスト１７を剥離し、この剥離によって露出した無電解銅めっき層１４をエッチング法（例えば、いわゆるクイックエッチング）で除去することによって配線１３を形成する。これにより多層プリント配線板１００が得られる。 Next, as shown in FIG. 18C, the electroplating resist 17 is stripped, and the electroless copper plating layer 14 exposed by the stripping is removed by an etching method (for example, so-called quick etching) to form the wiring 13. To do. Thereby, the multilayer printed wiring board 100 is obtained.
この製造方法によれば、電気めっき用レジスト１７の剥離によって露出した無電解銅めっき層１４のエッチングによって、配線１３のパターニングを行うので、図６、図７を参照して説明したように、絶縁樹脂層８の外面８１の無電解銅めっき層１４と電解銅めっき層１２とからなる導体層１５のエッチングによって配線１３のパターニングを行う方法に比べて、エッチングの精度を高めることができ、配線１３の最小幅、間隔を狭くことが容易である。
無電解銅めっき、電気銅めっき、配線１３のパターニングの手順以外は実施例１と条件を同じにして多層プリント配線板１００を試作した結果、配線１３の最小幅が２５μｍの配線１３を問題なく得ることができた。
According to this manufacturing method, since the wiring 13 is patterned by etching the electroless copper plating layer 14 exposed by peeling off the electroplating resist 17, as described with reference to FIGS. Compared with the method of patterning the wiring 13 by etching the conductor layer 15 composed of the electroless copper plating layer 14 and the electrolytic copper plating layer 12 on the outer surface 81 of the resin layer 8, the etching accuracy can be improved. It is easy to narrow the minimum width and interval.
As a result of trial manufacture of the multilayer printed wiring board 100 under the same conditions as in Example 1 except for the procedures of electroless copper plating, electrolytic copper plating, and wiring 13 patterning, the wiring 13 having a minimum width of 25 μm can be obtained without problems. I was able to.
なお、本発明では、上述の実施形態に限定されず、適宜変更可能であることは言うまでも無い。
内層コア基板１１０は、両面の銅箔２をエッチングによって完全に除去（図１（ｃ）参照）した後、樹脂基板１の表面（貫通穴４内面を含む）に無電解銅めっきのための触媒処理を行い、貫通穴４内面を含む全表面に無電解銅めっき（図１中図示略。図８中、符号５ａ参照）及び電気銅めっき５を施す（図１（ｄ）参照）が、無電解銅めっきのための触媒処理の前にデスミア処理を行っても良い。この場合、内層コア基板１１０の樹脂基板１としても、デスミア処理の処理条件が、過マンガン酸ナトリウム濃度６０ｇ／ｌ、ＮａＯＨ濃度４５ｇ／ｌ、液温８０℃、処理時間２０分において、重量減少量が１ｇ／ｍ２以上、５ｇ／ｍ２以下である樹脂材料（例えば、ガラスエポキシ樹脂）を採用することが好ましい。
In the present invention, it is needless to say that the present invention is not limited to the above-described embodiment and can be appropriately changed.
The inner layer core substrate 110 is a catalyst for electroless copper plating on the surface (including the inner surface of the through hole 4) of the resin substrate 1 after the copper foils 2 on both sides are completely removed by etching (see FIG. 1C). The entire surface including the inner surface of the through hole 4 is subjected to electroless copper plating (not shown in FIG. 1; refer to reference numeral 5a in FIG. 8) and electrolytic copper plating 5 (see FIG. 1 (d)). You may perform a desmear process before the catalyst process for electrolytic copper plating. In this case, even when the resin substrate 1 of the inner layer core substrate 110 is used, the desmear treatment conditions are such that the sodium permanganate concentration is 60 g / l, the NaOH concentration is 45 g / l, the liquid temperature is 80 ° C., and the treatment time is 20 minutes. Is preferably 1 g / m 2 or more and 5 g / m 2 or less.
１…樹脂基板（樹脂層）、２…銅箔、３…（銅箔の）粗面、４…貫通穴、５…電気銅めっき、５ａ…無電解銅めっき、６…配線、７…穴埋め樹脂、８、８Ａ…絶縁樹脂層、８１…外面、８２…ビア穴、８３…ビア配線部、９…銅箔、１０…（銅箔の）粗面、１２…電解銅めっき層、１３…配線パターン（配線）、１４…無電解銅めっき、１５…導体層、１６…エッチングレジスト、１７…パターン電気めっき用レジスト、１００…多層プリント配線板、１１０…内層コア基板、１１１…銅張積層板、１２０…銅箔付き積層基板、１３０…積層基板、１４０…多層プリント配線板。 DESCRIPTION OF SYMBOLS 1 ... Resin board | substrate (resin layer), 2 ... Copper foil, 3 ... Rough surface of (copper foil), 4 ... Through-hole, 5 ... Electro copper plating, 5a ... Electroless copper plating, 6 ... Wiring, 7 ... Filling resin 8, 8A ... insulating resin layer, 81 ... outer surface, 82 ... via hole, 83 ... via wiring part, 9 ... copper foil, 10 ... rough surface (of copper foil), 12 ... electrolytic copper plating layer, 13 ... wiring pattern (Wiring), 14 ... electroless copper plating, 15 ... conductor layer, 16 ... etching resist, 17 ... resist for pattern electroplating, 100 ... multilayer printed wiring board, 110 ... inner core substrate, 111 ... copper clad laminate, 120 ... Laminated substrate with copper foil, 130 ... Laminated substrate, 140 ... Multilayer printed wiring board.
Claims (9)
前記絶縁樹脂層として、その形成樹脂が前記デスミア処理にて過マンガン酸アルカリを含む液に溶解可能な樹脂材料のみであり、デスミア処理の処理条件が過マンガン酸ナトリウム濃度６０ｇ／ｌ、ＮａＯＨ濃度４５ｇ／ｌ、液温８０℃、処理時間２０分における重量減少量が１ｇ／ｍ２以上、５ｇ／ｍ２以下である絶縁樹脂層を用いることを特徴とする多層プリント配線板の製造方法。 A semi-cured insulating resin layer is layered on both sides or one side of the inner layer core substrate with wiring patterns formed on both sides or one side, and a copper foil roughened surface is further superimposed on the outside and pressed and heated. Then, after integrating the insulating resin layer and the copper foil cured by pressing and heating to the inner core substrate, the copper foil is removed by etching, thereby providing irregularities on the outer surface of the insulating resin layer. After forming the roughened laminate forming step and the roughened laminate forming step, a via hole reaching the wiring pattern of the inner core substrate from the outer surface of the insulating resin layer is processed, and permanganic acid is formed. A conductor layer forming step of forming a conductor by performing desmear treatment with an alkali-containing liquid, performing electroless copper plating catalyst treatment, and then performing electroless copper plating and electrolytic copper plating; The method for manufacturing a multilayer printed wiring board that,
As the insulating resin layer, the forming resin is only a resin material that can be dissolved in the liquid containing alkali permanganate by the desmear treatment, and the treatment conditions of the desmear treatment are sodium permanganate concentration 60 g / l, NaOH concentration 45 g. / L, a liquid temperature of 80 ° C., an insulating resin layer having a weight loss of 1 g / m 2 or more and 5 g / m 2 or less at a treatment time of 20 minutes is used.
前記パターニング工程の完了によって得られた多層プリント配線板を内層コア基板として機能させて、前記粗面化積層板形成工程と前記導体層形成工程とパターニング工程とを繰り返すことによって多層プリント配線板の層数を増やすことを特徴とする請求項１又は２記載の多層プリント配線板の製造方法。 After completion of the conductor layer forming step, performing a patterning step of patterning the conductor obtained in the conductor layer forming step to form a wiring pattern,
The multilayer printed wiring board obtained by completing the patterning process functions as an inner core substrate, and the layers of the multilayer printed wiring board are repeated by repeating the roughened laminated board forming process, the conductor layer forming process, and the patterning process. The method for producing a multilayer printed wiring board according to claim 1 or 2, wherein the number is increased.
前記配線パターンは、前記絶縁樹脂層の粗面とされている前記外面に形成されており、前記絶縁樹脂層は、その形成樹脂が前記デスミア処理にて過マンガン酸アルカリを含む液に溶解可能な樹脂材料のみであり、過マンガン酸ナトリウム濃度６０ｇ／ｌ、ＮａＯＨ濃度４５ｇ／ｌ、液温８０℃、処理時間２０分の処理条件でデスミア処理を行ったときの重量減少量が１ｇ／ｍ２以上、５ｇ／ｍ２以下以下であることを特徴とする多層プリント配線板。 An inner layer core substrate having a wiring pattern formed on both sides or one side, an insulating resin layer laminated on both sides or one side of the inner layer core substrate, and an outer surface opposite to the inner layer core substrate side of the insulating resin layer. Wiring patterns, and via wiring portions that reach the wiring pattern of the inner core board from the outer surface of the insulating resin layer,
The wiring pattern is formed on the outer surface which is a rough surface of the insulating resin layer, and the insulating resin layer is soluble in a liquid containing alkali permanganate by the desmear treatment. Resin material only, sodium permanganate concentration 60 g / l, NaOH concentration 45 g / l, liquid temperature 80 ° C., desmear treatment under treatment conditions of 20 minutes is 1 g / m 2 or more. A multilayer printed wiring board characterized by being 5 g / m 2 or less.
前記配線パターンを介して隣り合う絶縁樹脂層の内、前記内層コア基板から遠い側の絶縁樹脂層に、その外面から前記内層コア基板側の絶縁樹脂層の外面に形成された配線パターンに到達するビア配線部が形成されていることを特徴とする請求項７記載の多層プリント配線板。 A plurality of the insulating resin layers and a wiring pattern formed on the rough surface which is the outer surface opposite to the inner layer core substrate side of each insulating resin layer are laminated on both sides or one side of the inner layer core substrate,
Of the insulating resin layers adjacent to each other through the wiring pattern, the insulating resin layer far from the inner core substrate reaches the wiring pattern formed on the outer surface of the insulating resin layer on the inner core substrate side from the outer surface. The multilayer printed wiring board according to claim 7, wherein a via wiring portion is formed.
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| JP2015159177A (en) * | 2014-02-24 | 2015-09-03 | 住友ベークライト株式会社 | Resin substrate, metal clad laminated board, printed wiring board, and semiconductor device |
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