JP2009099782A5 - - Google Patents

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Publication number
JP2009099782A5
JP2009099782A5 JP2007270165A JP2007270165A JP2009099782A5 JP 2009099782 A5 JP2009099782 A5 JP 2009099782A5 JP 2007270165 A JP2007270165 A JP 2007270165A JP 2007270165 A JP2007270165 A JP 2007270165A JP 2009099782 A5 JP2009099782 A5 JP 2009099782A5
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JP
Japan
Prior art keywords
semiconductor chip
wiring pattern
stacked
semiconductor
sealing resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2007270165A
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English (en)
Japanese (ja)
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JP2009099782A (ja
JP5068133B2 (ja
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Priority to JP2007270165A priority Critical patent/JP5068133B2/ja
Priority claimed from JP2007270165A external-priority patent/JP5068133B2/ja
Publication of JP2009099782A publication Critical patent/JP2009099782A/ja
Publication of JP2009099782A5 publication Critical patent/JP2009099782A5/ja
Application granted granted Critical
Publication of JP5068133B2 publication Critical patent/JP5068133B2/ja
Active legal-status Critical Current
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JP2007270165A 2007-10-17 2007-10-17 半導体チップ積層構造体及び半導体装置 Active JP5068133B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007270165A JP5068133B2 (ja) 2007-10-17 2007-10-17 半導体チップ積層構造体及び半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007270165A JP5068133B2 (ja) 2007-10-17 2007-10-17 半導体チップ積層構造体及び半導体装置

Publications (3)

Publication Number Publication Date
JP2009099782A JP2009099782A (ja) 2009-05-07
JP2009099782A5 true JP2009099782A5 (pt) 2010-10-14
JP5068133B2 JP5068133B2 (ja) 2012-11-07

Family

ID=40702499

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007270165A Active JP5068133B2 (ja) 2007-10-17 2007-10-17 半導体チップ積層構造体及び半導体装置

Country Status (1)

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JP (1) JP5068133B2 (pt)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6290534B2 (ja) * 2012-12-20 2018-03-07 新光電気工業株式会社 半導体パッケージ及び半導体パッケージの製造方法
JP6318084B2 (ja) * 2014-12-17 2018-04-25 新光電気工業株式会社 半導体装置及びその製造方法
KR102628100B1 (ko) * 2021-12-28 2024-01-23 (주)심텍 내장된 칩을 구비하는 반도체 패키지 및 이의 제조 방법

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2910731B2 (ja) * 1997-06-16 1999-06-23 日本電気株式会社 半導体装置
JP2001177049A (ja) * 1999-12-20 2001-06-29 Toshiba Corp 半導体装置及びｉｃカード
JP2002057273A (ja) * 2000-08-07 2002-02-22 Orient Semiconductor Electronics Ltd 集積回路パッケージ用積み重ねダイセット
JP2003273317A (ja) * 2002-03-19 2003-09-26 Nec Electronics Corp 半導体装置及びその製造方法
JP4593951B2 (ja) * 2004-03-29 2010-12-08 ルネサスエレクトロニクス株式会社 マルチチップパッケージの製造方法
JP4865197B2 (ja) * 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP4819471B2 (ja) * 2005-10-12 2011-11-24 日本電気株式会社 配線基板及び配線基板を用いた半導体装置並びにその製造方法

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