JP2009099782A5 - - Google Patents

Claims (15)

A first semiconductor chip;
A wiring pattern electrically connected to the first semiconductor chip;
The first semiconductor chip is sealed so as to expose the second surface of the wiring pattern located on the opposite side of the first surface of the wiring pattern facing the first semiconductor chip. Sealing resin;
A semiconductor chip laminated structure comprising: a second semiconductor chip disposed to face the second surface of the wiring pattern and electrically connected to the wiring pattern. The second semiconductor chip is flip-chip connected to the wiring pattern,
A resin for bonding the second semiconductor chip, the wiring pattern, and the first sealing resin is provided between the second semiconductor chip, the wiring pattern, and the first sealing resin. The semiconductor chip laminated structure according to claim 1.   3. The semiconductor chip stacked structure according to claim 1, wherein the first semiconductor chip is flip-chip connected to the wiring pattern.   The through electrode connected to the wiring pattern is provided while penetrating the first sealing resin in a portion provided on the first surface of the wiring pattern. The semiconductor chip laminated structure according to any one of the above.   5. The semiconductor chip stacked structure according to claim 1, wherein an external connection terminal is provided at an end portion of the through electrode on the side opposite to the side connected to the wiring pattern. 6. body.   The opening part which exposes the 1st surface of the said wiring pattern was provided in the said 1st sealing resin of the part provided in the 1st surface of the said wiring pattern, The Claim 1 thru | or 3 characterized by the above-mentioned. Among them, the semiconductor chip laminated structure according to any one of the above. A plurality of semiconductor chip laminated structures according to any one of claims 1 to 6,
A semiconductor device comprising: a plurality of the semiconductor chip laminated structures stacked and arranged, and a conductive member that electrically connects the wiring patterns provided in the plurality of semiconductor chip laminated structures.   The conductive member is disposed between the wiring patterns provided in the two opposing semiconductor chip stacked structures so as to be in contact with the wiring patterns provided in the two opposing semiconductor chip stacked structures. The semiconductor device according to claim 7.   Two opposing semiconductor chip stacked structures are as follows:
  The second surface of the wiring pattern provided in each of the semiconductor chip stacked structures is arranged so that the second semiconductor chips provided in the respective semiconductor chip stacked structures are opposed to each other. 9. The semiconductor device according to claim 8, wherein each other is electrically connected by the conductive member. Two opposing semiconductor chip stacked structures are as follows:
The first semiconductor chip provided in one of the semiconductor chip laminated structures and the second semiconductor chip provided in another semiconductor chip laminated structure are arranged to face each other; and The first surface of the wiring pattern provided in one semiconductor chip stacked structure and the second surface of the wiring pattern provided in the other semiconductor chip stacked structure are formed by the conductive member. 9. The semiconductor device according to claim 8, wherein the semiconductor device is electrically connected . 11. The semiconductor chip stacked structure disposed in a lowermost layer among the stacked semiconductor chip stacked structures has the through electrode. 11 . Semiconductor device. A second sealing resin for sealing the stacked semiconductor chip stacked structures is provided so as to expose an end portion of the through electrode exposed from the first sealing resin. The semiconductor device according to claim 11 .   In the manufacturing method of the semiconductor chip laminated structure having the first semiconductor chip and the second semiconductor chip,
  Forming a wiring pattern on the upper surface of the conductive support;
  Connecting the first semiconductor chip and the wiring pattern;
  Sealing the wiring pattern and the first semiconductor chip with a sealing resin having an opening exposing a part of the wiring pattern;
  Removing the support;
  A method of manufacturing a semiconductor chip laminated structure, comprising: a second semiconductor chip connecting step of connecting the wiring pattern on the surface from which the support is removed and the second semiconductor chip.   14. The method of manufacturing a semiconductor chip laminated structure according to claim 13, further comprising a step of forming a through electrode in the opening.   A step of performing an electrical inspection of the first semiconductor chip by bringing a terminal of an inspection device into contact with a pad exposed from the sealing resin before the second semiconductor chip connection step. Item 15. A method for producing a semiconductor chip laminated structure according to Item 13 or 14.