JP2009094400A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2009094400A JP2009094400A JP2007265577A JP2007265577A JP2009094400A JP 2009094400 A JP2009094400 A JP 2009094400A JP 2007265577 A JP2007265577 A JP 2007265577A JP 2007265577 A JP2007265577 A JP 2007265577A JP 2009094400 A JP2009094400 A JP 2009094400A
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- Prior art keywords
- mounting
- package substrate
- semiconductor device
- chip
- resin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
【解決手段】パッケージ基板10の表面には、第1,第2の実装ランド11,12、ボンディングパッド13、及び、第1の実装ランド11とボンディングパッド13を接続する接続パターン14が形成されている。パッケージ基板10上に半導体チップ15が搭載されている。半導体チップ15とボンディングパッド13はワイヤ19により接続されている。第1,第2の実装ランド11,12上に半田を介してチップ部品17が搭載されている。これらは樹脂により封止されている。接続パターン14の一部はソルダーレジスト18で覆われている。第1,第2の実装ランド11,12とチップ部品17とパッケージ基板10で囲まれた領域に樹脂が充填されている。第2の実装ランド12には、ソルダーレジスト18に近接する部分に切り欠き42が形成されている。
【選択図】図1
Description
11 第1の実装ランド
12 第2の実装ランド
13 ボンディングパッド
14 接続パターン
15 半導体チップ
16 半田
17 チップ部品
18 ソルダーレジスト
19 金ワイヤ(ワイヤ)
20 樹脂
42 切り欠き
43 第1の辺
44 第2の辺
Claims (2)
- 第1,第2の実装ランド、ボンディングパッド、及び、前記第1の実装ランドと前記ボンディングパッドを接続する接続パターンが表面に形成されたパッケージ基板と、
前記パッケージ基板上に搭載された半導体チップと、
前記半導体チップと前記ボンディングパッドを接続するワイヤと、
前記第1,第2の実装ランド上に半田を介して搭載されたチップ部品と、
前記半導体チップ、前記ワイヤ及び前記チップ部品を封止する樹脂とを備え、
前記接続パターンの一部はソルダーレジストで覆われ、
前記第1,第2の実装ランドと前記チップ部品と前記パッケージ基板で囲まれた領域に前記樹脂が充填され、
前記第2の実装ランドには、前記ソルダーレジストに近接する部分に切り欠きが形成されていることを特徴とする半導体装置。 - 前記切り欠きは前記第2の実装ランドの第1の辺と第2の辺の間に形成され、
前記切り欠きの前記第1の辺に沿った幅と第2の辺に沿った幅は、それぞれ前記チップ部品と前記パッケージ基板の間隔よりも大きいことを特徴とする請求項1に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007265577A JP5098558B2 (ja) | 2007-10-11 | 2007-10-11 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007265577A JP5098558B2 (ja) | 2007-10-11 | 2007-10-11 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009094400A true JP2009094400A (ja) | 2009-04-30 |
JP5098558B2 JP5098558B2 (ja) | 2012-12-12 |
Family
ID=40666059
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007265577A Expired - Fee Related JP5098558B2 (ja) | 2007-10-11 | 2007-10-11 | 半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP5098558B2 (ja) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0265293A (ja) * | 1988-08-31 | 1990-03-05 | Toyo Commun Equip Co Ltd | 表面実装用プリント板のパターン |
JPH09252080A (ja) * | 1996-03-15 | 1997-09-22 | Mitsubishi Electric Corp | 高周波集積回路 |
-
2007
- 2007-10-11 JP JP2007265577A patent/JP5098558B2/ja not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0265293A (ja) * | 1988-08-31 | 1990-03-05 | Toyo Commun Equip Co Ltd | 表面実装用プリント板のパターン |
JPH09252080A (ja) * | 1996-03-15 | 1997-09-22 | Mitsubishi Electric Corp | 高周波集積回路 |
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JP5098558B2 (ja) | 2012-12-12 |
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