JP2009049361A - Stacked electronic part and method of manufacturing the same - Google Patents

Stacked electronic part and method of manufacturing the same Download PDF

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JP2009049361A
JP2009049361A JP2008068230A JP2008068230A JP2009049361A JP 2009049361 A JP2009049361 A JP 2009049361A JP 2008068230 A JP2008068230 A JP 2008068230A JP 2008068230 A JP2008068230 A JP 2008068230A JP 2009049361 A JP2009049361 A JP 2009049361A
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resin
plating
porous
element body
electrode
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JP5038950B2 (en
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Takashi Kajino
隆 楫野
Toshiyuki Abe
寿之 阿部
Akira Kakinuma
朗 柿沼
Kazuhiko Ito
和彦 伊藤
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TDK Corp
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Priority to TW97127669A priority patent/TWI395234B/en
Priority to EP08013190A priority patent/EP2019395B1/en
Priority to US12/219,519 priority patent/US8009012B2/en
Priority to KR1020080071795A priority patent/KR20090010929A/en
Priority to CN 200810215406 priority patent/CN101354935B/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a stacked electronic part that can sufficiently suppress plating deposition on the surface of a porous green body when a terminal electrode is formed on an external electrode, thereby enabling a decrease in the reliability of products to be prevented, and a method of manufacturing the same. <P>SOLUTION: The laminated electronic part 1 is a PTC thermistor having a stacked body 4 containing a porous green body 2 made of ceramics and having a plurality of vacancies and a plurality of internal electrodes 3 formed within the porous green body 2, and is provided with at least one unit structure 10 in which the porous green body 2 and the internal electrodes 3 are stacked. External electrode 5, 5 are connected to the internal electrode 2, and terminal electrodes 7, 7 are formed on the external electrode 5, 5 by plating. Resin is filled in a plurality of vacancies of the porous green body 2 at a filling ratio of not less than 60%. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、セラミックスからなる素体と内部電極の積層構造を備える積層電子部品およびその製造方法に関する。   The present invention relates to a laminated electronic component having a laminated structure of an element body made of ceramics and internal electrodes, and a method for manufacturing the same.

一般に、セラミックス素体、内部電極、および外部電極を有するサーミスタ、コンデンサ、インダクタ、LTCC(Low Temperature Co-fired Ceramics)、バリスタやそれらの複合体からなる積層電子部品は、プリント配線基板等の配線基板に搭載され、外部電極が所定の接続位置にはんだ付けされる。その際、例えばAgからなる外部電極(下地電極)上に、めっきによりNi層およびSn層からなる端子電極を形成したものを用いると、はんだによる基板への接合性が高められ、生産性を向上させ得る。   Generally, thermistors, capacitors, inductors, LTCCs (Low Temperature Co-fired Ceramics), varistors and their composites, which have ceramic bodies, internal electrodes and external electrodes, are printed circuit boards such as printed circuit boards. The external electrode is soldered to a predetermined connection position. In that case, for example, if the external electrode (base electrode) made of Ag and the terminal electrode made of Ni layer and Sn layer are formed by plating, the bondability to the substrate by solder is improved and the productivity is improved. Can be.

例えば、特許文献1には、かかる端子電極を形成するめっき工程において、めっき電解液が部品素体へ浸入してしまうことに起因して積層電子部品の電気特性が悪化してしまうことを防止すべく、電子部品のセラミック素体の表面部分に存在する全ての細孔に、シリコーン樹脂またはフェノール樹脂が含浸された電子部品が提案されている。   For example, Patent Document 1 discloses that in the plating process for forming such terminal electrodes, the electrical characteristics of the laminated electronic component are prevented from deteriorating due to the plating electrolyte entering the component element body. Therefore, an electronic component has been proposed in which all pores present on the surface portion of the ceramic body of the electronic component are impregnated with a silicone resin or a phenol resin.

特許第270097号公報Japanese Patent No. 270097

ところで、本発明者が、外部電極に端子電極がめっき形成された上記種々の積層電子部品の物性や電気特性について検討したところ、例えば、特にPTC(Positive Temperature Coefficient)サーミスタのような多孔質のセラッミク素体を有する積層電子部品では、素体の表面や表層部、さらには、素体の内部まで端子電極金属がめっきされることがあり、こうなると、外部電極間の絶縁特性の低下あるいは短絡が生じてしまい、ときには、めっきが内部電極にまで達してしまい、製品機能が失われるといった問題を生じ得ることが判明した。   By the way, the present inventor examined the physical properties and electrical characteristics of the above-mentioned various laminated electronic components in which terminal electrodes are plated on external electrodes. For example, a porous ceramic such as a PTC (Positive Temperature Coefficient) thermistor is used. In a multilayer electronic component having an element body, the terminal electrode metal may be plated up to the surface of the element body, the surface layer portion, and even the inside of the element body. It has been found that, sometimes, the plating reaches the internal electrodes, which can cause problems such as loss of product function.

具体的には、PTCサーミスタの両端に外部電極(下地電極)を形成し、ベレルめっきによる電気めっきでNi/Sn端子電極の形成を行なったところ、セラミック素体の全面にめっきが付着した。この素体断面のNi及びSnの元素分布をEPMA(Electron-Probe Microanalyzer)で検査した結果、表層部に大量のNiが付着しており、更に深い部位にもNiが付着していることが判明した。このことから、内部電極に達するような開孔(オープンポア)の内部にめっき液が浸入し、内部電極から給電されることにより、めっきが素体内部から付着・成長していくものと推定される。このような素体へのめっき付着現象は、触媒を用いた無電解めっき、および、触媒を用いずに接触法で無電解めっきを開始する場合にも、同様に見られ、この場合にも、内部電極に達するような開孔(オープンポア)の内部から、めっきが付着・成長していくものと推定される。これに対し、上記特許文献1に開示された従来の方法を用いて、セラミック素体の全面にシリコーン樹脂を含浸したところ、樹脂の含浸条件によっては、セラミック素体へのめっきの付着を十分に抑制できないことが確認された。   Specifically, external electrodes (underlying electrodes) were formed on both ends of the PTC thermistor, and Ni / Sn terminal electrodes were formed by electroplating with bereel plating. As a result, plating adhered to the entire surface of the ceramic body. As a result of inspecting the elemental distribution of Ni and Sn in the element cross section with EPMA (Electron-Probe Microanalyzer), it was found that a large amount of Ni adhered to the surface layer and Ni also adhered to a deeper part. did. From this, it is estimated that the plating solution infiltrates into the open holes that reach the internal electrodes and power is supplied from the internal electrodes, so that the plating adheres and grows from inside the element body. The Such plating adhesion phenomenon to the element body is similarly seen when electroless plating using a catalyst and when electroless plating is started by a contact method without using a catalyst. It is estimated that the plating adheres and grows from the inside of the opening (open pore) that reaches the internal electrode. On the other hand, when the entire surface of the ceramic body is impregnated with a silicone resin using the conventional method disclosed in Patent Document 1, depending on the resin impregnation conditions, the adhesion of the plating to the ceramic body is sufficiently performed. It was confirmed that it cannot be suppressed.

そこで、本発明はかかる事情に鑑みてなされたものであり、外部電極上にめっきにより端子電極が形成される場合でも、セラミックスからなる多孔質素体の表面へのめっき付着を十分に抑止でき、これにより、製品の信頼性低下を防止することが可能な積層電子部品およびその製造方法を提供することを目的とする。   Therefore, the present invention has been made in view of such circumstances, and even when a terminal electrode is formed by plating on an external electrode, plating adhesion to the surface of a porous body made of ceramics can be sufficiently suppressed. Accordingly, an object of the present invention is to provide a multilayer electronic component capable of preventing a decrease in product reliability and a method for manufacturing the same.

本発明者は、上記課題を解決すべく、積層電子部品の多孔質セラミック素体の表面にめっき付着が生じ得る素体材料の物性やそのときの条件と、その素体の空孔に樹脂を含浸させたときの樹脂の充填率との関係に着目し、鋭意研究を進めた結果、本発明を完成するに至った。すなわち、本発明による積層電子部品は、主としてセラミックスからなり、かつ、複数の空孔を含む多孔質素体(多孔質セラミック素体)と、その多孔質素体内に設けられた少なくとも1つの内部電極とを有する積層体と、内部電極に接続された外部電極と、外部電極上にめっきにより形成された端子電極とを備えるものであり、多孔質素体は、複数の空孔に樹脂が60%以上の充填率で充填されたものである。   In order to solve the above-mentioned problems, the present inventor has made physical properties of the element material that can cause plating adhesion on the surface of the porous ceramic element of the multilayer electronic component, conditions at that time, and resin in the pores of the element. Focusing on the relationship with the resin filling rate when impregnated, the present invention was completed as a result of diligent research. That is, the multilayer electronic component according to the present invention includes a porous element body (porous ceramic element body) mainly made of ceramics and including a plurality of pores, and at least one internal electrode provided in the porous element body. The porous body includes a plurality of pores filled with resin of 60% or more, and a laminated body having an external electrode connected to the internal electrode and a terminal electrode formed by plating on the external electrode. Filled at a rate.

なお、本発明における多孔質素体に含まれる「空孔」とは、日本工業規格JIS Z2500および同2501に規定される「気孔」と同等のものである。また、多孔質素体における樹脂の「充填率」とは、以下のとおり測定される値である。すなわち、まず、端子電極がめっきで形成される前の状態の積層電子部品を大気圧下150℃で1時間乾燥して水分を蒸発させたものの重量を測定する(重量m1)。次に、その積層電子部品を水中に浸漬させた状態で真空中30分間保持することにより、空孔内に水を含浸させたものの重量を測定する(重量m2)。さらに、その積層電子部品を大気圧下200℃で1時間乾燥した後、外部電極に樹脂が付着しないように、多孔質素体に未硬化の樹脂(重合性のものの場合はモノマー)を含浸させ、その樹脂を乾燥硬化(加熱硬化、重合)させたものの重量を測定する(重量m3)。そして、下記式(1);
充填率(%)=100×(m3−m1)/{(m2−m1)×ρ} …(1)、
で表される関係式に上記重量m1,m2,m3、および樹脂の乾燥硬化状態での密度ρを代入し、樹脂の「充填率」を算出する。
The “pores” contained in the porous element body in the present invention are equivalent to “pores” defined in Japanese Industrial Standards JIS Z2500 and 2501. The “filling rate” of the resin in the porous element body is a value measured as follows. That is, first, the weight of the laminated electronic component in a state before the terminal electrode is formed by plating is dried at 150 ° C. for 1 hour under atmospheric pressure to evaporate the moisture (weight m1). Next, the weight of the impregnated water is measured by holding the laminated electronic component in a state of being immersed in water for 30 minutes in a vacuum (weight m2). Further, after drying the laminated electronic component at 200 ° C. for 1 hour under atmospheric pressure, the porous body is impregnated with an uncured resin (a monomer in the case of a polymerizable material) so that the resin does not adhere to the external electrode, The weight of the resin obtained by drying and curing (heat curing, polymerization) is measured (weight m3). And the following formula (1);
Filling rate (%) = 100 × (m3−m1) / {(m2−m1) × ρ} (1),
Substituting the weights m1, m2, and m3 and the density ρ of the resin in the dry and cured state into the relational expression represented by

このように構成された積層電子部品においては、多孔質素体の空孔に樹脂が充填されており、多孔質素体に開口した空孔(開孔:オープンポア)が樹脂によって閉塞されるので、外部電極上にめっきにより端子電極を形成するときに、そのような開孔からめっき液が多孔質素体の内部へ浸入することにより内部電極にめっき液が到達してめっきが付着・成長することが抑制される。そして、本発明者の知見によれば、その樹脂の充填率が60%以上であると、多孔質素体の表面へのめっき付着率(露出面積に対するめっき付着面積の割合)が略5%以下となるように十分に低く抑えられることが確認された。なお、多孔質素体の露出面上、好ましくはそのほぼ全体に樹脂層が形成されていると、そのバリア効果が一層高められるので好適である。   In the multilayer electronic component configured in this way, the pores of the porous body are filled with resin, and the pores (open pores) opened in the porous body are closed by the resin. When forming a terminal electrode on the electrode by plating, the plating solution enters the inside of the porous body through such openings, thereby preventing the plating solution from reaching the internal electrode and depositing / growing the plating. Is done. According to the knowledge of the present inventor, when the filling rate of the resin is 60% or more, the plating adhesion rate (ratio of the plating adhesion area to the exposed area) on the surface of the porous element body is approximately 5% or less. It was confirmed that it was kept low enough. In addition, it is preferable that the resin layer is formed on the exposed surface of the porous element body, preferably almost entirely, since the barrier effect is further enhanced.

また、上記特許文献1に開示された従来と同様の方法を用いて得られたPTCサーミスタが、リフローなどの加熱処理に供されたり、実装時の加熱や作動時のヒートアップなどによって高温環境に曝されたりした場合、樹脂の含浸条件によっては、高温での抵抗値が有意に低下するといったPTC特性の不良が生じ得ることが確認された。これは、おそらく、PTCサーミスタなどの電子部品のはんだ付けに使用されるフラックスが、加熱時に多孔質素体の開孔内部に流入し、その残留フラックスによってセラミックス製の素体が還元されてしまうことによるものと推測される。   In addition, the PTC thermistor obtained by using the same method as that disclosed in the above-mentioned Patent Document 1 is subjected to a heat treatment such as reflow, or is heated to a high temperature environment by heating during mounting or heat up during operation. It has been confirmed that when exposed, the PTC characteristics may be deteriorated depending on the impregnation conditions of the resin, such that the resistance value at a high temperature is significantly reduced. This is probably because the flux used for soldering electronic components such as PTC thermistors flows into the pores of the porous body during heating, and the ceramic body is reduced by the residual flux. Presumed to be.

これに対し、本発明による積層電子部品では、かかるPTC特性不良の発生も有意に抑制できることが確認され、特に、多孔質素体における樹脂の充填率が70%以上であると、積層電子部品を配線基板などに実装する際の、あるいは、その後に、フラックスが多孔質素体の内部へ流入することが十分に抑制され、特性不良の発生割合(頻度)を格段に低下させることができることが判明した。   On the other hand, in the multilayer electronic component according to the present invention, it has been confirmed that the occurrence of such a PTC characteristic defect can be significantly suppressed. In particular, when the filling rate of the resin in the porous body is 70% or more, the multilayer electronic component is wired. It has been found that the flux can be sufficiently prevented from flowing into the porous body during or after mounting on a substrate or the like, and the occurrence rate (frequency) of characteristic defects can be significantly reduced.

さらに、上記従来方法を用いて得られたPTCサーミスタの温度特性の評価を行ったところ、樹脂の含浸条件によっては、セラッミク素体から発泡(いわゆる「爆ぜ」)を生じる個体が有意量発生することも確認された。これは、従来の方法では、セラミック素体の表面の細孔が閉塞されるものの、素体内部に空孔が残存することにより、高温に曝されたときに、空孔内部の空気が膨張し破裂することによって引き起こされるものと推定される。   Furthermore, when the temperature characteristics of the PTC thermistor obtained by using the above conventional method were evaluated, depending on the resin impregnation conditions, a significant amount of individuals that generate foam (so-called “explosion”) from the ceramic body was generated. Was also confirmed. In the conventional method, although the pores on the surface of the ceramic body are blocked, the air inside the pores expands when exposed to high temperatures due to the remaining pores inside the body. Presumed to be caused by rupture.

これに対し、本発明による積層電子部品では、そのような「爆ぜ」の発生をも有効に抑制できることが確認され、殊に、多孔質素体における樹脂の充填率が80%以上であると、「爆ぜ」の発生割合(頻度)を格別に低減できることも判明した。   On the other hand, in the multilayer electronic component according to the present invention, it has been confirmed that the occurrence of such “explosion” can be effectively suppressed, and in particular, when the filling rate of the resin in the porous body is 80% or more, “ It was also found that the occurrence rate (frequency) of “explosion” can be significantly reduced.

また、多孔質素体が焼成されたもの(焼結体)であり、その焼結密度(実測密度/理論密度×100%)が90%以下のものである場合に、本発明は更に有用である。すなわち、本発明者の研究によれば、多孔質素体として、焼結密度が90%を超えるものを用いた場合には、端子電極のめっき形成時に多孔質素体の表面にめっきの付着がほとんど認められず、焼結密度が90%以下であると、焼結密度の低下に伴って、多孔質素体の表面へのめっきの付着率が急激に増大することが確認された。これは、多孔質素体の焼結密度が90%を超えると開孔(オープンポア)がほとんど生じることがなく、空孔が生成したとしても多くが閉孔(クローズドポア)であってめっき液が浸入しないのに対し、その焼結密度が90%以下になると、開孔の数量および全空孔に対する割合が急増することによるものと推測される。よって、そのような多量の開孔が形成され得る焼結密度90%以下の多孔質素体を備える積層電子部品に適用したときに、本発明の作用効果が一層好適に実現される。   Further, the present invention is further useful when the porous body is fired (sintered body) and the sintered density (measured density / theoretical density × 100%) is 90% or less. . That is, according to the research of the present inventors, when a porous element having a sintered density exceeding 90% is used, the adhesion of plating to the surface of the porous element is almost recognized at the time of forming the terminal electrode. In other words, it was confirmed that when the sintered density was 90% or less, the adhesion rate of plating to the surface of the porous element body rapidly increased as the sintered density decreased. This is because when the sintered density of the porous element body exceeds 90%, almost no open pores are generated, and even if voids are formed, many are closed pores and the plating solution is Although it does not penetrate, when the sintered density becomes 90% or less, it is presumed that the number of holes and the ratio to all the holes rapidly increase. Therefore, when applied to a laminated electronic component including a porous element body having a sintered density of 90% or less in which such a large amount of openings can be formed, the operational effects of the present invention are more suitably realized.

また、外部電極を被覆するオーバーコート層を更に有すると、外部電極の表面に端子電極をめっきするときに、めっき液による外部電極の腐食を確実に防止することができるので好適である。   In addition, it is preferable to further include an overcoat layer that covers the external electrode, because when the terminal electrode is plated on the surface of the external electrode, corrosion of the external electrode by the plating solution can be surely prevented.

さらに、本発明による積層電子部品の製造方法は、本発明の積層電子部品を有効に製造するための方法であって、主としてセラミックスからなり、かつ、複数の空孔を含む多孔質素体内に、少なくとも1つの内部電極を設けて積層構造体を形成する工程と、積層構造体を焼成して積層体(焼結体)を形成する工程と、導電性ペーストを、積層体の内部電極と電気的に接続するように、積層体に塗布する工程と、導電性ペーストを焼成して外部電極を形成する工程と、多孔質素体に樹脂を含浸させて、複数の空孔に樹脂を、60%以上、好ましくは70%以上、より好ましくは80%以上の充填率で充填する工程と、外部電極上にめっきにより端子電極を形成する工程とを有する。   Furthermore, the method for manufacturing a multilayer electronic component according to the present invention is a method for effectively manufacturing the multilayer electronic component according to the present invention, which is mainly made of ceramics and includes at least a porous body including a plurality of pores. A step of forming a laminated structure by providing one internal electrode, a step of firing the laminated structure to form a laminated body (sintered body), and electrically connecting the conductive paste to the internal electrode of the laminated body A step of applying to the laminate so as to connect, a step of baking the conductive paste to form the external electrode, and impregnating the porous body with a resin, the resin in a plurality of pores, 60% or more, Preferably, the method includes a step of filling at a filling rate of 70% or more, more preferably 80% or more, and a step of forming a terminal electrode on the external electrode by plating.

本発明の積層電子部品およびその製造方法によれば、多孔質素体に含まれる複数の空孔が、60%以上の充填率で樹脂によって充填されているので、端子電極をめっきで形成しても、多孔質素体の開孔からめっき液が浸入して内部電極まで流入することが抑制され、よって、多孔質素体へのめっきの付着が十分に抑止されるので、製品の信頼性が低下してしまうといった不都合を解消することができ、また、高温が印加されたときの特性不良の発生や高温下での「爆ぜ」の発生をも有効に防止することができる。   According to the multilayer electronic component and the method for manufacturing the same according to the present invention, since the plurality of pores included in the porous element body are filled with the resin at a filling rate of 60% or more, the terminal electrode can be formed by plating. , It is possible to prevent the plating solution from entering through the pores of the porous element body and flowing into the internal electrode, thereby sufficiently suppressing the adhesion of the plating to the porous element body, thereby reducing the reliability of the product. In addition, it is possible to eliminate inconveniences such as the occurrence of a characteristic failure when a high temperature is applied and the occurrence of “explosion” at a high temperature.

以下、本発明の実施の形態について、図面を参照して説明する。なお、図面中、同一の要素には同一の符号を付し、重複する説明を省略する。また、上下左右等の位置関係は、特に断らない限り、図面に示す位置関係に基づくものとする。さらに、図面の寸法比率は、図示の比率に限定されるものではない。また、以下の実施の形態は、本発明を説明するための例示であり、本発明をその実施の形態のみに限定する趣旨ではない。さらに、本発明は、その要旨を逸脱しない限り、さまざまな変形が可能である。   Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. Further, the positional relationship such as up, down, left and right is based on the positional relationship shown in the drawings unless otherwise specified. Furthermore, the dimensional ratios in the drawings are not limited to the illustrated ratios. Further, the following embodiments are exemplifications for explaining the present invention, and are not intended to limit the present invention only to the embodiments. Further, the present invention can be variously modified without departing from the gist thereof.

<第1実施形態>
図1は、本発明による積層電子部品の第1実施形態の概略構造を示す断面図である。積層電子部品1は、セラミックスからなり複数の空孔を有する多孔質素体2と、多孔質素体2内に形成された複数の内部電極3とを含む積層体4を有するPTCサーミスタであり、換言すれば、多孔質素体2と内部電極3が積層された単位構造10を少なくとも1つ備えたものである。より具体的には、積層体4の一方の側面に露出した端部を有する内部電極3と、積層体4の他方の側面に露出した端部を有する内部電極3とが交互に積層されている。
<First Embodiment>
FIG. 1 is a sectional view showing a schematic structure of a first embodiment of a multilayer electronic component according to the present invention. The multilayer electronic component 1 is a PTC thermistor having a multilayer body 4 including a porous element body 2 made of ceramics and having a plurality of pores, and a plurality of internal electrodes 3 formed in the porous element body 2. For example, at least one unit structure 10 in which the porous body 2 and the internal electrode 3 are laminated is provided. More specifically, the internal electrodes 3 having end portions exposed on one side surface of the multilayer body 4 and the internal electrodes 3 having end portions exposed on the other side surface of the multilayer body 4 are alternately stacked. .

積層体4の両側面には、それらの側面を覆うように外部電極5,5が設けられており、各外部電極5は、積層体4の一方の側面から露出した内部電極3の群、あるいは積層体4の他方の面から露出した内部電極3の群に電気的に接続されている。   External electrodes 5 and 5 are provided on both side surfaces of the laminate 4 so as to cover the side surfaces, and each external electrode 5 is a group of internal electrodes 3 exposed from one side surface of the laminate 4 or It is electrically connected to the group of internal electrodes 3 exposed from the other surface of the laminate 4.

さらに、外部電極5,5の外側には、めっきにより端子電極7,7が形成されている。これらの端子電極7,7と、例えば、配線基板(図示せず)上の電極とがはんだ等により接合される。各端子電極7は、例えば、外部電極5側から積層形成されたNi層7aおよびSn層7bを含む2層構造を有する。Ni層7aは、Sn層7bと外部電極5との接触を防止して、Snによる外部電極5の腐食を防止するバリアメタルとして機能するものであり、その厚さは例えば2μm程度である。また、Sn層7bは、はんだの濡れ性を向上させる機能を有するものであり、その厚さは例えば4μm程度とされる。   Further, terminal electrodes 7 and 7 are formed on the outside of the external electrodes 5 and 5 by plating. These terminal electrodes 7 and 7 are joined to, for example, electrodes on a wiring board (not shown) by solder or the like. Each terminal electrode 7 has, for example, a two-layer structure including a Ni layer 7a and a Sn layer 7b that are stacked from the external electrode 5 side. The Ni layer 7a functions as a barrier metal which prevents the Sn layer 7b and the external electrode 5 from contacting each other and prevents corrosion of the external electrode 5 due to Sn, and has a thickness of about 2 μm, for example. Further, the Sn layer 7b has a function of improving the wettability of the solder, and the thickness thereof is, for example, about 4 μm.

本実施形態のように積層電子部品1としてPTCサーミスタを作製する場合には、先述のとおり、多孔質素体2はセラミックス、具体的には、半導体セラミックスからなる必要があり、より具体的には、例えば、チタン酸バリウム系セラミックスからなるものである。このチタン酸バリウム系セラミックスにおいて、必要に応じて、Baの一部をCa、Sr、Pbなどで置換しても、あるいは、Tiの一部をSn、Zrなどで置換してもよい。また、チタン酸バリウム系半導体セラミックスを得るために添加するドナー元素としては、La、Y、Sm、Ce、Dy、Gd等の希土類元素や、Nb、Ta、Bi、Sb、W等の遷移元素を用いることができる。さらにかかるチタン酸バリウム系半導体セラミックスに、必要に応じてSiO2やMn等を適宜添加して用いてもよい。 When a PTC thermistor is manufactured as the multilayer electronic component 1 as in the present embodiment, the porous element body 2 needs to be made of ceramics, specifically, semiconductor ceramics as described above, and more specifically, For example, it is made of a barium titanate ceramic. In this barium titanate ceramic, part of Ba may be replaced with Ca, Sr, Pb, or the like, or part of Ti may be replaced with Sn, Zr, or the like as necessary. As donor elements to be added to obtain barium titanate semiconductor ceramics, rare earth elements such as La, Y, Sm, Ce, Dy, and Gd, and transition elements such as Nb, Ta, Bi, Sb, and W are used. Can be used. Further, if necessary, SiO 2 , Mn or the like may be added to the barium titanate semiconductor ceramics.

このように多孔質素体2をチタン酸バリウム系半導体セラミックスで形成することにより、キュリー温度で電気抵抗が急上昇するというPTCサーミスタの特性(PTC特性)が良好に得られる。このようなPTCサーミスタの用途としては、過電流保護、定温度発熱体、過熱検知などが挙げられる。   Thus, by forming the porous element body 2 of barium titanate semiconductor ceramics, the PTC thermistor characteristic (PTC characteristic) that the electric resistance rapidly increases at the Curie temperature can be obtained satisfactorily. Applications of such PTC thermistors include overcurrent protection, constant temperature heating elements, overheat detection and the like.

多孔質素体2を形成するために用いられるチタン酸バリウム系セラミックス粉末の合成方法としては、特に限定されるものではないが、例えば、水熱法、加水分解法、共沈法、固相法、ゾルゲル法等を用いることができ、必要に応じて仮焼が施されてもよい。   The method for synthesizing the barium titanate-based ceramic powder used to form the porous element body 2 is not particularly limited. For example, a hydrothermal method, a hydrolysis method, a coprecipitation method, a solid phase method, A sol-gel method or the like can be used, and calcining may be performed as necessary.

また、多孔質素体2は、複数の空孔に樹脂が60%以上、好ましくは70%以上、より好ましくは80%以上の充填率で充填されたものである。この樹脂の充填率が60%以上であると、端子電極7をめっきで形成する際に、多孔質素体2に含まれる開孔(オープンポア)からめっき液が多孔質素体2の内部へ浸入することにより内部電極にめっき液が到達してめっきが付着・成長してしまうことを十分に抑制できる。さらに、多孔質素体2への樹脂の充填率が70%以上であると、積層電子部品1の実装時などに懸念されるフラックスの多孔質素体内への流入・残留に起因する特性不良の発生割合を格段に低下させることができ、特に、樹脂の充填率が80%以上となると、積層電子部品1が高温に曝されたときに、空孔内部の空気が膨張し破裂することによって引き起こされるおそれがある「爆ぜ」の発生を格別に低く抑えることができる。   Further, the porous element body 2 is formed by filling a plurality of pores with a resin at a filling rate of 60% or more, preferably 70% or more, more preferably 80% or more. When the filling ratio of the resin is 60% or more, when the terminal electrode 7 is formed by plating, the plating solution enters the inside of the porous element body 2 from the openings (open pores) included in the porous element body 2. As a result, it is possible to sufficiently prevent the plating solution from reaching the internal electrode and causing the plating to adhere and grow. Further, when the filling rate of the resin in the porous element body 70 is 70% or more, the occurrence ratio of characteristic defects due to the inflow / residue of the flux into the porous element, which is a concern when mounting the laminated electronic component 1 or the like In particular, when the filling rate of the resin is 80% or more, when the laminated electronic component 1 is exposed to a high temperature, the air inside the pores may expand and burst. It is possible to keep the occurrence of “explosion” extremely low.

また、多孔質素体2は、その露出面上、好ましくはそのほぼ全体に樹脂層が形成されていると、そのバリア効果が一層高められるので好適である。なお、多孔質素体2表面の樹脂層による被覆率は、ハンドリング上に特に不都合がなければ、より高い方が開孔(オープンポア)へのめっき液の浸入が防げられるので好適である。   In addition, it is preferable that the porous element body 2 has a resin layer formed on the exposed surface, preferably substantially the entire surface, because the barrier effect is further enhanced. In addition, the coverage with the resin layer on the surface of the porous element body 2 is preferably higher if the handling is not particularly inconvenient because the plating solution can be prevented from entering the opening (open pore).

ここで、図2は、樹脂が60%以上の充填率で充填された多孔質素体2の実物の一例の表層断面を示す拡大写真である。多孔質素体2の内部には複数の空孔が形成されており、多くの開孔は内部空孔と連通していることが確認され、図示の如く、それらが樹脂で充填されるとともに、多孔質素体2の表面上に樹脂層が形成されていることがわかる。   Here, FIG. 2 is an enlarged photograph showing a surface layer cross section of an example of a real porous element body 2 filled with a resin at a filling rate of 60% or more. A plurality of pores are formed inside the porous element body 2, and it is confirmed that many apertures communicate with the internal pores. It can be seen that a resin layer is formed on the surface of the element body 2.

多孔質素体2の空孔充填に用いられる樹脂の種類は、特に制限されるものではなく、多孔質素体2に含浸させることができ、その後硬化させることができるものであれば、モノマー、ポリマー、およびプレポリマー(オリゴマー)のいずれでもよく、含浸後の重合反応によって硬化する樹脂の場合、例えば、好ましくは、エポキシ系樹脂、フェノール系樹脂、付加重合型(付加重合反応性)のシリコーン系樹脂が挙げられ、これらのなかでも、付加重合型のものを用いるとより好ましい。付加重合型の樹脂を得るためのモノマーとしては、不飽和反応基を有するもの、特に好ましくは、(メタ)アクリロイル基、ビニル基、または、それらの誘導基を有するものが挙げられる。   The type of the resin used for filling the pores of the porous element body 2 is not particularly limited, and can be a monomer, polymer, or the like as long as it can be impregnated into the porous element body 2 and then cured. In the case of a resin that is cured by a polymerization reaction after impregnation, for example, an epoxy resin, a phenol resin, or an addition polymerization type (addition polymerization reactivity) silicone resin is preferably used. Among these, it is more preferable to use an addition polymerization type. Monomers for obtaining addition polymerization type resins include those having an unsaturated reactive group, particularly preferably those having a (meth) acryloyl group, a vinyl group, or a derivative group thereof.

樹脂として脱水縮合型のものを用いると、重合時に反応生成物として水が生じ、多孔質素体2の空孔の内部からその水が放出されることにより空隙が生起され得るのに対し、付加重合型の樹脂を用いると、重合硬化時に水を生じないので、空隙の発生を抑え、脱水縮合型の樹脂を用いる場合に比して多孔質素体2の空孔の充填率をより高めることができる。   When a dehydration-condensation type resin is used, water is generated as a reaction product during the polymerization, and voids can be generated by releasing the water from the pores of the porous element body 2 whereas addition polymerization is performed. When the type resin is used, water is not generated at the time of polymerization and curing, so that generation of voids can be suppressed and the filling rate of the pores of the porous element body 2 can be further increased as compared with the case of using a dehydration condensation type resin. .

また、多孔質素体2は焼結体であり、その焼結密度は特に制限されないが、焼結密度が90%以下のものである場合に、上述した樹脂充填による効果が顕著に発現される。すなわち、多孔質素体2の焼結密度が90%を超える場合には、端子電極7のめっき形成時に多孔質素体2の表面に付着するめっきは有意量ではないのに対し、焼結密度が90%以下になると、焼結密度の低下につれて、多孔質素体2の開孔の量および割合が増大することに起因して、多孔質素体2の表面へのめっきの付着率が急増する傾向にある。したがって、多孔質素体2が、かかる多量の開孔が形成され得る焼結密度90%以下のものである場合、その開孔が樹脂で充填されるので、多孔質素体2の表面へのめっき付着を効果的に抑止できる。   The porous body 2 is a sintered body, and the sintered density is not particularly limited. However, when the sintered density is 90% or less, the above-described effects due to the resin filling are remarkably exhibited. That is, when the sintered density of the porous element body 2 exceeds 90%, the amount of plating attached to the surface of the porous element body 2 when the terminal electrode 7 is plated is not significant, whereas the sintered density is 90%. When the ratio is less than or equal to%, the amount and ratio of the pores of the porous element body 2 increase as the sintered density decreases, and the adhesion rate of plating to the surface of the porous element body 2 tends to increase rapidly. . Therefore, when the porous element body 2 has a sintered density of 90% or less at which such a large amount of openings can be formed, the openings are filled with resin, so that the plating adheres to the surface of the porous element body 2. Can be effectively deterred.

一方、内部電極3には、多孔質素体2との間での確実なオーミック接触を可能とする点から、例えば、Ni、Cu、またはAlを主成分とする材料が用いられ、これらの合金または複合材料であってもよく、低温焼成可能な多孔質素体2を用いることにより、Ni(融点:1450℃)に比べて融点の低いCu(融点1083℃)およびAl(融点660℃)を用いることができる。   On the other hand, for the internal electrode 3, for example, a material mainly composed of Ni, Cu, or Al is used from the viewpoint of enabling reliable ohmic contact with the porous body 2. It may be a composite material, and by using a porous body 2 that can be fired at a low temperature, Cu (melting point 1083 ° C.) and Al (melting point 660 ° C.) having a melting point lower than Ni (melting point: 1450 ° C.) should be used. Can do.

他方、外部電極5は、例えば、積層体4の側面への導電性ペーストの塗布および焼成により得られる。外部電極5を形成するための導電性ペーストとしては、主として、ガラス粉末と、有機ビヒクル(バインダー)と、金属粉末とを含むものが挙げられ、導電性ペーストの焼成により、有機ビヒクルは揮散し、最終的にガラス成分および金属成分を含む外部電極5が形成される。なお、導電性ペーストには、必要に応じて、粘度調整剤、無機結合剤、酸化剤等種々の添加剤を加えてもよい。   On the other hand, the external electrode 5 is obtained, for example, by applying and baking a conductive paste on the side surface of the laminate 4. Examples of the conductive paste for forming the external electrode 5 mainly include glass powder, an organic vehicle (binder), and a metal powder. By firing the conductive paste, the organic vehicle is volatilized, Finally, the external electrode 5 containing a glass component and a metal component is formed. In addition, you may add various additives, such as a viscosity modifier, an inorganic binder, and an oxidizing agent, to an electrically conductive paste as needed.

本実施形態において、外部電極5は、例えば、金属成分としてAg、および、Al等を含むものであり、Al等が、内部電極3の構成成分であるNi、Cu、またはAlと、外部電極5に含まれるAgとの接合部位に介在することにより、内部電極3と外部電極5との間の接合面積が増大され、これにより、接続抵抗を十分に低下させることができるとともに、内部電極3と外部電極5との機械的な接合強度をも高めることが可能となる。   In the present embodiment, the external electrode 5 includes, for example, Ag and Al as metal components, and Al or the like is a constituent component of the internal electrode 3, such as Ni, Cu, or Al, and the external electrode 5. By interposing in the junction part with Ag contained in the electrode, the junction area between the internal electrode 3 and the external electrode 5 is increased, whereby the connection resistance can be sufficiently lowered, and the internal electrode 3 It is also possible to increase the mechanical bonding strength with the external electrode 5.

次に、上記の本実施形態に係る積層電子部品1の製造方法について、図3〜図7を参照して説明する。図3〜図7は、積層電子部品1を製造する手順の一例を示す工程図である。   Next, a method for manufacturing the multilayer electronic component 1 according to the present embodiment will be described with reference to FIGS. 3-7 is process drawing which shows an example of the procedure which manufactures the multilayer electronic component 1. FIG.

まず、出発原料として、BaCO3、TiO2および硝酸Sm溶液を所定量混合し、純水およびジルコニアボールとともにポリエチレン製ポットに入れて5時間粉砕混合した後、混合液を蒸発乾燥させて、得られた混合粉を1100度で仮焼成する。 First, as a starting material, a predetermined amount of BaCO 3 , TiO 2 and Sm nitrate solution are mixed, put into a polyethylene pot together with pure water and zirconia balls, pulverized and mixed for 5 hours, and then the mixture is evaporated and dried. The mixed powder was calcined at 1100 degrees.

次に、仮焼粉に対して、再び、純水およびジルコニアボールを用いて、5〜30時間ボールミルによる粉砕を行なった後、蒸発乾燥を行い、チタン酸バリウム半導体セラミック粉末を得る。例えば、組成が(Ba0.9985Gd0.00150.995(Ti0.9985Nb0.0015)O3からなるチタン酸バリウム半導体セラミック粉末を得る。 Next, the calcined powder is again pulverized with a ball mill for 5 to 30 hours using pure water and zirconia balls, and then evaporated and dried to obtain a barium titanate semiconductor ceramic powder. For example, a barium titanate semiconductor ceramic powder having a composition of (Ba 0.9985 Gd 0.0015 ) 0.995 (Ti 0.9985 Nb 0.0015 ) O 3 is obtained.

次いで、得られた粉末に、有機溶剤、有機バインダおよび可塑剤等を添加して、セラミックスラリーとした後、ドクターブレード法により成形して、図3に示すシート状の多孔質素体2、いわゆるセラミックグリーンシートを得る。   Next, an organic solvent, an organic binder, a plasticizer, and the like are added to the obtained powder to form a ceramic slurry, which is then molded by a doctor blade method to form a sheet-like porous body 2 shown in FIG. Get a green sheet.

さらに、図4に示すように、シート状の多孔質素体2上に、Ni、Cu、またはAlを金属成分として含有する導電性ペーストをスクリーン印刷することにより、内部電極3のパターンを形成する。   Furthermore, as shown in FIG. 4, the pattern of the internal electrode 3 is formed on the sheet-like porous body 2 by screen printing a conductive paste containing Ni, Cu, or Al as a metal component.

次に、図5に示すように、内部電極3が形成された複数の多孔質素体2と内部電極3が形成されていない複数の多孔質素体2とを交互に積層し、それを更に加圧して積層構造体40を得る。   Next, as shown in FIG. 5, a plurality of porous element bodies 2 on which internal electrodes 3 are formed and a plurality of porous element bodies 2 on which no internal electrodes 3 are formed are alternately laminated, and further pressurized. Thus, the laminated structure 40 is obtained.

それから、図6に示すように、積層構造体40を切断することにより個々の積層構造体41に分割する。切断後の積層構造体41の側面からは、内部電極3の端部が露出した状態とされている。   Then, as shown in FIG. 6, the laminated structure 40 is cut to be divided into individual laminated structures 41. The end of the internal electrode 3 is exposed from the side surface of the laminated structure 41 after cutting.

次に、積層構造体41を、大気中で脱バインダ処理した後、H2/N2=3/100の強還元雰囲気中において1300℃で2時間焼成を行い、焼結された積層体4を得る。その後、大気中において600℃〜1000℃の温度で1時間再酸化処理を施す。 Next, the laminated structure 41 is subjected to a binder removal treatment in the air, and then fired at 1300 ° C. for 2 hours in a strong reducing atmosphere of H 2 / N 2 = 3/100, whereby the laminated body 4 is sintered. obtain. Thereafter, reoxidation treatment is performed in the air at a temperature of 600 ° C. to 1000 ° C. for 1 hour.

次いで、図7に示すように、積層体4の側面に、Agと、Al等を含む導電性ペーストを塗布し、大気中において600℃〜1000℃の温度で1時間〜数時間で焼成して外部電極5を形成する。   Next, as shown in FIG. 7, a conductive paste containing Ag, Al, and the like is applied to the side surface of the laminate 4 and fired in the air at a temperature of 600 ° C. to 1000 ° C. for 1 hour to several hours. The external electrode 5 is formed.

次に、多孔質素体2への樹脂充填を実施する。充填方法としては、特に制限されず、(1)外部電極5,5の部分を適宜の部材で覆った状態で多孔質素体2全体を液状の未硬化の樹脂(重合性のものであればモノマー、プレポリマー:以下同様)中に浸漬させ所定時間保持することにより、多孔質素体2の空孔内に樹脂を含浸させ、その後、加熱し樹脂を硬化させる方法、(2)外部電極5,5の部分を覆うことなく多孔質素体2全体を未硬化樹脂中に浸漬させて多孔質素体2の空孔内に樹脂を含浸させ、外部電極5,5に付着した樹脂を溶剤等で除去した後、加熱し樹脂を硬化させる方法、(3)多孔質素体2の露出面から未硬化の樹脂を圧入する方法などを例示できる。   Next, the porous element body 2 is filled with resin. The filling method is not particularly limited. (1) The entire porous body 2 is covered with an appropriate member in a state where the external electrodes 5 and 5 are covered with an appropriate member (a monomer that is polymerizable if it is polymerizable). , Prepolymer: the same applies to the following) and retaining for a predetermined time to impregnate the resin in the pores of the porous body 2, and then heating to cure the resin, (2) external electrodes 5, 5 After immersing the entire porous element body 2 in an uncured resin without covering the part, impregnating the resin in the pores of the porous element body 2, and removing the resin adhering to the external electrodes 5 and 5 with a solvent or the like And a method of curing the resin by heating, and (3) a method of press-fitting uncured resin from the exposed surface of the porous element body 2.

なお、多孔質素体2への樹脂の充填率は、樹脂の含浸を1回または複数回繰り返し、その回数を適宜調整することにより、調節することができ、含浸回数が多い方が、樹脂の充填率をより高めることが可能である。あるいは、樹脂の粘度を調整することによっても、多孔質素体2への樹脂の充填率を調節することができる。また、樹脂の種類にもよるが、例えば、シリコーン系樹脂の場合、加熱硬化条件としては、70℃で30分加熱後さらに180℃で1時間加熱するといった手法を例示できる。さらに、モノマーやプレポリマーを加熱により重合硬化させる際に、多孔質素体2の表面の樹脂層の架橋を促進するべく、紫外線硬化型を兼ねる樹脂であれば、紫外線照射と加熱を同時に行なってもよい。   The filling rate of the resin into the porous body 2 can be adjusted by repeating the resin impregnation once or a plurality of times and adjusting the number of times as appropriate. It is possible to increase the rate. Alternatively, the filling rate of the resin into the porous body 2 can also be adjusted by adjusting the viscosity of the resin. Further, although depending on the type of resin, for example, in the case of a silicone-based resin, as a heat curing condition, a method of heating at 70 ° C. for 30 minutes and further heating at 180 ° C. for 1 hour can be exemplified. Furthermore, when the monomer or prepolymer is polymerized and cured by heating, if the resin also serves as an ultraviolet curable resin so as to promote cross-linking of the resin layer on the surface of the porous body 2, ultraviolet irradiation and heating can be performed simultaneously. Good.

さらに、図2に示す如く、多孔質素体2の表面上に樹脂層を形成させるには、多孔質素体2に樹脂を含浸させた後、多孔質素体2を洗浄しないか、または、十分に洗浄しない状態で加熱硬化させればよい。   Further, as shown in FIG. 2, in order to form a resin layer on the surface of the porous element body 2, the porous element body 2 is impregnated with resin, and then the porous element body 2 is not washed or sufficiently washed. What is necessary is just to heat-cure in the state which does not carry out.

さらに、図1に示すように、外部電極5の表面に、電気めっきによりNi層7aおよびSn層7bを順次堆積させて端子電極7を形成する。例えば、Ni層7aの形成では、バレルめっき方式を採用し、ワット浴を用いてNiを2μm析出させる。また、Sn層7bの形成では、バレルめっき方式を採用し、中性錫めっき浴を用いて、Snを4μm析出させる。それから、端子電極7上または図示しない配線基板の電極上にはんだを形成し、そのはんだを溶融させて端子電極7と基板の電極とを電気的に接続する。   Further, as shown in FIG. 1, a terminal electrode 7 is formed by sequentially depositing a Ni layer 7a and a Sn layer 7b on the surface of the external electrode 5 by electroplating. For example, in the formation of the Ni layer 7a, a barrel plating method is adopted, and Ni of 2 μm is deposited using a watt bath. Further, in forming the Sn layer 7b, a barrel plating method is adopted, and Sn is deposited by 4 μm using a neutral tin plating bath. Then, solder is formed on the terminal electrode 7 or an electrode of a wiring board (not shown), and the solder is melted to electrically connect the terminal electrode 7 and the electrode of the board.

かかる積層電子部品1の製造方法によれば、大気雰囲気にて外部電極5用の導電性ペーストを焼成できる。これにより、還元雰囲気で焼成する場合に比べて、雰囲気制御が簡易になるので、製造コストを低下させることができる。また、前記のとおり、特に、PTCサーミスタを作製する際には、外部電極形成用の導電性ペーストを還元雰囲気で焼成すると、積層体がPTC特性を発現しなくなるが、本発明によれば、積層体4のPTC特性を維持しつつ外部電極5を形成することができる。   According to the method for manufacturing the multilayer electronic component 1, the conductive paste for the external electrode 5 can be fired in the air atmosphere. Thereby, compared with the case where it bakes in a reducing atmosphere, atmosphere control becomes simple and can reduce manufacturing cost. In addition, as described above, in particular, when a PTC thermistor is manufactured, if the conductive paste for forming the external electrode is baked in a reducing atmosphere, the laminate does not exhibit the PTC characteristics. The external electrode 5 can be formed while maintaining the PTC characteristics of the body 4.

<第2実施形態>
図8は、本発明による積層電子部品の第2実施形態の概略構造を示す断面図である。積層電子部品9は、外部電極5の表面に、金属成分としてAgを含むオーバーコート層8が外部電極5を覆うように形成されていること以外は、図1に示す積層電子部品1と同様に構成されたものである。このオーバーコート層8は、例えば、Agを含む導電性ペーストを印刷・焼成することにより形成することができる。なお、図示を省略したが、図8においては、オーバーコート層8,8の外側に端子電極7,7が積層形成されている。
Second Embodiment
FIG. 8 is a sectional view showing a schematic structure of a second embodiment of the multilayer electronic component according to the present invention. The multilayer electronic component 9 is the same as the multilayer electronic component 1 shown in FIG. 1 except that an overcoat layer 8 containing Ag as a metal component is formed on the surface of the external electrode 5 so as to cover the external electrode 5. It is configured. The overcoat layer 8 can be formed, for example, by printing and baking a conductive paste containing Ag. Although illustration is omitted, in FIG. 8, terminal electrodes 7 and 7 are laminated on the outside of the overcoat layers 8 and 8.

かかる構造の積層電子部品9によれば、外部電極5の表面にオーバーコート層8が形成されていることにより、外部電極5に含まれるAl等が、図2に示すような端子電極7を形成するためのめっき液に腐食されることを、より一層確実に防止することができる。   According to the multilayer electronic component 9 having such a structure, since the overcoat layer 8 is formed on the surface of the external electrode 5, Al or the like contained in the external electrode 5 forms the terminal electrode 7 as shown in FIG. It can prevent more reliably that it is corroded by the plating solution for doing.

なお、上述したとおり、本発明は、上記各実施形態に限定されるものではなく、その要旨を逸脱しない範囲内において適宜変更を加えることが可能である。例えば、積層電子部品1では、外部電極5を形成する前に、多孔質素体2への樹脂含浸を行なってもよく、積層電子部品9では、外部電極5の形成前もしくは形成後またはオーバーコート層8の形成後に、多孔質素体2への樹脂含浸を行なってもよい。さらに、多孔質素体2はセラミックスであればよく、半導体セラミックスである必要はない。例えば、積層電子部品1,9として積層セラミックコンデンサを作製する場合には、多孔質素体2は、絶縁性のセラミックスからなるものを用いることができる。またさらに、内部電極3は、少なくとも1つ以上形成すればよい。   In addition, as above-mentioned, this invention is not limited to said each embodiment, In the range which does not deviate from the summary, it can add suitably. For example, in the multilayer electronic component 1, the porous element body 2 may be impregnated with the resin before forming the external electrode 5. In the multilayer electronic component 9, before or after the formation of the external electrode 5 or overcoat layer After the formation of 8, the porous element body 2 may be impregnated with resin. Furthermore, the porous element body 2 may be a ceramic, and need not be a semiconductor ceramic. For example, when a multilayer ceramic capacitor is manufactured as the multilayer electronic component 1, 9, the porous element body 2 can be made of an insulating ceramic. Furthermore, at least one internal electrode 3 may be formed.

以下、本発明の実施例について説明するが、本発明はこれら実施例に限定されるものではない。   Examples of the present invention will be described below, but the present invention is not limited to these examples.

〈PTCサーミスタの製造〉
上述した製造手順と同様にして、組成が(Ba0.9985Gd0.00150.995(Ti0.9985Nb0.0015)O3からなる多孔質素体2と、Niからなる複数の内部電極3を有する3.2mm×1.6mm×0.5mmサイズの積層体4を作製し、この積層体4の側面に、AlおよびAgの含有割合が種々異なる導電性ペーストを塗布し、大気雰囲気中において600℃で焼成して外部電極5を形成した。この多孔質素体2に付加重合型のシリコーン系モノマーを含浸させた後、70℃で30分加熱後さらに180℃で1時間加熱という加熱条件で樹脂を重合硬化させた。さらに、外部電極5,5上に端子電極7,7を、バレルめっきにてワット浴を用いてNiを2μmの厚さで、中性錫めっき浴を用いてSnを4μmの厚さで形成し、積層電子部品としてのPTCサーミスタを得た。
<Manufacture of PTC thermistors>
In the same manner as the manufacturing procedure described above, the composition has a porous element body 2 made of (Ba 0.9985 Gd 0.0015 ) 0.995 (Ti 0.9985 Nb 0.0015 ) O 3 and a plurality of internal electrodes 3 made of Ni of 3.2 mm × 1. A laminated body 4 having a size of 6 mm × 0.5 mm was prepared, and conductive pastes having different contents of Al and Ag were applied to the side surfaces of the laminated body 4 and fired at 600 ° C. in an air atmosphere to external electrodes. 5 was formed. After impregnating this porous element body 2 with an addition polymerization type silicone monomer, the resin was polymerized and cured under heating conditions of heating at 70 ° C. for 30 minutes and further heating at 180 ° C. for 1 hour. Further, the terminal electrodes 7 and 7 are formed on the external electrodes 5 and 5 by using a watt bath by barrel plating with a Ni thickness of 2 μm and a neutral tin plating bath with a thickness of 4 μm. A PTC thermistor as a laminated electronic component was obtained.

(実施例1〜5)
焼結密度が80%である多孔質素体2への樹脂の充填率を変化させ、上記のPTCサーミスタの製造手順により、本発明による樹脂の充填率60%以上のPTCサーミスタを5種類、それぞれ複数製造した。なお、樹脂の充填率は、含浸を1回または複数回繰り返し、その含浸回数で適宜調節した。
(Examples 1-5)
By changing the filling rate of the resin into the porous body 2 having a sintered density of 80%, and according to the PTC thermistor manufacturing procedure, five types of PTC thermistors having a filling rate of 60% or more of the resin according to the present invention are used. Manufactured. The filling rate of the resin was adjusted as appropriate by the number of impregnations by repeating the impregnation once or plural times.

(比較例1)
焼結密度が80%である多孔質素体に樹脂を含浸・充填しなかったこと以外は、上記のPTCサーミスタの製造手順により、樹脂の充填率0%のPTCサーミスタを複数製造した。
(Comparative Example 1)
A plurality of PTC thermistors having a resin filling rate of 0% were manufactured by the above-described PTC thermistor manufacturing procedure except that the porous element body having a sintered density of 80% was not impregnated and filled with the resin.

(比較例2〜4)
焼結密度が80%である多孔質素体への樹脂の充填率を変化させ、上記のPTCサーミスタの製造手順により、樹脂の充填率60%未満のPTCサーミスタを、それぞれ複数製造した。
(Comparative Examples 2 to 4)
A plurality of PTC thermistors each having a resin filling rate of less than 60% were manufactured by changing the filling rate of the resin into the porous body having a sintered density of 80% and manufacturing the PTC thermistor.

(試験評価1)
各実施例および比較例で得られたPTCサーミスタについて、多孔質素体の表面のめっき付着率(%)、PTCサーミスタの配線基板への実装後の特性不良発生率(%)、爆ぜ試験での不良発生率(%)を測定評価した。表面のめっき付着率(%)は、PTCサーミスタの多孔質素体の露出面積に対するめっきされた領域の面積から算出した。また、実装後の特性不良発生率(%)は、各PTCサーミスタにつき100体のサンプルを、リフロー処理で配線基板へ実装した後、200℃での抵抗値がリフロー前の抵抗値よりも10%低下したものの個体数の割合から算出した。さらに、爆ぜ試験での不良発生率(%)は、各PTCサーミスタにつき100体のサンプルを、260℃のシリコンオイルに浸漬し、多孔質素体から発泡があったものの個体数の割合から算出した。結果をまとめて表1に示す。また、図9は、表1のデータをグラフ化したものである。
(Test evaluation 1)
For the PTC thermistors obtained in each of the examples and comparative examples, the plating adhesion rate (%) on the surface of the porous element body, the occurrence rate of characteristic defects after mounting the PTC thermistor on the wiring board (%), the failure in the explosion test The incidence (%) was measured and evaluated. The plating adhesion rate (%) on the surface was calculated from the area of the plated region with respect to the exposed area of the porous body of the PTC thermistor. Also, the characteristic failure rate (%) after mounting is 10% higher than the resistance value before reflow after mounting 100 samples for each PTC thermistor on the wiring board by reflow processing. It was calculated from the ratio of the number of individuals that decreased. Furthermore, the defect occurrence rate (%) in the explosion test was calculated from the ratio of the number of individuals in which 100 samples for each PTC thermistor were immersed in silicon oil at 260 ° C. and foamed from the porous body. The results are summarized in Table 1. FIG. 9 is a graph of the data in Table 1.

表1および図9より、多孔質素体2への樹脂の充填率が60%以上であると、多孔質素体の表面のめっき付着率を十分に抑制でき、また、その充填率が70%以上であると、PTCサーミスタの配線基板への実装後の特性不良発生率を十分に改善でき、さらに、その充填率が80%以上であると、爆ぜ試験での不良発生率を十分に低減できることが確認された。   From Table 1 and FIG. 9, when the filling rate of the resin to the porous body 2 is 60% or more, the plating adhesion rate on the surface of the porous body can be sufficiently suppressed, and the filling rate is 70% or more. It is confirmed that the failure rate of characteristics after mounting the PTC thermistor on the wiring board can be sufficiently improved, and that the failure rate in the explosion test can be sufficiently reduced when the filling rate is 80% or more. It was.

なお、図10および図11は、それぞれ、樹脂充填率0%(めっき付着率100%)の比較例のPTCサーミスタの多孔質素体の平面外観写真、および、その表層部の断面拡大写真であり、図12および図13は、その断面をEPMAで観察したときのそれぞれNiおよびSnの元素分布を示す図である。これらの結果より、多孔質素体に樹脂を含浸・充填していないPTCサーミスタでは、多孔質素体表面が金属光沢を有しており、また、多孔質素体の内部の深い領域までNiが浸入していることが判明した。   FIG. 10 and FIG. 11 are a plane external view photograph of a porous body of a PTC thermistor of a comparative example having a resin filling rate of 0% (plating adhesion rate of 100%), and a cross-sectional enlarged photograph of the surface layer portion, respectively. 12 and 13 are diagrams showing element distributions of Ni and Sn, respectively, when the cross section is observed with EPMA. From these results, in the PTC thermistor in which the porous element body is not impregnated / filled with resin, the surface of the porous element body has a metallic luster, and Ni penetrates to a deep region inside the porous element body. Turned out to be.

また、図14および図15、図16および図17、図18および図19、図20および図21は、それぞれ、樹脂充填率42%(めっき付着率31%)、樹脂充填率56%(めっき付着率9.1%)の比較例のPTCサーミスタ、樹脂充填率82%(めっき付着率3.2%)、樹脂充填率98%(めっき付着率0.5%)の実施例のPTCサーミスタの各多孔質素体の平面外観写真、および、それらの表層部の断面拡大写真である。   14 and 15, FIG. 16 and FIG. 17, FIG. 18 and FIG. 19, FIG. 20 and FIG. 21 respectively show a resin filling rate of 42% (plating adhesion rate of 31%) and a resin filling rate of 56% (plating adhesion). Each of the PTC thermistors of the comparative example with a rate of 9.1%), the resin filling rate of 82% (plating adhesion rate of 3.2%), and the resin filling rate of 98% (plating adhesion rate of 0.5%). It is the plane external appearance photograph of a porous element | base_body, and the cross-sectional enlarged photograph of those surface layer parts.

(参考例1〜6)
多孔質素体2の焼結密度を変化させ、比較例1と同様の手順でPTCサーミスタを製造し、焼結密度と多孔質素体の表面へのめっき付着率との関係を評価した。結果をまとめて表2に示す。また、図22は、表1のデータをグラフ化したものである。
(Reference Examples 1-6)
The PTC thermistor was manufactured in the same procedure as in Comparative Example 1 by changing the sintered density of the porous element body 2, and the relationship between the sintered density and the plating adhesion rate to the surface of the porous element body was evaluated. The results are summarized in Table 2. FIG. 22 is a graph of the data in Table 1.

表2および図22より、多孔質素体の焼結密度が90%以下の場合にはめっき付着率が80%を超えてしまう程度にめっきの付着が顕著であるのに対し、焼結密度が90%を超えると、めっき付着率は急激に低下し、めっきの付着は、ほとんど不都合が生じない程度であることが判明した。   From Table 2 and FIG. 22, when the sintered density of the porous element body is 90% or less, the adhesion of the plating is remarkable to the extent that the plating adhesion rate exceeds 80%, whereas the sintering density is 90%. When the percentage exceeds 50%, the plating adhesion rate decreases rapidly, and it has been found that the adhesion of the plating is almost inconvenient.

本発明は、サーミスタ、コンデンサ、インダクタ、LTCC(Low Temperature Co-fired Ceramics)、バリスタ、それらの複合部品からなる積層電子部品等、および、それらを備える機器、装置、システム、設備等、ならびに、それらの製造に広く利用することができる。   The present invention relates to a thermistor, a capacitor, an inductor, a LTCC (Low Temperature Co-fired Ceramics), a varistor, a laminated electronic component composed of a composite part thereof, and a device, an apparatus, a system, a facility, and the like including them, and Can be widely used in the manufacture of

本発明による積層電子部品の第1実施形態の概略構造を示す断面図である。It is sectional drawing which shows schematic structure of 1st Embodiment of the multilayer electronic component by this invention. 樹脂が60%以上の充填率で充填された多孔質素体2の実物の一例の表層断面を示す拡大写真である。It is an enlarged photograph which shows the surface layer cross section of an example of the real thing of the porous element | base_body 2 with which the resin was filled with the filling rate of 60% or more. 積層電子部品を製造する手順の一例を示す工程図である。It is process drawing which shows an example of the procedure which manufactures a laminated electronic component. 積層電子部品を製造する手順の一例を示す工程図である。It is process drawing which shows an example of the procedure which manufactures a laminated electronic component. 積層電子部品を製造する手順の一例を示す工程図である。It is process drawing which shows an example of the procedure which manufactures a laminated electronic component. 積層電子部品を製造する手順の一例を示す工程図である。It is process drawing which shows an example of the procedure which manufactures a laminated electronic component. 積層電子部品を製造する手順の一例を示す工程図である。It is process drawing which shows an example of the procedure which manufactures a laminated electronic component. 本発明による積層電子部品の第2実施形態の概略構造を示す断面図である。It is sectional drawing which shows schematic structure of 2nd Embodiment of the multilayer electronic component by this invention. 多孔質素体への樹脂の充填率に対する、表面のめっき付着率、実装後の特性不良発生率、爆ぜ試験での不良発生率を示すグラフである。It is a graph which shows the plating adhesion rate of the surface with respect to the filling rate of the resin to a porous element body, the characteristic defect occurrence rate after mounting, and the defect occurrence rate in the explosion test. 樹脂充填率0%(めっき付着率100%)の比較例のPTCサーミスタの多孔質素体の平面外観写真である。It is a plane external appearance photograph of the porous element body of the PTC thermistor of the comparative example with a resin filling rate of 0% (plating adhesion rate of 100%). 樹脂充填率0%(めっき付着率100%)の比較例のPTCサーミスタの多孔質素体の表層部の断面拡大写真である。It is a cross-sectional enlarged photograph of the surface layer part of the porous element body of the PTC thermistor of the comparative example of 0% of resin filling rate (plating adhesion rate 100%). 樹脂充填率0%(めっき付着率100%)の比較例のPTCサーミスタの多孔質素体の表層部の断面をEPMAで観察したときのNiの元素分布を示す図である。It is a figure which shows element distribution of Ni when the cross section of the surface layer part of the porous body of the PTC thermistor of the comparative example of 0% of resin filling rate (plating adhesion rate 100%) is observed by EPMA. 樹脂充填率0%(めっき付着率100%)の比較例のPTCサーミスタの多孔質素体の表層部の断面をEPMAで観察したときのSnの元素分布を示す図である。It is a figure which shows element distribution of Sn when the cross section of the surface layer part of the porous element body of the PTC thermistor of the comparative example of 0% of resin filling rate (plating adhesion rate 100%) is observed by EPMA. 樹脂充填率42%(めっき付着率31%)の比較例のPTCサーミスタの多孔質素体の平面外観写真である。It is a plane external appearance photograph of the porous element body of the PTC thermistor of the comparative example of resin filling rate 42% (plating adhesion rate 31%). 樹脂充填率42%(めっき付着率31%)の比較例のPTCサーミスタの多孔質素体の表層部の断面拡大写真である。It is a cross-sectional enlarged photograph of the surface layer part of the porous element body of the PTC thermistor of the comparative example with a resin filling rate of 42% (plating adhesion rate of 31%). 樹脂充填率56%(めっき付着率9.1%)の比較例のPTCサーミスタの多孔質素体の平面外観写真である。It is a plane external appearance photograph of the porous element body of the PTC thermistor of the comparative example of 56% of resin filling rate (plating adhesion rate 9.1%). 樹脂充填率56%(めっき付着率9.1%)の比較例のPTCサーミスタの多孔質素体の表層部の断面拡大写真である。It is a cross-sectional enlarged photograph of the surface layer part of the porous element body of the PTC thermistor of the comparative example of 56% of resin filling rate (plating adhesion rate 9.1%). 樹脂充填率82%(めっき付着率3.2%)の比較例のPTCサーミスタの多孔質素体の平面外観写真である。It is a plane external appearance photograph of the porous element body of the PTC thermistor of the comparative example of resin filling rate 82% (plating adhesion rate 3.2%). 樹脂充填率82%(めっき付着率3.2%)の比較例のPTCサーミスタの多孔質素体の表層部の断面拡大写真である。It is a cross-sectional enlarged photograph of the surface layer part of the porous element body of the PTC thermistor of the comparative example of resin filling rate 82% (plating adhesion rate 3.2%). 樹脂充填率98%(めっき付着率0.5%)の比較例のPTCサーミスタの多孔質素体の平面外観写真である。It is a plane external appearance photograph of the porous element body of the PTC thermistor of the comparative example of resin filling rate 98% (plating adhesion rate 0.5%). 樹脂充填率98%(めっき付着率0.5%)の比較例のPTCサーミスタの多孔質素体の表層部の断面拡大写真である。It is a cross-sectional enlarged photograph of the surface layer part of the porous body of the PTC thermistor of the comparative example with a resin filling rate of 98% (plating adhesion rate of 0.5%). 多孔質素体の焼結密度に対する、多孔質素体の表面へのめっき付着率を示すグラフである。It is a graph which shows the plating adhesion rate to the surface of a porous element with respect to the sintered density of a porous element.

符号の説明Explanation of symbols

1,9…積層電子部品、2…多孔質素体、3…内部電極、4…積層体(焼結体)、5…外部電極、7…端子電極、7a…Ni層、7b…Sn層、8…オーバーコート層、10…単位構造、40,41…積層構造体。   DESCRIPTION OF SYMBOLS 1,9 ... Laminated electronic component, 2 ... Porous element body, 3 ... Internal electrode, 4 ... Laminated body (sintered body), 5 ... External electrode, 7 ... Terminal electrode, 7a ... Ni layer, 7b ... Sn layer, 8 ... overcoat layer, 10 ... unit structure, 40, 41 ... laminated structure.

Claims (3)

主としてセラミックスからなり、かつ、複数の空孔を含む多孔質素体と、該多孔質素体内に設けられた少なくとも1つの内部電極と、を有する積層体と、
前記内部電極に接続された外部電極と、
前記外部電極上にめっきにより形成された端子電極と、
を備えており、
前記多孔質素体は、前記複数の空孔に樹脂が60%以上の充填率で充填されたものである、
積層電子部品。
A laminate comprising a porous body mainly made of ceramics and including a plurality of pores, and at least one internal electrode provided in the porous body;
An external electrode connected to the internal electrode;
A terminal electrode formed by plating on the external electrode;
With
The porous element body is formed by filling the plurality of pores with a resin at a filling rate of 60% or more.
Laminated electronic components.
前記多孔質素体は、焼成されたものであり、焼結密度が90%以下のものである、
請求項1記載の積層電子部品。
The porous body is fired and has a sintered density of 90% or less.
The multilayer electronic component according to claim 1.
主としてセラミックスからなり、かつ、複数の空孔を含む多孔質素体内に、少なくとも1つの内部電極を設けて積層構造体を形成する工程と、
前記積層構造体を焼成して積層体を形成する工程と、
導電性ペーストを、前記積層体の内部電極と電気的に接続するように、前記積層体に塗布する工程と、
前記導電性ペーストを焼成して外部電極を形成する工程と、
前記多孔質素体に樹脂を含浸させて、前記複数の空孔に樹脂を60%以上の充填率で充填する工程と、
前記外部電極上にめっきにより端子電極を形成する工程と、
を有する積層電子部品の製造方法。
A step of forming a laminated structure by providing at least one internal electrode in a porous body mainly made of ceramics and including a plurality of pores;
Firing the laminated structure to form a laminated body;
Applying a conductive paste to the laminate so as to be electrically connected to an internal electrode of the laminate;
Firing the conductive paste to form external electrodes;
Impregnating the porous body with resin, and filling the plurality of pores with resin at a filling rate of 60% or more;
Forming a terminal electrode on the external electrode by plating;
A method of manufacturing a laminated electronic component having
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JP2010232320A (en) * 2009-03-26 2010-10-14 Tdk Corp Multilayer ceramic electronic component and method of manufacturing the same
JP2011216637A (en) * 2010-03-31 2011-10-27 Murata Mfg Co Ltd Laminated positive temperature coefficient thermistor and method of manufacturing laminated positive temperature coefficient thermistor
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WO2017217469A1 (en) * 2016-06-16 2017-12-21 株式会社村田製作所 Method for producing electronic component

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04282802A (en) * 1991-03-11 1992-10-07 Taiyo Yuden Co Ltd Manufacture of ceramic electronic parts
JPH07240334A (en) * 1992-09-14 1995-09-12 Tdk Corp Electronic parts and its manufacture
JPH10208907A (en) * 1997-01-28 1998-08-07 Matsushita Electric Ind Co Ltd Electronic device and production thereof
JP2004297020A (en) * 2002-04-01 2004-10-21 Murata Mfg Co Ltd Ceramic electronic component and its manufacturing method
JP2005093707A (en) * 2003-09-17 2005-04-07 Murata Mfg Co Ltd Method for manufacturing lamination ceramic electronic component

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09205005A (en) * 1996-01-24 1997-08-05 Matsushita Electric Ind Co Ltd Electronic component and manufacture thereof
KR100544908B1 (en) * 2002-04-01 2006-01-24 가부시키가이샤 무라타 세이사쿠쇼 Ceramic electronic component and method for manufacturing the same
CN100527289C (en) * 2003-02-21 2009-08-12 株式会社村田制作所 Laminate type ceramic electronic component and method of producing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04282802A (en) * 1991-03-11 1992-10-07 Taiyo Yuden Co Ltd Manufacture of ceramic electronic parts
JPH07240334A (en) * 1992-09-14 1995-09-12 Tdk Corp Electronic parts and its manufacture
JPH10208907A (en) * 1997-01-28 1998-08-07 Matsushita Electric Ind Co Ltd Electronic device and production thereof
JP2004297020A (en) * 2002-04-01 2004-10-21 Murata Mfg Co Ltd Ceramic electronic component and its manufacturing method
JP2005093707A (en) * 2003-09-17 2005-04-07 Murata Mfg Co Ltd Method for manufacturing lamination ceramic electronic component

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010232320A (en) * 2009-03-26 2010-10-14 Tdk Corp Multilayer ceramic electronic component and method of manufacturing the same
JP2011216637A (en) * 2010-03-31 2011-10-27 Murata Mfg Co Ltd Laminated positive temperature coefficient thermistor and method of manufacturing laminated positive temperature coefficient thermistor
JP2016524813A (en) * 2013-05-06 2016-08-18 エプコス アクチエンゲゼルシャフトEpcos Ag Electronic device and passivation method thereof
US9734948B2 (en) 2013-05-06 2017-08-15 Epcos Ag Electronic component and method for the passivation thereof
WO2017217469A1 (en) * 2016-06-16 2017-12-21 株式会社村田製作所 Method for producing electronic component
JPWO2017217469A1 (en) * 2016-06-16 2019-02-28 株式会社村田製作所 Manufacturing method of electronic parts
US11309124B2 (en) 2016-06-16 2022-04-19 Murata Manufacturing Co., Ltd. Method for producing electronic component

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