JP2009038409A - Method of manufacturing semiconductor package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor package which is capable of achieving high density, minute wiring, and the pitch-narrowing of external electrodes, and superior in mounting reliability. <P>SOLUTION: The method of manufacturing a semiconductor package includes steps of: forming an electrode pattern on a substrate; forming an insulating layer covering the electrode pattern; forming a via-hole reaching the electrode pattern in the electrode pattern; forming a conductor layer over the insulating layer so as to bury the via-hole and patterning the conductor layer to form a wiring pattern; and mounting a semiconductor device on the wiring pattern. In this method, a resist layer having an opening pattern corresponding to the electrode pattern is formed on the substrate, and the substrate is etched with the resist layer as a mask to form a recess corresponding to the opening pattern of the resist layer on a substrate upper face, and a conductor is provided in the recess and the opening pattern to form the electrode pattern. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  INDUSTRIAL APPLICABILITY The present invention is capable of mounting various semiconductor devices at high density, and is suitably used for realizing a high-speed and high-density module or system, a manufacturing method thereof, and a semiconductor device mounted on the wiring board The present invention relates to a manufactured semiconductor package.

  In recent years, with the increase in the number of terminals and the reduction in pitch due to higher speeds, multifunctions and higher integration of semiconductor devices, even higher density and finer wiring has been achieved in mounting wiring boards on which semiconductor devices are mounted. It is requested.

  As a mounting wiring board that is often used at present, there is a build-up multilayer board which is a kind of multilayer wiring board.

  This build-up multilayer board is manufactured as follows using a glass epoxy printed board as a base core board. First, an epoxy resin layer is formed on both surfaces of the glass epoxy printed board. Next, via holes are formed in these epoxy resin layers by photolithography or laser. Thereafter, a wiring layer and a via conductor are formed on the epoxy resin layer by combining electroless or electrolytic Cu plating and photolithography. A build-up laminated structure is formed by sequentially repeating the above steps.

  However, in this build-up multilayer board, because a glass epoxy printed board with low heat resistance is used for the base core board, the glass epoxy printed board is shrunk, warped, by heat treatment during build-up multilayer board production. There is a problem that defects such as undulation occur. Since these defects significantly reduce the accuracy in the exposure process, it is difficult to form a high-density and fine wiring pattern on the glass epoxy printed board.

  In addition, when mounting a semiconductor device on such a build-up multilayer substrate by flip chip method, a connection failure or strain is caused between the semiconductor device and the build-up multilayer substrate due to heat treatment during chip mounting or solder reflow. Therefore, long-term connection reliability may be reduced.

  In order to solve the above problem, a mounting wiring board in which a build-up laminated structure is formed on a base board made of a metal plate has been proposed (Patent Document 1: Japanese Patent Laid-Open No. 2000-3980).

FIG. 18 is a manufacturing process diagram of this mounting wiring board. First, as shown in FIG. 18A, the insulating layer 102 is formed on the metal plate 101, and the via hole 103 is formed in the insulating layer 102. Next, as shown in FIG. 18B, a wiring pattern 104 is formed on the insulating layer 102 including the via hole 103. Next, as shown in FIG. 18C, an insulating layer 106 is formed on the wiring pattern 104, and a flip chip pad portion 105 reaching the wiring pattern 104 is formed on the insulating layer 106. Finally, as shown in FIG. 18D, the metal plate 101 is etched from below to form the substrate reinforcement 107 and the external electrode terminals 108.
Japanese Unexamined Patent Publication No. 2000-3980

  In recent years, for mounting wiring boards, in addition to the above-mentioned high-density and fine wiring, in order to achieve miniaturization and high-density of the system, to electrically connect with external boards and devices There is a strong demand to narrow the pitch of the external electrodes.

  However, in the conventional mounting wiring substrate shown in FIG. 18, since the external electrode terminal 108 is formed by etching the metal plate 101, the external electrode terminal 108 having a narrow pitch is formed due to the limit of the side etching amount control at the time of etching. It is very difficult to do.

  Also, when this mounting wiring board is mounted on an external board or device, due to the structure, stress concentrates on the interface between the external electrode terminal 108 and the insulating layer 102, and open defects are likely to occur, so that sufficient mounting reliability is achieved. Sex cannot be obtained.

  The present invention has been made in view of the above circumstances, and can realize high density and fine wiring corresponding to an increase in the number of terminals of semiconductor devices and narrow pitch, and downsizing and high density of the system. An object of the present invention is to provide a wiring board for mounting a semiconductor device, a method for manufacturing the same, and a semiconductor package, which can realize a narrow pitch of external electrodes corresponding to the increase in the size, and which is excellent in mounting reliability.

  The present invention provides an insulating layer, a wiring provided on the upper surface of the insulating layer, and an electrode provided on the lower surface side of the insulating layer, wherein at least the periphery of the side of the upper end of the electrode is in contact with the insulating layer and at least the lower surface of the electrode , An electrode provided so as not to contact the insulating layer, a via located on the upper surface of the electrode and provided in the insulating layer so as to conduct the electrode and the wiring, and a surface of the insulating layer The present invention relates to a wiring board for mounting a semiconductor device having a support provided on the board.

  The present invention also relates to the above-described wiring board for mounting a semiconductor device, wherein the electrode has a side surface in contact with the insulating layer, and the lower surface of the electrode is in the same plane as the lower surface of the insulating layer.

  The present invention also relates to the above-described wiring board for mounting a semiconductor device, wherein the insulating layer has a recess on its lower surface, and the lower surface of the electrode forms the bottom surface of the recess.

  The present invention also relates to the above-mentioned wiring board for mounting a semiconductor device, wherein the lower end portion of the electrode protrudes from the lower surface of the insulating layer.

  The present invention also relates to the above-mentioned wiring board for mounting a semiconductor device, which has a laminated structure in which a Cu layer is disposed on the upper end of the electrode and at least one different conductor layer is disposed on the lower end thereof.

  Further, the present invention provides the above semiconductor having a multilayer wiring structure in which one or more pairs of insulating layers and wirings formed on the upper surface of the insulating layer are alternately and sequentially provided on the upper surface of the insulating layer on which the wiring is formed. The present invention relates to a device mounting wiring board.

  Further, the present invention is an electrode provided on the lower surface side of the insulating layer, at least a side surface of the upper end of the electrode is in contact with the insulating layer, and at least an electrode lower surface is not in contact with the insulating layer; A capacitor comprising: a dielectric layer provided on the upper surface of the electrode; and a conductive layer provided on the upper surface of the dielectric layer, the conductive layer being electrically connected to a wiring provided on the upper surface of the insulating layer. The present invention relates to a wiring board for mounting a semiconductor device.

  The present invention also relates to the above-mentioned wiring board for mounting a semiconductor device, wherein the support is provided on the lower surface of the insulating layer so that the lower surface of the electrode is exposed.

  The present invention also relates to the above semiconductor device mounting wiring board in which the support is provided on the entire lower surface of the insulating layer.

  The present invention also relates to a wiring board for mounting a semiconductor device, wherein the wiring board is provided on the upper surface and the lower surface side of a laminated board on which two substrates are bonded, using the substrate as the support.

  The present invention also relates to a semiconductor package in which a semiconductor device is mounted on the wiring board.

  The present invention also provides an insulating layer, a wiring provided on the upper surface of the insulating layer, and an electrode provided on the lower surface side of the insulating layer, wherein at least the periphery of the side of the upper end of the electrode is in contact with the insulating layer and at least the electrode A wiring board having an electrode provided so that a lower surface thereof does not contact the insulating layer, and vias provided on the upper surface of the electrode and provided in the insulating layer so as to conduct the electrode and the wiring; The present invention relates to a semiconductor package having a semiconductor device mounted on the wiring board.

  The present invention also relates to the above-described semiconductor package, wherein the periphery of the side surface of the electrode is in contact with the insulating layer, and the lower surface of the electrode is in the same plane as the lower surface of the insulating layer.

  The present invention also relates to the above-described semiconductor package, wherein the lower surface of the insulating layer has a recess, and the lower surface of the electrode forms the bottom surface of the recess.

  The present invention also relates to the above semiconductor package, wherein the lower end of the electrode protrudes from the lower surface of the insulating layer.

  The present invention also relates to the above semiconductor package, wherein the electrode has a laminated structure in which a Cu layer is disposed at the upper end portion and at least one different conductor layer is disposed at the lower end side.

  Further, the present invention provides the above semiconductor having a multilayer wiring structure in which one or more pairs of insulating layers and wirings formed on the upper surface of the insulating layer are alternately and sequentially provided on the upper surface of the insulating layer on which the wiring is formed. Regarding packages.

  Further, the present invention is an electrode provided on the lower surface side of the insulating layer, at least a side surface of the upper end of the electrode is in contact with the insulating layer, and at least an electrode lower surface is not in contact with the insulating layer; A capacitor comprising: a dielectric layer provided on the upper surface of the electrode; and a conductive layer provided on the upper surface of the dielectric layer, the conductive layer being electrically connected to a wiring provided on the upper surface of the insulating layer. The present invention relates to the above semiconductor package.

  The present invention also includes a step of forming an electrode pattern on the substrate, a step of forming an insulating layer on the substrate so as to cover the electrode pattern, and a step of forming a via hole reaching the electrode pattern in the insulating layer. And a method of manufacturing a wiring board for mounting a semiconductor device, comprising: forming a conductor layer on the insulating layer so as to fill the via hole; and patterning the conductor layer to form a wiring pattern.

  The present invention further includes a step of forming a dielectric layer on the predetermined electrode pattern after forming the electrode pattern, the dielectric layer, the electrode pattern under the dielectric layer, and the dielectric layer being formed on the dielectric layer. The present invention relates to the above manufacturing method, characterized in that a capacitor is formed with a conductive layer embedded in a via hole that reaches the via hole.

  The present invention also relates to the above-described manufacturing method including a step of selectively removing the substrate to expose the electrode pattern and using the remaining portion of the substrate as a support.

  The present invention also relates to the above-described manufacturing method including a step of removing the substrate and exposing the electrode pattern after mounting a semiconductor device.

  The present invention also relates to the above manufacturing method, wherein the exposed electrode pattern is selectively etched and removed by a predetermined thickness to form a recess in the lower surface of the insulating layer.

  According to the present invention, in the step of forming an electrode pattern on the substrate, a conductive substrate is used as the substrate, a resist layer having an opening pattern corresponding to the electrode pattern is formed on the substrate, and the opening pattern is formed in the opening pattern. The present invention relates to the above manufacturing method in which a metal is deposited by a plating method to form the electrode pattern.

  In the present invention, the substrate is etched using the resist layer as a mask to form a recess corresponding to the opening pattern of the resist layer on the upper surface of the substrate, and then the metal is deposited on the recess to form the electrode pattern. It relates to the above manufacturing method.

  The present invention also provides a step of preparing a laminated plate formed by bonding a first substrate and a second substrate, a first electrode pattern is formed on the first substrate, and the second substrate is formed on the second substrate. A step of forming a second electrode pattern, a step of forming first and second insulating layers on the laminated plate so as to cover the first and second electrode patterns, respectively, and the first insulating layer Forming a via hole reaching the first electrode pattern and forming a via hole reaching the second electrode pattern in the second insulating layer; and filling the via hole with the first and second vias. The present invention relates to a method for manufacturing a wiring board for mounting a semiconductor device, comprising: forming a conductor layer on each of two insulating layers; and patterning the conductor layer to form first and second wiring patterns.

  The present invention also relates to the above manufacturing method including a step of separating the first substrate and the second substrate.

  In the present invention, after the first substrate and the second substrate are separated, the first and second substrates are selectively removed to expose the electrode pattern and to remove the remaining portion of the substrate. It is related with said manufacturing method which has the process made into a support body.

  The present invention also relates to the above-described manufacturing method including a step of removing the first and second substrates and exposing the electrode pattern after mounting the semiconductor device.

  The present invention also relates to the above-described method for manufacturing a wiring board, wherein the exposed electrode pattern is selectively etched and removed by a predetermined thickness to form a recess in the lower surface of the insulating layer.

  According to the present invention, in the step of forming the first and second electrode patterns, a conductive substrate is used as the first and second substrates, and the first and second substrates are respectively formed on the first and second substrates. The present invention relates to a method for manufacturing a wiring board as described above, wherein a resist layer having an opening pattern corresponding to two electrode patterns is formed, and a metal is deposited in the opening pattern by plating to form the first and second electrode patterns. .

  In the present invention, the first and second support substrates are etched using the resist layer as a mask to form a recess corresponding to the opening pattern of the resist layer on the upper surface of the substrate, and then a metal is formed on the recess. It is related with the manufacturing method of said wiring board which deposits and forms said 1st and 2nd electrode pattern.

  The present invention also relates to the above-described method for manufacturing a wiring board, wherein in the formation of the electrode pattern, a laminated structure is formed in which a Cu layer is disposed on the upper end portion of the electrode pattern and at least one different conductive layer is disposed on the lower end side.

  Further, the present invention provides a laminated structure in which a Cu layer is disposed at the upper end of the electrode pattern, a barrier conductive layer for solder diffusion is disposed at the lower end, and a barrier conductive layer for etching removal of the substrate is disposed at the lower end. The present invention relates to a method for manufacturing the wiring board to be formed.

  According to the present invention, it is possible to realize a high density and fine wiring of a wiring board corresponding to an increase in the number of terminals of a semiconductor device and a narrow pitch, and an outside of the wiring board corresponding to a miniaturization and a high density of a system. A narrow pitch of the electrodes can be realized. Furthermore, a wiring board with excellent mounting reliability can be provided, and a semiconductor package with high performance and excellent reliability can be realized.

  A preferred embodiment of a wiring board for mounting a semiconductor device (hereinafter referred to as “wiring board” as appropriate) and a semiconductor package of the present invention, and a manufacturing method thereof will be described.

[Wiring board]
A schematic cross-sectional view of one embodiment of the wiring board of the present invention is shown in FIG.

  The wiring board according to the present embodiment includes an insulating layer 6, a wiring 8 provided on the upper surface of the insulating layer 6, an electrode 5 provided on the lower surface side of the insulating layer 6, and an upper surface of the electrode 5. A via 7 provided in the insulating layer 6 so that the electrode 5 and the wiring 8 are electrically connected to each other, and a support 16 is provided on the lower surface of the insulating layer 6.

  In the present embodiment, the entire periphery of the side surface of the electrode 5 is in contact with the insulating layer 6, and the lower surface of the electrode 5 is in the same plane as the lower surface of the insulating layer 6. That is, the electrode 5 is embedded in the insulating layer 6 so that the lower surface thereof is exposed from the insulating layer 6. According to the present invention, since the electrode 5 is embedded in the insulating layer 6 in this way, stress and strain on the electrode 5 can be relieved and stress concentration can be reduced, and mounting on an external board or device is possible. A highly reliable wiring board can be obtained.

  The electrode on the lower surface side of the insulating layer in the wiring board of the present invention may be provided so that at least the periphery of the side of the upper end of the electrode is in contact with the insulating layer and at least the lower surface of the electrode is not in contact with the insulating layer. In addition to the structure shown, the structure shown in FIGS. 2A and 2B may be used.

  In the structure shown in FIG. 2A, the insulating layer 6 has a recess 41 on its lower surface side, and the electrode 5 is provided in the insulating layer 6 so that its lower surface forms the bottom surface of the recess. According to this structure, the stress and strain on the electrode 5 are relieved and the stress concentration is reduced, and a wiring board having excellent mounting reliability to an external board or device can be obtained. Even if it is arranged, solder balls can be easily provided on each electrode 5.

  In the structure shown in FIG. 2B, the lower end of the electrode 5 protrudes from the lower surface of the insulating layer 6. According to this structure, stress and strain on the electrode 5 are alleviated, stress concentration is reduced, and a wiring board having excellent mounting reliability to an external board or device can be obtained. The connection reliability can be improved.

  FIG. 3 is a schematic sectional view showing a structure in which solder balls 31 are provided on the electrodes 5 in the configuration shown in FIG. If necessary, a solder resist 17 may be provided around the electrode 5. This solder resist 17 can be similarly provided in the structure shown in FIGS. 2 (a) and 2 (b). The solder resist can be formed from a normal resist material. By providing such a solder resist, it is possible to prevent rolling at the time of solder ball installation and improve workability, and after installation, stress concentration at the joint between the solder ball and the electrode can be reduced, Installation stability can be improved.

  The electrode on the lower surface side of the insulating layer in the wiring board of the present invention can be formed of various conductive materials such as metals, alloys such as Cu, Ag, Au, Ni, etc. Or a laminated structure including a reinforcing layer of electrode strength. As an electrode having a laminated structure, an electrode in which Au, Ni, and Cu are laminated in this order from the lower end side (Au / Ni / Cu electrode), and an electrode in which Ni, Au, Ni, and Cu are laminated in this order from the lower end side (Ni / Au / Ni / Cu electrode), an Au / Ni / Cu electrode from which the Ni layer at the bottom end is removed from the Ni / Au / Ni / Cu electrode, and Cu, Ag and Cu in this order from the bottom end side A laminated electrode (Cu / Ag / Cu electrode) can be mentioned. In the electrode, the intermediate Ni layer functions as a solder diffusion preventing layer. In the Cu / Ag / Cu electrode, the Ag layer functions as a reinforcing layer that improves the strength of the electrode.

  The support provided on the surface of the insulating layer in the wiring board of the present invention is provided to reinforce the wiring board. By providing a support on the wiring board, deformation such as warping of the wiring board can be suppressed, mounting reliability of the semiconductor chip (device) on the wiring board, mounting reliability of the wiring board or semiconductor package on the external board, etc. Can be secured.

  In the embodiment shown in FIG. 1, the support 16 is provided on the lower surface of the insulating layer 6 and is provided in a frame shape around the insulating layer 6. FIG. 4 shows a schematic bottom view (bottom view) of the wiring board of the present embodiment. In addition to the frame shape as shown in FIG. 4, the shape of the support in the wiring board of the present invention may be provided in a region other than the electrode 5 (as the electrode 5 is exposed) as a lattice shape or a mesh shape. Further, the support in the wiring board of the present invention may be provided on the upper surface of the wiring board as long as the semiconductor device can be mounted. Further, in this case, when a sufficient strength can be ensured by the support provided on the upper surface, a wiring board having no support on the lower surface can be provided.

  Further, in order to mount a wiring board or a semiconductor package having a semiconductor chip mounted on the wiring board, the electrode 5 needs to be exposed. If a process for exposing the electrode 5 can be performed later, the wiring 5 It is good also as a form which provided the support body (support plate) in the lower surface whole surface of the board | substrate. In this case, after the semiconductor chip is mounted on the wiring board and the semiconductor package is formed, the electrode 5 can be exposed by selectively removing the support in a frame shape or the like. Since the support is formed on the entire lower surface, the flatness of the wiring board is more sufficiently secured when the semiconductor chip is mounted, and the mounting reliability of the semiconductor chip can be improved. When the support for exposing the electrode 5 is removed, if the produced semiconductor package has sufficient strength to ensure sufficient mounting reliability to an external board without the support, wiring The entire support on the lower surface of the substrate may be removed.

  The support material is a material that can give the above-described sufficient strength to the wiring board and has heat resistance that can withstand heat treatment when mounting the semiconductor chip on the wiring board or mounting the wiring board or semiconductor package. Although not limited, a conductive material is preferable from the viewpoint of manufacturing electrodes, vias, and wiring. As such a conductive material, a metal made of stainless steel, copper, copper alloy, aluminum, nickel, or the like is preferable because it has sufficient strength and is inexpensive and easy to process.

  The insulating layer in the wiring board of the present invention can be formed as a single layer made of a single material, but may have a laminated structure in which two or more different materials are laminated as shown in FIG. Good.

  This insulating layer is preferably 10 μm or more from the viewpoint of mounting reliability of the semiconductor chip on the wiring board and mounting reliability of the wiring board or semiconductor package on the external board.

  The insulating layer may be made of an epoxy resin, a resin obtained from a acrylate compound having a fluorene skeleton, a polyimide resin, polybenzoxazole, polybenzocyclobutene, or a mixture of two or more thereof. Various insulating resins can be applied. In particular, it is made of an insulating material (hereinafter abbreviated as “insulating material A” as appropriate) having a film strength of 70 MPa or more, a breaking elongation of 5% or more, a glass transition temperature of 150 ° C. or more, and a thermal expansion coefficient of 60 ppm or less. A layer film or at least a single layer film made of an insulating material having an elastic modulus of 10 GPa or more, a thermal expansion coefficient of 30 ppm or less, and a glass transition temperature of 150 ° C. or more (hereinafter abbreviated as “insulating material B” as appropriate). Is preferred. These single layer films are preferably 10 μm or more. Here, the film strength and elongation at break are values measured by a tensile test of an insulating material in accordance with JIS K 7161 (tensile property test), and the elastic modulus is a strain amount of 0.1% based on the tensile test result. It is a calculated value from the intensity at. The coefficient of thermal expansion is a value measured by a TAM method in accordance with JIS C 6481, and the glass transition temperature is a value measured by a DMA method in accordance with JIS C 6481.

  Examples of the insulating material A include an epoxy resin (manufactured by Hitachi Chemical; MCF-7000LX), a polyimide resin (manufactured by Nitto Denko; AP-6832C), a benzocyclobutene resin (manufactured by Dow Chemical; Cyclotene 4000 series), A polyphenylene ether resin (Asahi Kasei; Zylon), a liquid crystal polymer film (Kuraray; LCP-A), a stretched porous fluororesin-impregnated thermosetting resin (Japan Gore-Tex; MICROLAM600) and the like are suitable.

  Examples of the insulating material B include a glass cloth impregnated epoxy resin (manufactured by Hitachi Chemical; MCL-E-679), an aramid non-woven fabric impregnated epoxy resin (manufactured by Shin-Kobe Electric Machinery; EA-541), and a stretched porous fluororesin impregnated thermosetting resin. (Japan Gore-Tex; MICROLAM400) is suitable.

  When the insulating layer in the wiring board of the present invention has a laminated structure, it is preferable to have a layer made of the insulating material A or B, but the material constituting the other layer is obtained from a both-end acrylate compound having a fluorene skeleton. It is preferable to use a resin (hereinafter referred to as “fluorene resin” as appropriate). Moreover, in order to further add or improve a desired characteristic, you may use the resin mixture which has as a main component the fluorene-type resin which mixed other resin. As such a resin mixture, it is preferable to contain 80% by mass or more of a fluorene resin. For example, a resin mixture containing 5 to 20% by mass, preferably about 5 to 10% by mass of an epoxyoxy resin is suitably used. be able to. A fluorene resin has excellent characteristics such as heat resistance, low dielectric constant, low thermal expansion coefficient, low water absorption, and is suitable as an insulating material used for high-density and fine wiring boards. This is disclosed in Japanese Patent No. 214141.

  Examples of such a resin include a resin obtained from a both-terminal acrylate compound having a 9,9-diphenylfluorene skeleton represented by the following general formula (I).

  In the formula, each R independently represents a hydrogen atom or a lower alkyl group such as methyl, ethyl, n-propyl or isopropyl, and n represents an integer of 0 to 20.

  By using the resin material as described above for the insulating layer, it is possible to obtain a wiring substrate having excellent film strength and elongation at break, and particularly excellent crack resistance. A semiconductor chip can be mounted.

  The inventors conducted a pressure cooker test (temperature 121 ° C., humidity 100%) on the wiring board having an insulating layer made of these resins, and no delamination of the resin was observed even after 192 hours had elapsed. .

  Further, a temperature cycle test (one cycle at −65 ° C. for 30 minutes and 150 ° C. for 30 minutes) is performed on the semiconductor package shown in FIG. As a result, no disconnection or cracking occurred even after 1000 cycles.

Resin a; film strength 78 MPa, elongation at break 8.5%, glass transition temperature 175 ° C., thermal expansion coefficient 55 ppm, elastic modulus 2.5 GPa,
Resin b; film strength 180 MPa, breaking elongation 30%, glass transition temperature 385 ° C., thermal expansion coefficient 28 ppm, elastic modulus 6.0 GPa,
Resin c; glass transition temperature 180 ° C., thermal expansion coefficient 11 ppm, elastic modulus 11 GPa,
Resin d: Glass transition temperature 200 ° C., thermal expansion coefficient 18 ppm, elastic modulus 12 GPa.

  The wiring board of the present invention can have a multilayer wiring structure in which one or more sets of insulating layers and wirings formed on the upper surface of the insulating layer are alternately and sequentially formed on the upper surface of the insulating layer provided with the wiring. . FIG. 6 shows an embodiment having a multilayer wiring structure in which an insulating layer and a wiring are further stacked on the structure shown in FIG. 1 as one embodiment. An insulating layer 12 is provided on the insulating layer 6 so as to cover the wiring 8, a wiring 13 is provided on the insulating layer 12, and a via is formed in the insulating layer 12 so that the wiring 13 and the wiring 8 are electrically connected. Is provided. In such a multilayer wiring structure, it is preferable that at least one of the insulating layers is made of the insulating material A or B, and it is preferable that the other insulating layer is made of the fluorene-based resin.

As in the embodiment shown in FIG. 7, the wiring board of the present invention is provided with a dielectric layer 93 on the upper surface of a part of the plurality of electrodes 5 provided on the lower surface side, and vias are formed on the dielectric layer 93. It is also possible to provide a conductor 7 and have a capacitor composed of the electrode 5, the dielectric layer 93, and the via conductor 7. By forming such a capacitor, transmission noise can be reduced, and an optimal wiring board for high speed can be obtained. Materials for the dielectric layer include titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), silicon oxide (SiO ₂ ), niobium oxide (Nb ₂ O ₅ ), BST _{(Ba x Sr 1-x TiO} 3), PZT (PbZr x Ti 1-x O 3), PLZT (Pb 1-y La y Zr x Ti 1-x O 3), perovskite such as SrBi ₂ Ta ₂ O ₉ Mention may be made of system materials.

  As shown in FIGS. 8A and 8B, the wiring board of the present invention has a configuration in which the above-described wiring board structure is formed on both surfaces of a laminated board on which two supporting boards 1 are bonded. You can also. In this embodiment, two support substrates are separated into two wiring substrates or semiconductor packages before or after mounting the semiconductor chip, and the support substrate 1 is removed so that the electrodes 5 are exposed as described above, It can be configured to be mountable on another board or the like.

[Semiconductor package]
The semiconductor package of the present invention can be formed by mounting a semiconductor chip on the upper surface of the wiring board of the present invention. The electrical connection portion such as a pad of a semiconductor chip and the wiring of the wiring board can be electrically connected by various methods, and examples thereof include a flip chip method, a wire bonding method, and a tape bonding method.

  FIG. 9 shows an embodiment using a flip chip method. As shown in FIG. 9A, the semiconductor package of the present invention can be configured such that the substrate 1 is provided on the entire lower surface of the wiring substrate. In this case, the substrate 1 is removed so that the electrode 5 is exposed when mounted on another board or the like. As a form in which the electrode 5 is exposed, as shown in FIG. 9B, the substrate 1 is processed and left on the lower surface of the insulating layer 6 in a frame shape, a lattice shape, or a mesh shape, and a support for reinforcing the semiconductor package. 16 can be used. When sufficient strength can be ensured without forming such a support, the entire substrate 1 may be removed to form as shown in FIG. As shown in FIGS. 9A to 9C, when the semiconductor chip is encapsulated with a mold resin, the mold resin functions as a support, and therefore sufficient strength is ensured without providing the support 16. It is possible.

  Further, in the semiconductor package of the present invention, as in the embodiment shown in FIG. 9, the pad 19 provided on the semiconductor chip 18 and the wiring 8 of the wiring structure 9 corresponding to the wiring substrate of the present invention are, for example, metal Electrical connection can be made via the bumps 20. At that time, an underfill resin 21 can be filled between the semiconductor chip 18 and the wiring structure 8 as necessary. Further, the semiconductor chip on the wiring structure 9 can be encapsulated by the transfer molding method using the mold resin 22. Alternatively, in order to increase thermal radiation, as shown in FIG. 9D, after the heat sink 33 is provided on the semiconductor chip 18, it can be sealed by another sealing method.

  Moreover, as shown in FIG. 10, the semiconductor package of this invention can be made into the form by which the semiconductor chip was mounted in both surfaces. Such a form can be formed by mounting semiconductor chips on both sides of the wiring board having the form described with reference to FIG. In this semiconductor package, when mounting on another board or the like, the laminated substrate on which the two substrates are bonded is separated into two semiconductor packages, and the electrodes 5 of the wiring structure 9 are respectively formed as described above. The substrate 1 can be removed so that the substrate is exposed, and can be mounted on another board or the like.

[Manufacturing method of wiring board and semiconductor package]
FIG. 11 is a sectional process diagram of an embodiment of the manufacturing method of the present invention.

  First, as shown in FIG. 11A, a resist layer for forming an electrode pattern is formed on a substrate 1 made of a metal plate such as stainless steel, Cu, Cu alloy, Al, or Ni, and this resist layer is patterned. Thus, a resist mask 2 having an opening 3 corresponding to a predetermined electrode pattern is formed.

  Next, as shown in FIG. 11B, the substrate 1 is energized, and the plating layer 4 is formed on the substrate 1 in the opening 3 by electrolytic plating. Next, as shown in FIG. 11C, the resist mask 2 is removed, leaving a plating layer 4 having a predetermined electrode pattern corresponding to the opening pattern of the resist mask 2 on the substrate 1, and this being applied to the electrode 5. And Thus, for the formation of the electrode 5, it is desirable to use an electrolytic plating method capable of depositing a dense metal from the viewpoint of reliability. However, the plating layer 4 is deposited on the opening 3 by the electroless plating method. Thus, the electrode 5 can also be formed.

  Next, as shown in FIG. 11D, an insulating layer 6 is formed on the substrate 1 on which the electrode 5 is formed, and a via hole reaching the electrode 5 is formed in the insulating film 6 by a photolithography method or a laser processing method. 7a is formed.

  As the material of the insulating layer 6, various insulating resins such as epoxy resins, the above-mentioned fluorene resins, polyimide resins, polybenzoxazole, polybenzocyclobutene can be applied. In order to improve the mounting reliability, the insulating layer 6 can be composed of a plurality of resin layers, for example, as shown in FIG.

  Next, as shown in FIG. 11E, a conductor layer is formed on the insulating layer 6 so as to bury the via hole 7a by sputtering, electroless plating, electrolytic plating, or the like. The wiring layer 8 is formed by patterning by photolithography. Alternatively, after a conductor layer is formed so as to fill the via hole 7a, an unnecessary conductor layer on the upper surface of the insulating layer 6 is removed to leave the conductor only in the via hole 7a, and then the via 7 is formed. It is also possible to form the wiring layer 8 by forming the same kind or different kinds of conductor layers connected to the vias and patterning them.

  Although the wiring board of this embodiment can be formed as described above, in order to make this wiring board mountable on another board or the like, for example, as shown in FIG. 1 and FIG. The substrate 1 is selectively etched to expose the electrodes 5 for electrical connection to the outside, and the substrate left in the form of a frame on the outer periphery of the insulating layer 6 is used as the support 16. As described above, the support 16 can be formed in a lattice shape or a mesh shape in addition to the frame shape.

  Thereafter, if necessary, a solder resist 17 may be formed around the electrode 5 in order to mount a solder ball on the electrode 5 as shown in FIG.

  Further, after forming the wiring layer 8, as shown in FIG. 12, a cover coat 10 is formed on the insulating layer 6 so as to cover the wiring layer 8, and the semiconductor chip is electrically connected to a predetermined position of the cover coat 10. An opening can also be provided as the pad portion 11 for this purpose. The pad portion 11 can be used as an electrode pad by burying a conductor in the opening.

  Further, after forming the wiring layer 8, as shown in FIG. 6, an insulating layer 12 is formed on the insulating layer 6 so as to cover the wiring layer 8, and vias and insulation are formed in the insulating layer 12 in the same manner as described above. A wiring layer 13 can be formed on the layer 12 to provide a multilayer wiring structure. By repeating this process, the number of layers can be increased.

  According to such a manufacturing method of the present embodiment, it is very easy to reduce the pitch and increase the accuracy of the electrodes 5. In addition, since the electrode 5 has a structure embedded in the insulating film 6, stress and strain on the electrode 5 can be relieved and stress concentration is reduced, so that mounting reliability with an external board or device is also excellent. A wiring board can be manufactured. If a semiconductor chip is mounted on the wiring board of this embodiment to form a semiconductor package, the mounting reliability of the semiconductor package with an external board or device can be improved.

  Further, since the substrate 1 used for forming the electrode 5 can be left as the support 16 of the wiring board in the removal process for exposing the electrode 5, a process of providing a separate support is not required, which is simple. By this method, it is possible to manufacture a wiring board that is excellent in handleability and excellent in chip mounting reliability and mounting reliability on other boards.

  A wiring board having a wiring structure formed on both sides of a laminate as shown in FIG. 8 can be manufactured, for example, as follows.

  First, as shown in FIG. 13A, a laminated plate 25 in which a first substrate and a second substrate are bonded together is prepared. For example, an epoxy-based or polyimide-based heat-resistant adhesive resin is arranged around one substrate 1 (adhesion region 24), and the other substrate is bonded and fixed to the surface thereof.

  Next, in the same manner as described above, resist layers are respectively formed on both surfaces of the laminate, and these are patterned to form opening patterns corresponding to predetermined first and second electrode patterns. Next, the substrate 1 is energized, and a plating layer is formed in the opening of the resist layer by electrolytic plating. Subsequently, the resist layer is removed, and the first and second electrodes 5 are respectively applied to both surfaces of the laminated plate 25. Form. Next, in the same manner as described above, the insulating layers 6 are respectively formed on both surfaces of the laminated plate 25, and then via holes are respectively formed in these insulating layers, and then the conductive film is embedded so as to fill these via holes. Then, these are patterned to form the wiring 8 (FIG. 13B). Thereafter, the wiring board 26 is cut at the position of the dotted line shown in FIG. 13B (inside the adhesion region 24), so that the first and second substrates 1 bonded together as shown in FIG. 13C. By separating the two, two wiring boards can be obtained. Alternatively, a semiconductor chip is mounted on at least one surface of the wiring substrate, and a semiconductor package is formed by mounting the semiconductor chip on both surfaces as shown in FIG. Two semiconductor packages can be obtained by separating the two.

  According to such a manufacturing method, since a process can be simplified, productivity can be improved and cost reduction can be achieved.

[Manufacturing method of wiring board having laminated electrodes]
FIG. 14 shows an embodiment of a method for manufacturing a wiring board having laminated electrodes.

  In the manufacturing method of the present embodiment, a stainless steel plate is used as the substrate 1, and an electrode having a three-layer structure in which an Au plating layer, a Ni plating layer, and a Cu plating layer are laminated in this order from the lower surface side of the wiring substrate is formed.

  First, as shown in FIG. 14A, a resist layer for forming a plating film is formed on a substrate 1 made of stainless steel (for example, made by Nisshin Steel; SUS304), and this resist layer is patterned to form a predetermined pattern. A resist mask 2 having an opening 3 corresponding to the electrode pattern is formed.

  Here, the preferable board thickness of the board | substrate 1 is 0.1 mm-1.0 mm, More preferably, it is 0.2 mm-0.8 mm. The reason is that if the plate thickness is too thin, warping is likely to occur in the manufacturing process of the wiring board, and the precision is lowered and it becomes difficult to form fine wiring, and if the plate thickness is too thick. This is because the handling property is lowered due to the increased weight.

  Next, as shown in FIG. 14B, an Au plating layer 4a, a Ni plating layer 4b, and a Cu plating layer 4c are arranged in this order on the substrate 1 in the opening 33 by an electrolytic plating method or an electroless plating method. Form with. The thickness of each plating layer is preferably 0.3 μm to 3 μm for the Au plating layer, 1 μm to 7 μm for the Ni plating layer, and 5 μm or more for the Cu plating layer.

  Next, as shown in FIG. 14C, the resist mask 2 is removed from the substrate 1, leaving a plating layer having a predetermined electrode pattern corresponding to the opening pattern of the resist mask 2 on the substrate 1, The electrode 5 has a three-layer structure of Au / Ni / Cu.

  Next, as shown in FIG. 14D, an insulating layer 6 is formed on the substrate 1 on which the electrode 5 is formed, and a via hole 7 a reaching the electrode 5 is formed in the insulating layer 6.

  Next, as shown in FIG. 14E, a conductor layer is formed on the insulating layer 6 so as to fill the via hole 7a, and this conductor layer is patterned to form a wiring layer 8.

  Finally, as shown in FIG. 14F, a predetermined region of the substrate 1 is removed from the lower surface side by etching to expose the electrode 5 and simultaneously form a support 16.

  In the present embodiment having the electrode 5 having a three-layer structure of Au / Ni / Cu, peeling is unlikely to occur because of sufficient adhesion at the interface between the stainless steel substrate 1 and the Au plating layer. In addition, the Au plating layer is less likely to diffuse into the substrate 1 and the Ni plating layer depending on the thermal history during manufacturing such as the formation of the insulating layer 6. For this reason, the Au plating layer can function sufficiently as a barrier metal when the substrate 1 is etched, and a wide range of etching conditions can be selected. Therefore, the manufacturing yield, productivity, and handleability can be improved. Further, when the solder ball is mounted on the electrode 5 and electrically connected to an external board or device, the Ni plating layer functions as a solder diffusion preventing layer, so that the mounting reliability can be improved.

  As a method for manufacturing a wiring board having other laminated electrodes, a Cu plate or a Cu alloy plate (for example, made by Kobe Steel; KFC) is used as the substrate 1, and a Ni plating layer, an Au plating layer, An electrode having a four-layer structure in which a Ni plating layer and a Cu plating layer are laminated in this order can be formed. This structure can be formed in the same manner as the above method except that the substrate 1 and the electrode structure are different.

  The thickness of the substrate 1 is preferably 0.1 mm to 1.0 mm as in the above method, the thickness of the Ni plating layer from the substrate 1 side is 1 μm or more, the thickness of the Au plating layer is 0.3 μm to 3 μm, Ni The thickness of the plating layer is preferably 1 to 7 μm, and the thickness of the Cu plating layer is preferably 5 μm or more.

  The substrate 1 made of Cu or Cu alloy (hereinafter referred to as “Cu substrate” as appropriate) can be easily etched with a copper chloride or iron chloride etching solution, and thus has an advantage of further improving productivity.

  Moreover, according to the present inventors' earnest study, since the Cu substrate has different characteristics from the substrate made of stainless steel, when an Au plating layer is formed directly on the Cu substrate, the manufacturing process of the wiring substrate is performed. It has been found that due to the thermal history at, metal diffusion occurs between the Cu substrate and the Au plating layer and does not function as a barrier metal during etching. As a result of extensive studies, it has been found that this metal diffusion problem can be solved by forming another plating layer on the Cu substrate via the Ni plating layer 52. Furthermore, since the Ni layer of the intermediate layer also functions as a solder diffusion prevention layer, it has been found that the electrode 5 having a Ni / Au / Ni / Cu plated multilayer structure is optimal as an electrode of a wiring board.

  As another embodiment, a Cu / Ag / Cu electrode can also be formed in the same manner as described above, and the substrate at that time is not particularly limited, but for example, a Cu substrate or a stainless steel plate can be used.

[Method of manufacturing a wiring board having a concave electrode structure]
As shown in FIG. 2A, the electrode in the wiring board of the present invention can be structured to be exposed from the bottom surface of the recess 41 provided on the lower surface of the insulating layer 6. For example, as shown in FIG. 15, this structure can be obtained by etching and removing the electrode 5 from the lower surface side of the wiring substrate (insulating layer 6) by a predetermined thickness to form a recess 41. As shown in FIG. 15, in the case of an electrode having a multi-layer structure composed of a plurality of different material layers, it can be easily removed by etching in units of a predetermined thickness due to the difference in etching rate depending on the material. For example, in the electrode 5 having the Ni / Au / Ni / Cu plating multilayer structure, only the Ni plating layer can be removed by etching to form a structure that is recessed with respect to the lower surface of the insulating layer (lower surface of the wiring board). With this structure, solder balls can be easily mounted even when the electrodes 5 have a narrow pitch.

[Method of manufacturing a wiring board having a convex electrode structure]
The electrode in the wiring board of the present invention may have a structure protruding from the lower surface of the insulating layer 6 as shown in FIG. This structure can be formed as follows, for example.

  First, as shown in FIG. 16A, a resist layer for forming an electrode pattern is formed on a substrate 1 made of a metal plate, and the resist layer is patterned to form an opening 3 corresponding to a predetermined electrode pattern. A resist mask 2 is formed.

  Next, as shown in FIG. 16B, the upper surface of the substrate 1 is etched using the resist mask 2 as an etching mask to form a recess 51 corresponding to the opening 3 of the resist mask 2 on the upper surface of the substrate 1.

  Next, as shown in FIG. 16C, a metal is deposited on the exposed substrate 1 by a plating method to form a plating layer 4 in the recess 51 and the opening 3. Next, as shown in FIG. 16D, the resist mask 2 is removed, leaving a plating layer 4 having a predetermined electrode pattern corresponding to the opening pattern of the resist mask 2 on the substrate 1, and this is applied to the electrode 5. And

  Next, as shown in FIG. 16E, an insulating layer 6 is formed on the substrate 1 on which the electrode 5 is formed, and a via hole reaching the electrode 5 is formed in the insulating layer 6 by photolithography or laser processing. 7a is formed.

  Next, as shown in FIG. 16 (f), a conductor layer is formed on the insulating layer 6 so as to fill the via hole 7a by sputtering, electroless plating, electrolytic plating, or the like. The wiring layer 8 is formed by patterning by photolithography.

  Thereafter, as shown in FIG. 2B, the substrate 1 in a predetermined region is selectively etched from the lower surface side to expose the electrode 5 for electrical connection to the outside, and for example, on the outer periphery of the insulating layer 6 The substrate 16 is left as a frame to form a support 16.

  A convex electrode can be easily formed as described above. Note that by adjusting the etching amount in the step shown in FIG. 16B, the protruding size of the electrode from the lower surface of the insulating layer can be adjusted.

[Method of manufacturing a wiring board having a capacitor]
As described above, the wiring board of the present invention may be configured to have a capacitor as shown in FIG. 7, for example. A configuration having a capacitor can be formed as follows, for example.

  First, as shown in FIG. 17A, an electrode 92 is formed on a substrate 1 according to a method using the above-described plating method.

  Next, as shown in FIG. 17B, a dielectric layer 93 is formed on a part of the plurality of electrodes by, for example, a sputtering method using a metal mask.

  Next, as shown in FIG. 17C, an insulating layer 94 is formed on the substrate 1 on which the electrode 92 and the dielectric layer 93 are formed, and via holes are formed on the insulating layer 94 by photolithography or laser processing. 95a is formed.

  Next, as shown in FIG. 17D, a conductor layer is formed on the insulating film 94 so as to fill the via hole 95a, and the conductor layer is patterned to form a wiring layer 96. Next, as shown in FIG.

  Thereafter, as shown in FIG. 17E, the substrate 1 in a predetermined region is selectively etched from the lower surface side to expose the electrode 92 for electrical connection with the outside, and to form a support 97.

  Since the dielectric layer 93, the electrode 92 below the dielectric layer 93, and the via conductor layer 95 on the dielectric layer 93 have a function as a capacitor, transmission noise can be reduced. As a result, it is possible to obtain a wiring board that is optimal for speeding up.

It is a schematic sectional drawing of one Embodiment of the wiring board for semiconductor device mounting of this invention. It is a schematic sectional drawing of other embodiment of the wiring board for semiconductor device mounting of this invention. It is a schematic sectional drawing of other embodiment of the wiring board for semiconductor device mounting of this invention. 1 is a schematic bottom (bottom) view of an embodiment of a wiring board for mounting a semiconductor device of the present invention. It is a schematic sectional drawing of other embodiment of the wiring board for semiconductor device mounting of this invention. It is a schematic sectional drawing of other embodiment of the wiring board for semiconductor device mounting of this invention. It is a schematic sectional drawing of other embodiment of the wiring board for semiconductor device mounting of this invention. It is a schematic sectional drawing of other embodiment of the wiring board for semiconductor device mounting of this invention. It is a schematic sectional drawing of embodiment of the semiconductor package of this invention. It is a schematic sectional drawing of other embodiment of the semiconductor package of this invention. It is sectional process drawing which shows one Embodiment of the manufacturing method of the wiring board for semiconductor device mounting of this invention. It is a schematic sectional drawing of other embodiment of the wiring board for semiconductor device mounting of this invention. It is sectional process drawing which shows other embodiment of the manufacturing method of the wiring board for semiconductor device mounting of this invention. It is sectional process drawing which shows other embodiment of the manufacturing method of the wiring board for semiconductor device mounting of this invention. It is sectional process drawing which shows other embodiment of the manufacturing method of the wiring board for semiconductor device mounting of this invention. It is sectional process drawing which shows other embodiment of the manufacturing method of the wiring board for semiconductor device mounting of this invention. It is sectional process drawing which shows other embodiment of the manufacturing method of the wiring board for semiconductor device mounting of this invention. It is sectional process drawing which shows the manufacturing method of the conventional wiring board for semiconductor device mounting.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Board | substrate 2 Resist mask 3 Opening part 4 Plating layer 5 Electrode 6 Insulating layer 7 Via 7a Via hole 8 Wiring layer 9 Wiring structure 10 Cover coat 11 Pad part 12 Insulating layer 13 Wiring layer 16 Support body 17 Solder resist 18 Semiconductor chip 19 Pad 20 Metal bump 21 Underfill resin 22 Mold resin 24 Adhesion area 25 Laminate board 26 Wiring board 31 Solder ball 32 Dielectric layer 33 Heat sink 41 Recess 51 Recess 91 Substrate 92 Electrode 93 Dielectric layer 94 Insulating layer 95 Via conductor 96 Wiring 97 Support 101 Metal plate 102 Insulating layer 103 Via hole 104 Wiring pattern 105 Flip chip pad part 106 Insulating layer 107 Substrate reinforcement 108 External electrode terminal

Claims (15)

Forming an electrode pattern on the substrate; forming an insulating layer on the substrate so as to cover the electrode pattern; forming a via hole reaching the electrode pattern in the insulating layer; and the via hole Forming a conductor layer on the insulating layer so as to embed the semiconductor layer, patterning the conductor layer to form a wiring pattern, and mounting a semiconductor device on the wiring pattern. A manufacturing method comprising:
In the step of forming the electrode pattern, a resist layer having an opening pattern corresponding to the electrode pattern is formed on the substrate, and the substrate is etched using the resist layer as a mask to correspond to the opening pattern of the resist layer. A method of manufacturing a semiconductor package, wherein a recess is formed on the upper surface of the substrate, and a conductor is provided in the recess and the opening pattern to form the electrode pattern.   2. The manufacturing of a semiconductor package according to claim 1, wherein in the step of forming the electrode pattern, a conductive substrate is used as the substrate, and the electrode pattern is formed by depositing a metal in the recess and the opening pattern by a plating method. Method.   After the electrode pattern is formed, the method further includes a step of forming a dielectric layer on the predetermined electrode pattern, and is embedded in the dielectric layer, the electrode pattern under the dielectric layer, and the via hole reaching the dielectric layer. 3. The method of manufacturing a semiconductor package according to claim 1, wherein a capacitor is formed with the conductive layer formed.   The method of manufacturing a semiconductor package according to claim 1, further comprising a step of selectively removing the substrate and exposing the electrode pattern after the step of mounting the semiconductor device.   4. The method of manufacturing a semiconductor package according to claim 1, further comprising a step of selectively removing the substrate to expose the electrode pattern and using a remaining portion of the substrate as a support. A step of preparing a laminated plate formed by bonding a first substrate and a second substrate, a first electrode pattern is formed on the first substrate, and a second electrode pattern is formed on the second substrate. Forming a first insulating layer on the laminated plate so as to cover the first electrode pattern and the second electrode pattern, respectively, and forming the first insulating layer on the first insulating layer. Forming a via hole reaching the second electrode pattern, forming a via hole reaching the second electrode pattern in the second insulating layer, and the first and second insulating layers so as to fill the via hole. Forming a conductive layer on each of them, patterning the conductive layer to form first and second wiring patterns, and forming a semiconductor device on at least one of the first and second wiring patterns Mounting process A method of manufacturing a semiconductor package that,
In the step of forming the first and second electrode patterns, a resist layer having opening patterns corresponding to the first and second electrode patterns is formed on the first and second substrates, respectively, and the resist Using the layer as a mask, the first and second substrates are etched to form a recess corresponding to the opening pattern of the resist layer on the upper surface of the first and second substrates, and a conductive layer is formed in the recess and the opening pattern. A method of manufacturing a semiconductor package, comprising providing a body to form the first and second electrode patterns.   The method of manufacturing a semiconductor package according to claim 6, further comprising a step of separating the first substrate and the second substrate. A step of preparing a laminated plate formed by bonding a first substrate and a second substrate, a first electrode pattern is formed on the first substrate, and a second electrode pattern is formed on the second substrate. Forming a first insulating layer on the laminated plate so as to cover the first electrode pattern and the second electrode pattern, respectively, and forming the first insulating layer on the first insulating layer. Forming a via hole reaching the second electrode pattern, forming a via hole reaching the second electrode pattern in the second insulating layer, and the first and second insulating layers so as to fill the via hole. Forming a conductive layer on each of them, patterning the conductive layer to form first and second wiring patterns, separating the first substrate and the second substrate; Said first substrate separated or front Mounting a semiconductor device on at least one of the wiring pattern of the second substrate, a manufacturing method of a semiconductor package having,
In the step of forming the first and second electrode patterns, a resist layer having opening patterns corresponding to the first and second electrode patterns is formed on the first and second substrates, respectively, and the resist Using the layer as a mask, the first and second substrates are etched to form a recess corresponding to the opening pattern of the resist layer on the upper surface of the first and second substrates, and a conductive layer is formed in the recess and the opening pattern. A method of manufacturing a semiconductor package, comprising providing a body to form the first and second electrode patterns.   After separating the first substrate and the second substrate, the first and second substrates are selectively removed to expose the first and second electrode patterns and the first and second substrates. The method for manufacturing a semiconductor package according to claim 7, further comprising a step of using the remaining portions of the substrate as a support.   In the step of forming the first and second electrode patterns, a conductive substrate is used as the first and second substrates, and a metal is deposited in the recess and the opening pattern by a plating method to form the first and second substrates. The method for manufacturing a semiconductor package according to claim 6, wherein the second electrode pattern is formed.   11. The method of manufacturing a semiconductor package according to claim 2, wherein, in forming the electrode pattern, a stacked structure is formed in which a Cu layer is disposed on an upper end portion of the electrode pattern and at least one different conductive layer is disposed on a lower end side.   3. The electrode pattern is formed by forming a laminated structure in which a Cu layer is disposed at an upper end portion thereof, a barrier conductive layer for diffusion of solder is disposed at a lower end side, and a barrier conductive layer for etching removal of the substrate is disposed at a lower end side. Or a method for producing a semiconductor package according to 10;   11. The method of manufacturing a semiconductor package according to claim 2, wherein the substrate is a stainless steel plate, and the electrode pattern is formed by laminating an Au plating layer, a Ni plating layer, and a Cu plating layer in this order on the substrate. .   The substrate is a Cu plate or a Cu alloy plate, and the electrode pattern is formed by laminating a Ni plating layer, an Au plating layer, a Ni plating layer, and a Cu plating layer in this order on the substrate. The manufacturing method of the semiconductor package of description.   The method of manufacturing a semiconductor package according to claim 2, wherein the electrode pattern is formed by stacking a Cu plating layer, an Ag plating layer, and a Cu plating layer in this order on the substrate.

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