JP2009015101A - Array substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an array substrate which has a narrowed frame area and is excellent in reliability of wiring by suppressing the occurrence of voids in a Cu plating layer. <P>SOLUTION: The array substrate is prepared by forming a thin-film transistor on a display part H. The Cu plating layer 17b is connected to a source area 13A and a drain area 13B of the thin-film transistor via a contact hole 18. Aspect ratio of the contact hole 18 is one or more. In the contact hole 18, a Cu seed layer 17a is formed only near the bottom part. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an array substrate used for a liquid crystal display panel or the like, and more particularly to an improvement in the configuration of electrodes in a contact hole.

  For example, in a liquid crystal display panel, a liquid crystal cell is composed of an array substrate and a counter substrate, and the liquid crystal is driven by a switching element (a thin film transistor for pixel driving) formed on the array substrate and a drive circuit for driving the switching element. Image display is performed. In this case, one thin film transistor is required to drive the liquid crystal of one pixel, and a technique for forming a polycrystalline thin film transistor using polycrystalline silicon (polysilicon) as a channel layer on a glass substrate has been developed. Advances in process technology have made it possible to form high performance polycrystalline thin film transistors on glass substrates at low process temperatures.

  In the manufacture of a liquid crystal display panel using a polycrystalline silicon film, a thin film transistor constituting a driving circuit, such as a driver circuit and a power supply circuit, is formed on an array substrate together with the thin film transistor for driving a pixel. For example, drive circuits that have been installed as external integrated circuits (ICs) are also being built in the peripheral area (frame area) of the array substrate. In this case, the narrowing of the frame area necessary for forming the wiring around the liquid crystal display panel is a big problem. If the circuit is built in the array substrate, the number of necessary thin film transistors and the number of wirings are increased, and thus the width of the frame region must be increased.

  Therefore, for the purpose of meeting the above-mentioned demand for narrowing the frame region, for example, in the process technology, the shift from wet etching to dry etching is advanced, and the miniaturization is realized by reducing the etching conversion difference. . If the miniaturization of the wiring can be promoted, it is advantageous for narrowing the frame region.

  However, with the miniaturization of wiring, low resistance wiring is required, and the wiring film thickness tends to increase instead of reducing the wiring width, which hinders further narrowing of the frame region. This is because as the wiring film thickness increases, the etching conversion difference gradually increases in dry etching.

  Under such circumstances, a low-resistance wiring technique using a plating method that does not cause a conversion difference and using Cu, which is a low-resistance material, has attracted attention in the field of liquid crystal display panels. For example, in Patent Document 1, a metal diffusion prevention film provided on an insulating substrate without being embedded in the insulating substrate, a metal seed layer provided on the metal diffusion prevention film, and a metal seed layer are provided. A wiring having a three-layer structure composed of a metal wiring layer has been proposed, and an application example to a liquid crystal display device is disclosed.

A so-called damascene method is known as a method for forming fine wiring using copper (Cu), but it requires a polishing stop film for CMP, an etching process for forming a groove for embedding the wiring, and the like. It is. By adopting the plating method as in the invention described in Patent Document 1, these steps are unnecessary, and the number of steps can be reduced.
JP 2004-134771 A

  However, for example, when a source electrode or a drain electrode is formed in a contact hole by a plating method, there is a problem that a resistance value increases due to generation of a so-called void. This is particularly noticeable in contact holes having a large aspect ratio. Inside the contact hole, it is presumed that Cu isotropically precipitates from the Cu seed layer formed on the entire inner wall, thereby causing voids.

  The present invention has been proposed in view of such conventional circumstances, and provides a wiring structure capable of suppressing the generation of voids and suppressing an increase in resistance value. An object of the present invention is to provide an array substrate that can be narrowed and has excellent wiring reliability.

  In order to achieve the above object, an array substrate of the present invention is an array substrate in which a thin film transistor is formed in a display unit, and a Cu plating layer is connected as an electrode to the source and drain of the thin film transistor through a contact hole. A Cu seed layer is formed on the barrier metal layer, the contact hole has an aspect ratio of 1 or more, and the interlayer insulating film of the contact hole portion is composed of an insulating film including a film having Cu diffusion preventing ability In addition, a Cu seed layer is formed only in the vicinity of the bottom of the contact hole.

  When the Cu seed layer is formed only near the bottom of the contact hole, the deposition of the Cu plating layer starts from the portion where the Cu seed layer is formed (that is, the bottom of the contact hole) and gradually fills the inside of the contact hole. To do. Therefore, the deposited Cu does not collide with each other as in the case of isotropic growth, and generation of voids is avoided.

  According to the present invention, the Cu plating layer formed in the contact hole does not cause an increase in resistance due to the generation of voids. Therefore, in the array substrate of the present invention, highly reliable wiring can be formed, and the wiring can be miniaturized, so that the frame region can be narrowed.

  Hereinafter, embodiments of an array substrate to which the present invention is applied will be described in detail with reference to the drawings.

  The array substrate of this embodiment is used for a liquid crystal display panel. As shown in FIG. 1, the liquid crystal display panel includes an array substrate 1 and a counter substrate 2, and a liquid crystal layer between the array substrate 1 and the counter substrate 2 is formed in a matrix on the array substrate 1. An image is displayed by driving a thin film transistor (pixel transistor) as a switching element.

  Here, in the display area H, pixel electrodes are formed on the array substrate 1 corresponding to the respective pixels in a matrix, scanning lines are formed along the row direction of the pixel electrodes, and signals along the column direction are formed. A line is formed. Further, the pixel transistor is formed at the intersection of each scanning line and signal line.

  On the other hand, in the peripheral area of the array substrate 1 (the frame area of the liquid crystal display panel), a signal line drive circuit 3 that supplies drive signals to signal lines arranged and formed on the array substrate 1 and a drive signal to scan lines are supplied. A driving circuit such as the scanning line driving circuit 4 is formed. These drive circuits are composed of a plurality of thin film transistors (drive transistors) and wirings connected to these thin film transistors.

  FIG. 2 is a schematic cross-sectional view of a thin film transistor formed on a liquid crystal display panel. The thin film transistor is formed directly on the array substrate 1 using, for example, polysilicon as an active layer. That is, the thin film transistor is formed by forming a polycrystalline semiconductor layer (polysilicon layer) 13 on a glass substrate 11 via an undercoat layer 12 and using the polycrystalline semiconductor layer 13 as an active layer (channel layer). It is configured.

  The undercoat layer 12 is formed on the glass substrate 11 as described above. This is because the surface of the glass substrate 11 is covered with scratches, holes, and the like, and is planarized, and the impurities contained in the glass substrate 11 are polycrystalline. It is formed for the purpose of preventing diffusion into the semiconductor layer 13. The undercoat layer 12 is formed, for example, by depositing a silicon oxide film, a silicon nitride film, or the like. For example, the undercoat layer 12 prevents a diffusion of impurities and a planarization layer made of a fluidized resin that is fluidized by heat treatment. It is also possible to have a laminated structure comprising a coating layer. Alternatively, when the glass substrate 11 is excellent in planarization and contains a small amount of impurities, the undercoat layer 12 can be omitted.

  The polycrystalline semiconductor layer 13 formed on the undercoat layer 12 is annealed with amorphous silicon (a-Si) formed by, for example, a plasma CVD method, and then polycrystallineized by laser irradiation or the like. Is formed. The polycrystalline semiconductor layer 13 is separated into islands by etching or the like, and is formed as a channel of each thin film transistor. A source region 13A and a drain region 13B are formed in the polycrystalline semiconductor layer 13 by impurity implantation. Further, a gate electrode 15 is formed on the channel of the polycrystalline semiconductor layer 13 through a gate insulating film 14. Is formed.

  Further, the glass substrate 11 is formed with wirings connecting these thin film transistors and other circuits. Specifically, in the thin film transistor, the wiring 17 is connected to the source region 13A or the drain region 13B of the thin film transistor through a contact hole 18 formed in the interlayer insulating film 16. The interlayer insulating film 16 is an insulating film (for example, SiN film) having Cu diffusion preventing ability.

  Here, the wiring 17 is composed of a Cu plating layer formed by electroless plating of Cu, and the wiring width is narrowed and the resistance is reduced. Hereinafter, the layer structure of the wiring 17 in the contact hole 18 will be described.

  As described above, in order to form the wiring 17 as an electrode connected to the source region 13A and the drain region 13B of the thin film transistor, it is necessary to form a Cu plating layer so as to fill the contact hole 18. Further, when the Cu plating layer is formed by an electroless plating method, it is necessary to form a Cu seed layer. The Cu plating layer is deposited on the Cu seed layer.

  In the present embodiment, as shown in FIG. 3, a Cu seed layer 17a is formed only near the bottom of the contact hole 18, and a Cu plating layer 17b is deposited from this. In the present embodiment, the Cu seed layer 17a is formed on the barrier metal layer 17c, but the barrier metal layer 17c has a function of preventing the diffusion of Cu into the polycrystalline semiconductor layer 13. . Although the surface of the polycrystalline semiconductor layer 13 is covered with the gate insulating film 14, the diffusion of Cu cannot be prevented by the gate insulating film 14 made of Si oxide or the like. Therefore, by interposing the barrier metal layer 17c, Cu is prevented from passing through the gate insulating film 14 and diffusing into the polycrystalline semiconductor layer 23.

  The reason why the Cu seed layer 17a is formed only in the vicinity of the bottom of the contact hole 18 as described above is to prevent generation of voids in the Cu plating layer 17b. For example, as shown in FIG. 4A, when a Cu seed layer 17a is formed on the entire wall surface of the contact hole 18, it is isotropically deposited from the Cu seed layer 17a as indicated by an arrow in the figure. Then, isotropically deposited Cu collide with each other, and as shown in FIG. 4B, voids V are generated in the Cu plating layer 17b. The generation of the void V becomes a factor for increasing the resistance value of the wiring 17 formed by the Cu plating layer 17b.

  On the other hand, when the Cu seed layer 17a is formed only near the bottom of the contact hole 18, the Cu plating layer 17b grows in order from the bottom of the contact hole 18 to fill the contact hole 18, as shown in FIG. Thus, the Cu plating layer 17b is formed. At this time, the deposited Cu does not collide with each other, and no void is generated.

  The generation of the void is remarkable when the aspect ratio of the contact hole 18 is large. As shown in FIG. 6, the aspect ratio is the ratio D / R between the depth D of the contact hole 18 and the opening diameter R. When this value is 1 or more, the layer structure (the Cu seed layer 17a is formed into the contact hole). It is effective to adopt a layer structure formed only in the vicinity of the bottom of 18.

The array substrate having the wiring 17 having the layer structure as described above can be manufactured through the following steps. That is, first, after a polycrystalline semiconductor layer (eg, a film thickness of 100 nm) on a glass substrate is patterned into a desired pattern, a gate insulating film (eg, a film thickness of 50 nm) made of SiO ₂ or the like is formed by a CVD method or the like. Then, a metal film (for example, a film thickness of 300 nm) to be a gate electrode is formed thereon by a sputtering method or the like, and a gate electrode is formed in a predetermined pattern through a photolithography process, an etching process, and the like.

Thereafter, an interlayer insulating film (for example, a film thickness of 700 nm) is formed by a CVD method or the like. The interlayer insulating film may be an oxide film such as SiO ₂ , but it is preferable to form at least one layer of SiN, SiC or the like having a small diffusion coefficient with respect to Cu. After the formation of the interlayer insulating film, a contact hole is formed in the interlayer insulating film. The aspect ratio of the contact hole is, for example, 1 or more.

  Next, a barrier metal layer and a Cu seed layer are formed by sputtering or the like for wiring formation. As the barrier metal layer, for example, a Ta layer with a thickness of 30 nm is formed. As the Cu seed layer, for example, a Cu layer having a thickness of 30 nm is formed. When the barrier metal layer or Cu seed layer is formed by sputtering, Ta or Cu does not adhere to the sidewall of the contact hole formed at a steep angle, and the barrier metal layer or Cu seed layer is not formed. On the other hand, the bottom surface of the contact hole is opposed to flying Ta or Cu, and a barrier metal layer or a Cu seed layer is formed. As a result, a structure in which the barrier metal layer and the Cu seed layer are formed only near the bottom of the contact hole as shown in FIG.

  The barrier metal layer and the Cu seed layer formed on the interlayer insulating film are patterned according to the wiring pattern. Patterning is performed through a photolithography process, an etching process, and the like.

  Further, a resist layer is formed by a photolithography technique, and a Cu plating layer is formed by a plating method at a location on the Cu seed layer where the resist layer is not formed. When plating the Cu plating layer, Cu is deposited in a desired film thickness, and the Cu plating layer is formed so as to fill the contact hole. As a result, the wiring layer, the source electrode, and the drain electrode are formed by removing the resist.

  As described above, the thin film transistor and the drive circuit are formed, and then the array substrate is completed according to a normal method, and this is bonded to the counter substrate to complete the liquid crystal display panel.

  In the fabricated array substrate, voids are not generated in the Cu plating layer formed in the contact hole, and a highly reliable wiring with a low resistance value can be formed. In addition, since the wiring can be miniaturized while reducing the resistance, the frame region can be narrowed.

  By the way, in the above-described embodiment, since the gate insulating film 14 is very thin, even if there is no barrier metal layer 17c on the side wall of the contact hole 18, the barrier metal layer 17c and the Cu seed layer are only near the bottom. If 17a is present, diffusion of Cu into the polycrystalline semiconductor layer 13 can be prevented.

  On the other hand, for example, when the thickness of the gate insulating film 14 is set to be somewhat thick, the end of the gate insulating film 14 faces the contact hole 18 and Cu may be diffused therefrom. In such a case, it is preferable that the shape of the contact hole 18 is devised so that the barrier metal layer 17c covers the end portion of the gate insulating film 14.

  Specifically, as shown in FIG. 7, the inclination (taper) of the side wall of the contact hole 18 is set in two stages. That is, when the inclination angle of the inclined surface (side wall) near the bottom is θ1, and the inclination angle of the upper side wall (opening side wall) is θ2, θ1 <θ2. Thereby, the barrier metal layer 17c and the Cu seed layer 17a are formed on the inclined surface in the vicinity of the gently inclined bottom. The barrier metal layer 17c and the Cu seed layer 17a are not formed on the steep upper side wall. If the inclined surface with a gentle inclination angle is formed so as to reach the gate insulating film 14, the end portion of the gate insulating film 14 is covered with the barrier metal layer 17c and the Cu seed layer 17a, and Cu diffusion is ensured. To be prevented. The inclination of the wall surface of the contact hole 18 can be adjusted by adjusting the etching conditions.

Further, when only a part of the interlayer insulating film in the contact hole portion is formed of a film having Cu diffusion preventing ability, the barrier metal layer 17c and the Cu seed layer 17a are at least the films having Cu diffusion preventing ability. It is preferable to form up to the position to reach. For example, when the interlayer insulating film 16 is formed of a two-layer film of a SiN film having a small Cu diffusion coefficient (a film having a Cu diffusion preventing ability) and a SiO ₂ film having a large Cu diffusion coefficient, the gentle slope is formed. It is preferable to adjust the formation height of the surface and form the barrier metal layer 17c and the Cu seed layer 17a up to a height that reaches the SiN film having a small Cu diffusion coefficient. FIG. 8 shows a case where the interlayer insulating film 16 is formed of a two-layer film of an SiN film 16a having a small Cu diffusion coefficient and an SiO ₂ film 16b having a large Cu diffusion coefficient. In the case of this example, the gently inclined surface is formed to a height that reaches the SiN film 16a, and the barrier metal layer 17c and the Cu seed layer 17a are formed to a height that reaches the SiN film.

It is a schematic perspective view which shows the structural example of a liquid crystal display panel. It is a schematic sectional drawing which shows the structural example of a thin-film transistor. It is typical sectional drawing which shows an example of the layer structure of the wiring in a contact hole. (A) is a figure which shows typically the mode of the isotropic growth of Cu at the time of forming Cu seed layer in the whole contact hole, (b) is a figure which shows a mode that the void was formed in Cu plating layer. FIG. It is a figure which shows typically the mode of Cu growth at the time of forming Cu seed layer only in the bottom part of a contact hole. It is a schematic diagram for demonstrating the aspect-ratio of a contact hole. It is typical sectional drawing which shows the other example of the layer structure of the wiring in a contact hole. It is typical sectional drawing which shows the further another example of the layer structure of the wiring in a contact hole.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Array substrate, 2 Opposite substrate, 3 Signal line drive circuit, 4 Scan line drive circuit, 11 Glass substrate, 12 Undercoat layer, 13 Polycrystalline semiconductor layer, 14 Gate insulating film, 15 Gate electrode, 16 Interlayer insulating film, 17 Wiring, 17a Cu seed layer, 17b Barrier metal layer, 17c Cu plating layer, 18 Contact hole

Claims (3)

An array substrate in which a thin film transistor is formed in a display unit,
A Cu plating layer is connected as an electrode to the source and drain of the thin film transistor via a contact hole,
Cu seed layer is formed on the barrier metal layer,
The contact hole has an aspect ratio of 1 or more;
The interlayer insulating film of the contact hole portion is composed of an insulating film including a film having Cu diffusion preventing ability,
An array substrate, wherein a Cu seed layer is formed only in the vicinity of the bottom of the contact hole.   2. The array substrate according to claim 1, wherein, in the contact hole, θ1 <θ2 when a taper angle of the side wall near the bottom is θ1 and a taper angle of the side wall on the opening side is θ2.   3. The array substrate according to claim 2, wherein the barrier metal layer and the Cu seed layer are formed up to a position reaching at least the film having the Cu diffusion preventing ability.

Images