JP2006080244A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a contact hole and contact wiring that are superior in uniformity and reliability on a large board surface in a fine thin film transistor manufacturing process. <P>SOLUTION: According to the manufacturing process, an inter-layer insulating film 9 is subjected to wet etching with 10:1 BHF followed by dry etching using the same resist mask 10 for the wet etching, to form contact holes 11, 12 consecutively on the inter-layer insulating film 9 and a gate insulating film 4. The contact holes 11, 12 have a taper opening which extends to the middle of the depth of the inter-layer insulating film 9 and opens wider to the surface side; and a cylindrical opening which communicates with the taper opening, extends from the middle of the depth of the inter-layer insulating film 9 to the point where a source/drain area 3c is exposed, and has a wall surface perpendicular to the surface. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device using a MOS type semiconductor element such as an insulated gate transistor formed on an insulating substrate such as a substrate made of an insulating material or a substrate having an insulating film formed on a surface thereof, and a method for manufacturing the same.

  In recent years, attempts have been made to form high-performance semiconductor elements on an insulating substrate such as a glass substrate in order to realize a high-performance system liquid crystal display device or the like. A thin film silicon semiconductor is generally used as a semiconductor element used in these devices. In particular, a thin film transistor (TFT) is widely used as a semiconductor element constituting a peripheral circuit section such as a switching element and a driver (drive circuit) provided in an image display section in an active matrix liquid crystal display device.

  For example, in an active matrix liquid crystal display device, a plurality of gate wirings and source wirings are provided on one substrate (active matrix substrate) opposed to each other across a liquid crystal layer so as to cross each other, and are surrounded by both wirings. A pixel electrode is provided for each region. A thin film transistor (TFT) in which a drain region is connected to each pixel electrode, a source wire is connected to the source region, and a gate wire is connected to the gate electrode is provided as a switching element near the intersection of both wires. . This active matrix substrate is placed opposite to the other substrate (counter substrate) provided with a common counter electrode so as to face each pixel electrode, with a predetermined gap, and a liquid crystal material is enclosed between the two substrates. Has been. Further, when the peripheral circuit portion is provided on the active matrix substrate, a peripheral circuit such as a driver made of a CMOS circuit or the like is provided in the peripheral portion of the image display portion provided with the pixel electrode and the TFT.

  In particular, in recent years, in order to perform high-definition image display and large-capacity information signal processing, improvement of driving capability in peripheral circuit portions such as drivers has become a very important issue, which is smaller than semiconductor devices. There is an increasing demand for higher speed and higher speed characteristics.

  In TFTs, TFTs using a polycrystalline silicon thin film having higher mobility than an amorphous silicon thin film have been developed in order to obtain higher speed characteristics. This is disclosed in Patent Document 1, for example. In addition, miniaturization of semiconductor elements has also been attempted in order to reduce the size of the device.

  For example, in a liquid crystal display device, when a top gate type TFT is used, for example, an interlayer insulating film is provided so as to cover a semiconductor element such as a TFT formed on an insulating substrate. A wiring layer such as a drain wiring is provided. In the contact opening (contact hole) provided in the interlayer insulating film, the TFT source region and drain region are electrically connected to the source wiring and drain wiring.

  As the miniaturization of semiconductor elements proceeds, the contact holes (contact openings) also need to be miniaturized.

  Conventionally, this contact hole is formed by etching the interlayer insulating film and the gate insulating film so as to expose the source region and the drain region by wet etching or dry etching.

  FIG. 5 is a cross-sectional view showing the shape of the contact hole when the contact hole is formed only by wet etching. FIG. 3 shows a basic configuration example of a TFT constituting the semiconductor device. An example in which isotropic etching is performed by wet etching is disclosed in Patent Document 2, for example.

  As shown in FIG. 5, a semiconductor layer 3 having LDD regions 3b and source / drain regions (n + regions) 3c on both sides of a channel region 3a is provided on a glass substrate 1 having a base coat film 2 provided on the surface. A gate electrode 5 is provided on the gate insulating film 4 provided so as to cover the semiconductor layer 3 so as to overlap the channel region 3a, thereby forming a thin film transistor (TFT). An interlayer insulating film 9 is provided on the gate insulating film 4 and the gate electrode 5 so as to cover the TFT, and a contact hole 14 formed only by wet etching is formed in the interlayer insulating film 9 and the gate insulating film 4. A source / drain wiring 13 is provided on the interlayer insulating film 9, and the source / drain wiring 13 and the source / drain region 3c are electrically connected through a contact hole 14 to constitute an electrode connection structure. .

  FIG. 6 is a cross-sectional view showing the shape of the contact hole when the contact hole is formed only by dry etching. FIG. 6 shows a basic configuration example of a TFT constituting a semiconductor device. An example of performing anisotropic etching by dry etching is disclosed in Patent Document 3, for example.

As shown in FIG. 6, a semiconductor layer 3 having an LDD region 3b and source / drain regions (n + regions) 3c on both sides of a channel region 3a is provided on a glass substrate 1 having a base coat film 2 provided on the surface. A gate electrode 5 is provided on the gate insulating film 4 provided so as to cover the semiconductor layer 3 so as to overlap the channel region 3a, thereby forming a thin film transistor (TFT). An interlayer insulating film 9 is provided on the gate insulating film 4 and the gate electrode 5 so as to cover the TFT, and a contact hole 15 is formed in the interlayer insulating film 9 and the gate insulating film 4 only by dry etching. A source / drain wiring 13 is provided on the interlayer insulating film 9, and the source / drain wiring 13 and the source / drain region 3c are electrically connected through a contact hole 15 to constitute an electrode connection structure. .
JP 2004-158850 A JP 2004-80016 A JP 2004-241780 A

  In the configuration shown in FIG. 5, when the contact hole 14 is formed only by wet etching, the wet etching is isotropic etching, so that a tapered portion is formed from the lower end to the upper end of the contact hole 14, Due to this taper portion, the contact hole 14 is widened, making it difficult to miniaturize the semiconductor device.

  In the configuration of FIG. 6, when the contact hole 15 is formed only by dry etching, the film thickness variation of the interlayer insulating film 9 formed on the large substrate, the variation of the dry etching rate, and the insulating film and the silicon film It is difficult to form a contact hole 15 in a good state with good uniformity on a large substrate.

  In this case, since the dry etching is anisotropic etching, the aspect ratio (aspect ratio) of the contact hole 15 increases as the contact hole 15 becomes finer. For this reason, the step coverage of the wiring material is deteriorated, the conduction material is interrupted at the contact hole portion, and the probability of occurrence of conduction failure is increased, which causes a decrease in yield.

  When the contact hole 15 is formed only by dry etching, there is a problem that the etching time becomes long and the throughput is deteriorated.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described conventional problems and to provide a semiconductor device capable of forming a good contact hole with good in-plane uniformity and a method for manufacturing the same.

  The method of manufacturing a semiconductor device according to the present invention includes an insulating film forming step in which a lower electrode is formed on an insulating substrate, an interlayer insulating film is formed so as to cover the lower electrode, and a depth of the interlayer insulating film is formed in a part of the interlayer insulating film. After forming isotropic etching in the middle of the direction, subsequently forming an opening in the interlayer insulating film by performing anisotropic etching until the lower electrode is exposed at the same portion of the interlayer insulating film Forming an upper electrode on the opening and the interlayer insulating film, and electrically connecting the lower electrode and the upper electrode through the opening, and This achieves the above object.

  According to a method of manufacturing a semiconductor device of the present invention, a semiconductor element is formed by forming a semiconductor element in which a gate insulating film is provided between a semiconductor layer including a source region, a drain region, and a channel region and a gate electrode overlapping with the channel region. An insulating film forming step of forming an interlayer insulating film so as to cover the semiconductor element; and after performing isotropic etching on each part of the interlayer insulating film, the same portion of the interlayer insulating film Forming an opening in each of the interlayer insulating film, the gate insulating film, and the interlayer insulating film by performing anisotropic etching until the gate electrode, the source region, and the drain region are exposed. Then, a gate wiring, a source wiring, and a drain wiring are formed on the opening and the interlayer insulating film, respectively, and the gate electrode, the gate wiring, the source region, and the source are formed. Scan lines, and has a wiring forming step of electrically connecting each said drain region and said drain wiring, the objects can be achieved.

  Preferably, in the method of manufacturing a semiconductor device according to the present invention, in the opening forming step, the isotropic etching is performed by wet etching using a mask, and the anisotropy is performed by using the same mask used in the wet etching. Etching is performed by dry etching.

  Further preferably, in the insulating film forming step in the method for manufacturing a semiconductor device of the present invention, the interlayer insulating film is formed as a two-layer film in which a first insulating film and a second insulating film are laminated.

  Further preferably, the first insulating film in the method for manufacturing a semiconductor device of the present invention is an etching stopper for isotropic etching for etching the second insulating film.

  More preferably, a silicon nitride film is formed as the first insulating film and a silicon oxide film is formed as the second insulating film in the method for manufacturing a semiconductor device of the present invention.

  In the semiconductor device of the present invention, an upper electrode is provided on a lower electrode provided on an insulating substrate via an interlayer insulating film, and the lower electrode and the upper electrode are connected through an opening provided in the interlayer insulating film. In the electrically connected semiconductor device, the opening is provided partway in the depth direction of the interlayer insulating film, and communicates with the tapered opening that is wide open on the surface side, A cylindrical opening portion of a wall surface perpendicular to the surface provided from the middle of the interlayer insulating film in the depth direction until the lower electrode is exposed, thereby achieving the above object.

  A semiconductor device of the present invention includes a semiconductor element in which a gate insulating film is provided between a semiconductor layer including a source region, a drain region, and a channel region, and a gate electrode overlapping with the channel region. An interlayer insulating film is provided so as to cover, and a gate wiring, a source wiring, and a drain wiring provided on the interlayer insulating film are respectively provided on the interlayer insulating film, the gate insulating film, and the interlayer insulating film. In the semiconductor device electrically connected to the gate electrode, the source region, and the drain region through the openings, respectively, the openings are provided partway in the depth direction of the interlayer insulating film, A tapered opening wide open to the side, and communicated with the tapered opening, and the gate electrode, the source region or the drain from the middle of the interlayer insulating film in the depth direction. Has a cylindrical opening of the wall surface perpendicular to the surface provided to the in-region is exposed, the object is achieved.

  Preferably, in the semiconductor device of the present invention, the interlayer insulating film is a two-layer film in which a first insulating film and a second insulating film are stacked, and the opening has a lower end of the tapered opening. It is located at the interface between the first insulating film and the second insulating film.

  More preferably, a silicon nitride film is formed as the first insulating film and a silicon oxide film is formed as the second insulating film in the semiconductor device of the present invention.

  The operation of the present invention will be described below with the above configuration.

  In the present invention, in the manufacture of a semiconductor device such as a TFT formed on an insulating substrate, for example, in the case of a top gate type transistor, a semiconductor layer including a source region, a drain region and a channel region is formed on the insulating substrate. A semiconductor element such as a transistor is manufactured by forming a gate electrode on the semiconductor layer so as to overlap the channel region with a gate insulating film interposed therebetween, and then an interlayer insulating film is formed so as to cover the semiconductor element. Further, a mask having a contact opening pattern is formed by photolithography or the like, and the interlayer insulating film is etched halfway in the depth direction by wet etching using, for example, 10: 1 BHF as isotropic etching. Subsequently, etching is performed until the source region and the drain region are exposed by dry etching such as RIE, for example, as anisotropic etching, and openings for contact (contact holes) are formed in the interlayer insulating film and the gate insulating film, respectively. Form.

  For example, when a contact hole is formed only by wet etching as in the prior art, as shown in FIG. 5, the tapered portion is formed from the upper end to the lower end of the contact hole to take up an area, and it is difficult to miniaturize the contact hole. become.

  In addition, when a contact hole is formed only by dry etching as in the prior art, it is large due to variations in the film thickness of the interlayer insulating film, variations in the dry etching rate, and a low selectivity between the insulating film and the silicon film. It becomes difficult to form a contact hole in good condition with good uniformity on the substrate. In addition, as the contact hole becomes finer, the aspect ratio (aspect ratio) of the contact hole increases, the step coverage of the wiring material becomes worse, and the probability of occurrence of poor conduction in the contact hole portion increases, and the yield increases. It becomes a factor to reduce. Furthermore, since the etching time becomes longer, the throughput becomes worse.

  On the other hand, in the present invention, since wet etching and dry etching are combined, the etching depth is halved compared to the case of only wet etching, so the necessary area for taper is reduced, and only dry etching is performed. Compared to the case, a contact hole having a high uniformity and a good state can be manufactured. In addition, since the tapered portion is formed and the opening area on the surface side is wide, even when the contact hole is miniaturized and the aspect ratio of the contact hole is increased, the wiring can be connected with good step coverage. Furthermore, by combining wet etching, the dry etching time can be shortened and the throughput can be improved.

  Thus, for example, when manufacturing a fine top-gate transistor, a contact opening and contact wiring having good characteristics with good in-plane uniformity are formed, and a semiconductor having high performance and high reliability. The device can be manufactured with high yield.

  As the interlayer insulating film, for example, a silicon oxide film, a silicon oxide film to which phosphorus or boron is added (BPSG or PSG), a silicon nitride film, or the like can be used.

  Furthermore, by forming the interlayer insulating film as a two-layered film, it is possible to form contact openings with less variation.

  For example, when manufacturing a semiconductor device such as a TFT on an insulating substrate, a semiconductor layer including a source region, a drain region, and a channel region is formed on the insulating substrate, and a gate electrode is formed on the semiconductor layer via a gate insulating film. After the semiconductor element is formed so as to overlap with the channel region, a first insulating film made of, for example, a silicon nitride film and a second insulating film made of, for example, a silicon oxide film are formed so as to cover the semiconductor element Laminate. Further, a mask having a contact opening pattern is formed by photolithography or the like, and the second insulating film is etched by wet etching using, for example, 10: 1 BHF as isotropic etching. Subsequently, etching is performed using the same mask until the source / drain regions are exposed by dry etching such as RIE as anisotropic etching, thereby forming contact openings (contact holes). At this time, since the selective ratio between the silicon oxide film and the silicon nitride film is high in wet etching, the silicon nitride film is used as an etching stopper, so that the silicon oxide film has a film thickness variation or a wet etching rate variation. Etching and under-etching can be reduced, and variations in the remaining film can be reduced.

  As described above, according to the present invention, contact openings with good uniformity and contact wiring with high reliability can be formed with high yield in the substrate surface, and a fine semiconductor device can be manufactured. it can.

  In addition, since the tapered portion is formed in the contact hole by isotropic wet etching, even when the TFT has been miniaturized and the aspect ratio of the contact hole is increased, the source / drain wiring is connected with good step coverage. A highly reliable contact wiring can be formed.

  Furthermore, the dry etching time can be shortened by combining wet etching, so that the throughput can be improved.

  Therefore, for example, in a liquid crystal display device, the high performance and high integration required for an active matrix substrate are satisfied at the same time, and a multifunctional system (functional circuits such as image processing in addition to the drive circuit and the image display unit are peripheral. It is possible to manufacture a substrate for a high performance system liquid crystal display device mounted on the same substrate with a high yield. As a result, the liquid crystal module can be made compact, high performance and low cost.

Hereinafter, a case where the semiconductor device of the present invention and the first and second embodiments of the manufacturing method thereof are applied to an N-type TFT formed on a glass substrate and a manufacturing method thereof will be described in detail with reference to the drawings.
(Embodiment 1)
FIG. 1 is a cross-sectional view of a principal part showing a basic configuration example of a TFT constituting Embodiment 1 of the semiconductor device of the present invention.

  As shown in FIG. 1, a semiconductor layer 3 having an LDD region 3b and source / drain regions (n + regions) 3c on both sides of a channel region 3a is provided on a glass substrate 1 having a base coat film 2 provided on the surface. A gate electrode 5 is provided on the gate insulating film 4 provided so as to cover the semiconductor layer 3 so as to overlap the channel region 3a, thereby forming a thin film transistor (TFT) as a semiconductor device. An interlayer insulating film 9 is provided on the gate insulating film 4 and the gate electrode 5 so as to cover the TFT, and contact openings (contact holes) 11 and wet etching and dry etching are formed on the gate insulating film 4 and the interlayer insulating film 9. 12 is formed in two stages. A source / drain wiring 13 is provided on the interlayer insulating film 9, and the source / drain wiring 13 and the source / drain region 3 c are electrically connected via the contact holes 11 and 12 to constitute an electrode connection structure of the TFT. Has been.

  In this case, the contact hole 11 on the surface side has a tapered portion formed by wet etching that is isotropic etching and spreads upward, and the contact hole 12 on the substrate side is formed by dry etching that is anisotropic etching. A substantially vertical plane (here, a plane including the substantially vertical plane is simply referred to as a vertical plane) formed on the surface is formed. That is, the electrode connection structure of the present invention is provided halfway in the depth direction of the interlayer insulating film 9 and communicates with the tapered opening (contact hole 11) that opens widely on the surface side, and this tapered opening. The interlayer insulating film 9 has a cylindrical opening (contact hole 12) on the wall surface perpendicular to the surface provided from the middle in the depth direction until the source / drain region 3c is exposed.

  The method for manufacturing the semiconductor device according to the first embodiment will be described below with the above configuration.

  2A (a) to FIG. 2A (d) and FIG. 2B (e) to FIG. 2B (g) are main-part cross-sectional views showing a series of manufacturing steps of the semiconductor device of FIG.

  2A (a) to FIG. 2A (d) and FIG. 2B (e) to FIG. 2B (g) will be described in order according to a series of manufacturing steps.

  First, as shown in FIG. 2A (a), a silicon oxide film having a thickness of 300 nm is formed as a base coat film 2 on a glass substrate 1 by a plasma CVD method and baked. ) Amorphous silicon film (a-Si film). A silicon layer is crystallized using a solid phase growth method using a catalyst, a laser crystallization method, or the like to form a crystalline silicon film. The obtained crystalline silicon film is processed into an island shape (island shape), and a silicon oxide film having a thickness of 60 nm is formed by plasma CVD as a gate insulating film 4 so as to cover the island-like crystalline silicon film (semiconductor layer) 3. Form.

  Next, as shown in FIG. 2A (b), the material of the gate electrode 5 is formed on the gate insulating film 4 as a tungsten film having a thickness of 300 nm by sputtering, and this is processed into a gate electrode shape by etching. A gate electrode 5 is obtained. Using this gate electrode 5 as a mask, an n− impurity 6 is implanted to form the LDD region 3b. At this time, the n-impurity 6 is not implanted into the crystalline silicon film portion under the gate electrode 5, but is formed as the channel region 3a.

  Subsequently, as shown in FIG. 2A (c), a resist mask 7 is formed in a predetermined shape on the gate insulating film 4 so as to cover the gate electrode 5 and the LDD region 3b, and n + impurity 8 is implanted to form the LDD region. 3b and an n + region to be the source / drain region 3c are formed. The implanted impurities are activated by RTA, furnace annealing, laser irradiation, or the like.

  Thereafter, as shown in FIG. 2A (d), after removing the resist mask 7, a silicon oxide film having a thickness of 1000 nm is deposited on the gate insulating film 4 and the gate electrode 5 as the interlayer insulating film 9. Further, a resist mask 10 is formed thereon, and a contact opening pattern 10a is formed by photolithography.

  Further, the silicon oxide film 9 having a thickness of 600 nm is wet-etched as shown in FIG. 2B (e) by immersing it in, for example, 10: 1 BHF for 5 minutes through the resist mask 10 using a wet etching method. The recess 11a is formed by erosion. At this time, the contact hole 11 having a tapered portion is formed by wet etching which is isotropic etching.

  Next, as shown in FIG. 2B (f), the remaining interlayer insulating film 9 and the gate insulating film are passed through the resist mask 10 under a dry etching method, for example, RIE conditions of 100 mT and 700 W using C4F8 / CO gas. 4 is eroded by dry etching until the surface of the source / drain region 3c is exposed to form a further recess 12a. At this time, the contact hole 12 having a vertical surface that stands upright on the substrate surface is formed by dry etching which is anisotropic etching.

  Further, after removing the resist mask 10, as shown in FIG. 2B (g), source / drain wirings 13 are formed on the interlayer insulating film 9, thereby forming the source / drain regions 3c via the contact holes 11 and 12. And the source / drain wiring 13 are electrically connected to form a TFT electrode connection structure.

  As described above, according to the first embodiment, the contact hole is formed by combining wet etching and dry etching in the thick interlayer insulating film 9, so that it is a tapered portion as compared with the case of only wet etching. In addition, the contact area can be made in a good state with high uniformity compared to the case of only dry etching.

  In addition, since the tapered portion is formed by wet etching in the contact hole, wiring can be connected with good step coverage even when the contact hole is miniaturized and the aspect ratio of the contact hole is increased.

  Furthermore, by combining wet etching, the dry etching time can be shortened and the throughput can be improved.

  Accordingly, contact holes and contact wirings having good characteristics with good in-plane uniformity can be formed, and a semiconductor device having high performance and high reliability can be manufactured with high yield.

In the first embodiment, a silicon oxide film is used as the interlayer insulating film 9, but a silicon oxide film (BPSG, PSG) to which phosphorus or boron is added, a silicon nitride film, or the like may be used.
(Embodiment 2)
In the second embodiment, by forming the interlayer insulating film 9 as a two-layered film, over-etching and under-etching at the time of contact hole formation is reduced, and a semiconductor device capable of more reliably forming a low-resistance contact and its manufacture A method will be described.

  FIG. 3 is a cross-sectional view of a principal part showing a basic configuration example of a TFT constituting Embodiment 2 of the semiconductor device of the present invention.

  As shown in FIG. 3, the LDD region 3b and the source / drain regions (n + regions) are formed on both sides of the channel region 3a on the glass substrate 1 having the base coat film 2 provided on the surface, as in the case of the first embodiment. The semiconductor layer 3 having 3c is provided, and the gate electrode 5 is provided on the gate insulating film 4 provided so as to cover the semiconductor layer 3 so as to overlap the channel region 3a, so that a TFT as a semiconductor device is configured. Has been. An interlayer insulating film composed of a first insulating film 9a and a second insulating film 9b is provided in two stages on the gate insulating film 4 and the gate electrode 5 so as to cover the TFT, and the second insulating film 9b and the first insulating film Contact openings (contact holes) 12 and 11 are formed in the film 9a and the gate insulating film 4 by wet etching and dry etching. A source / drain wiring 13 is provided on the second insulating film 9b which is an interlayer insulating film, and the source / drain wiring 13 and the source / drain region 3c are electrically connected via the contact holes 12 and 11 to form an electrode. A connection structure is configured.

  In this case, the contact hole 12 on the surface side has a tapered portion formed by wet etching which is isotropic etching, and the contact hole 11 on the substrate side is perpendicular to the substrate surface by dry etching which is anisotropic etching. A wall surface (cylindrical opening) is formed. In the contact hole 12, the lower end of the tapered portion, which is the end of the wet etching, is generally located at the interface between the first insulating film 9a and the second insulating film 9b. That is, the electrode connection structure of the present invention is provided halfway in the depth direction of the interlayer insulating film 9 and communicates with the tapered opening (contact hole 11) that opens widely on the surface side, and this tapered opening. The interlayer insulating film 9 has a cylindrical opening (contact hole 12) on the wall surface perpendicular to the surface provided from the middle in the depth direction until the source / drain region 3c is exposed.

  With the above configuration, a method for manufacturing the semiconductor device of the second embodiment will be described below.

  4A (a) to FIG. 4A (d) and FIG. 4B (e) to FIG. 4B (g) are cross-sectional views of relevant parts showing a series of manufacturing steps of the semiconductor device of FIG.

  4A (a) to FIG. 4A (d) and FIG. 4B (e) to FIG. 4B (g) will be described in order according to a series of manufacturing steps.

  First, as shown in FIG. 4A (a), a 300 nm thick silicon oxide film is formed as a base coat film 2 by a plasma CVD method on a glass substrate 1 and baked, and then an intrinsic (I type) film having a thickness of 30 nm. An amorphous silicon film (a-Si film) is formed. Further, the silicon layer is crystallized using a solid phase growth method using a catalyst or a laser crystallization method to form a crystalline silicon film. The obtained crystalline silicon film is processed into an island shape (island shape), and a silicon oxide film having a thickness of 60 nm is formed as a gate insulating film 4 so as to cover the island-like crystalline silicon film (semiconductor layer) 3 by plasma CVD. To form.

  Next, as shown in FIG. 4A (b), a tungsten film to be the gate electrode 5 having a thickness of 300 nm is formed on the gate insulating film 4 by sputtering and processed into a gate electrode shape by etching. Using this gate electrode 5 as a mask, an n− impurity 6 is implanted to form the LDD region 3b. At this time, the n-impurity 6 is not implanted into the crystalline silicon film portion under the gate electrode 5, and the channel region 3a is formed.

  Subsequently, as shown in FIG. 4A (c), the resist mask 7 covers the gate electrode 5 and the LDD region 3b, and an n + impurity 8 is implanted to form the LDD region 3b and the n + region to be the source / drain region 3c. Form. The implanted impurities are activated by RTA, furnace annealing, laser irradiation, or the like. The process up to this point is the same as that in the first embodiment.

  Thereafter, as shown in FIG. 4A (d), a silicon nitride film having a thickness of 400 nm is continuously deposited as the first insulating film 9a constituting the interlayer insulating film, and a silicon oxide film having a thickness of 600 nm is continuously deposited as the second insulating film 9b. . A resist mask 10 is formed thereon, a contact opening pattern 10a is formed by a photolithography method, and the substrate is immersed in, for example, 10: 1 BHF for 5 minutes by using a wet etching method, as shown in FIG. 4B (e). As described above, the silicon oxide film 9b is eroded by wet etching to form a recess 11a (tapered opening). At this time, the contact hole 11 having a tapered portion is formed by wet etching which is isotropic etching. Further, 10: 1 BHF has a high selection ratio between the silicon oxide film 9b and the silicon nitride film 9a, and the silicon nitride film 9b has a slower etching rate by 10: 1 BHF than the silicon oxide film 9a, so that the silicon nitride film 9a is wet etched. It becomes an etching stopper at the time. The lower end of the tapered portion, which is the end of the wet etching, is located approximately at the interface between the first insulating film 9a and the second insulating film 9b.

Next, as shown in FIG. 4B (f), the silicon nitride film 9a and the gate insulating film 4 are sourced by dry etching using, for example, C ₄ F ₈ / CO gas and RIE conditions of 100 mT and 700 W. / Erosion is performed by dry etching until the drain region 3c is exposed to form a recess 12a (a cylindrical opening communicating with the tapered opening). At this time, the contact hole 12 having a plane perpendicular to the substrate surface is formed by dry etching which is anisotropic etching.

  After removing the resist mask 10, a source / drain wiring 13 is formed on the interlayer insulating film 9b as shown in FIG. 4B (g), whereby the source / drain region 3c and the source are connected via the contact holes 11 and 12. / Drain wiring 13 is connected.

  Therefore, according to the second embodiment, since the selection ratio between the silicon oxide film and the silicon nitride film is high at the time of wet etching, by using the silicon nitride film as an etching stopper, the film thickness variation of the silicon oxide film and the wet etching are reduced. It is possible to form a contact hole with higher uniformity by reducing over-etching and under-etching due to rate variation and reducing variation in remaining film.

  As described above, according to the first and second embodiments, the interlayer insulating film 9 (or 9a, 9a, 9a, 9b) is obtained by performing dry etching using the same resist mask 10 following the wet etching by 10: 1 BHF on the interlayer insulating film 9. 9b) and contact holes 11 and 12 are continuously formed in the gate insulating film 4. That is, the electrode connection structure of the present invention is provided halfway in the depth direction of the interlayer insulating film 9 and communicates with the tapered opening (contact hole 11) that opens widely on the surface side, and this tapered opening. The interlayer insulating film 9 has a cylindrical opening (contact hole 12) on the wall surface perpendicular to the surface provided from the middle in the depth direction until the source / drain region 3c is exposed. As a result, in a manufacturing process of a fine thin film transistor, contact calls and contact wirings having high uniformity and high reliability can be formed within a large substrate surface.

  In the first and second embodiments, the example in which the semiconductor device manufacturing method of the present invention is applied to a method of manufacturing an N-type TFT on the glass substrate 1 has been described. The method is not limited to this, and can be applied to any electrode connection structure in which a lower electrode and an upper electrode provided on an insulating substrate are electrically connected through a contact opening provided in an insulating film. It is possible. In particular, the present invention is suitable for a thin film transistor provided in an image display unit and a peripheral circuit unit in a system liquid crystal display device and the like that are required to be downsized and increased in speed, and can realize a high-performance system liquid crystal display device. it can.

  In the first and second embodiments, the top gate transistor is described as the structure of the thin film transistor as the semiconductor device. However, the present invention is not limited to this, and the present invention can be applied to the bottom gate transistor. Play. For example, in the case of a top gate transistor, a semiconductor layer including a source region, a drain region, and a channel region is formed on an insulating substrate, and a gate electrode is superimposed on the channel region via a gate insulating film on the semiconductor layer. To form. In the case of a bottom gate transistor, a gate electrode is formed on an insulating substrate, and a semiconductor layer including a source region, a drain region, and a channel region is formed thereon via a gate insulating film. Superimposed. In short, in any case, a semiconductor element in which a gate insulating film is provided between a semiconductor layer including a source region, a drain region, and a channel region and a gate electrode overlapping with the channel region is formed.

  Further, although not particularly described in the first and second embodiments, the contact hole structure of the present invention is also used for connection between the gate electrode and the gate wiring. That is, a gate wiring, a source wiring, and a drain wiring are formed on the opening (contact hole) and the interlayer insulating film, respectively, and the gate electrode and the gate wiring, the source region and the source wiring, and the drain region and the drain wiring are electrically connected. A wiring forming process for connecting them individually.

  As mentioned above, although this invention was illustrated using preferable Embodiment 1, 2 of this invention, this invention should not be limited and limited to this Embodiment 1,2. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of the specific preferred embodiments 1 and 2 of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention relates to a semiconductor device using a MOS semiconductor element such as an insulated gate transistor formed on an insulating substrate such as a substrate made of an insulating material or a substrate having an insulating film formed on the surface thereof, a method for manufacturing the same, and a method for manufacturing the same. In the field of the electrode connection structure used for and the formation method thereof, wet etching and dry etching are combined to form a contact hole, so that the area required for taper is smaller than in the case of only wet etching. Thus, a contact hole having a high uniformity and a favorable state can be manufactured as compared with the case of only dry etching. Further, since the taper is formed by wet etching, wiring can be connected with good step coverage even when the contact hole is miniaturized and the aspect ratio of the contact hole is increased. Furthermore, by combining wet etching, the dry etching time can be shortened and the throughput can be improved. Furthermore, by forming the interlayer insulating film as a two-layered film, it is possible to form contact openings with less variation. INDUSTRIAL APPLICABILITY The present invention is suitable for a thin film transistor provided in an image display unit and a drive unit in a system liquid crystal display device and the like that are required to be reduced in size and speed, and can realize a high-performance system liquid crystal display device.

It is principal part sectional drawing which shows the basic structural example of TFT which comprises Embodiment 1 of the semiconductor device of this invention. (A)-(d) is principal part sectional drawing for demonstrating sequentially a series of each manufacturing process (the 1) in the semiconductor device of FIG. (E)-(g) is principal part sectional drawing for demonstrating sequentially a series of each manufacturing process (the 2) in the semiconductor device of FIG. It is principal part sectional drawing which shows the basic structural example of TFT which comprises Embodiment 2 of the semiconductor device of this invention. (A)-(d) is principal part sectional drawing for demonstrating sequentially a series of each manufacturing process (the 1) in the semiconductor device of FIG. (E)-(g) is principal part sectional drawing for demonstrating sequentially a series of each manufacturing process (the 2) in the semiconductor device of FIG. It is sectional drawing which shows the shape of a contact hole at the time of forming a contact hole only by wet etching. It is sectional drawing which shows the shape of a contact hole at the time of forming a contact hole only by dry etching.

Explanation of symbols

1 Glass substrate (insulating substrate)
2 Base coat film 3 Semiconductor layer (island-like crystalline silicon film)
3a channel region 3b LDD region 3c source / drain region (n + region)
4 Gate insulating film 5 Gate electrode 6 n-impurity implantation 7 Resist mask 8 n + impurity implantation 9 Interlayer insulating film (silicon oxide film)
9a First insulating film (silicon nitride film)
9b Second insulating film (silicon oxide film)
DESCRIPTION OF SYMBOLS 10 Resist mask 10a Contact opening pattern 11 Contact hole 11a Recessed part formed by wet etching 12 Contact hole 12a Recessed part formed by dry etching
13 Source / drain wiring

Claims (10)

An insulating film forming step of forming a lower electrode on the insulating substrate and forming an interlayer insulating film so as to cover the lower electrode;
An isotropic etching is performed on a part of the interlayer insulating film halfway in the depth direction, and then an anisotropic etching is performed until the lower electrode is exposed at the same portion of the interlayer insulating film. An opening forming step of forming an opening in the insulating film;
An upper electrode forming step of forming an upper electrode on the opening and the interlayer insulating film and electrically connecting the lower electrode and the upper electrode through the opening. A semiconductor element formation step of forming a semiconductor element in which a gate insulating film is provided between a semiconductor layer including a source region, a drain region, and a channel region and a gate electrode overlapping with the channel region;
An insulating film forming step of forming an interlayer insulating film so as to cover the semiconductor element;
Isotropic etching is performed on each part of the interlayer insulating film, and then anisotropic etching is performed until the gate electrode, the source region, and the drain region are respectively exposed at the same portion of the interlayer insulating film. An opening forming step of forming each opening in the interlayer insulating film, the gate insulating film, and the interlayer insulating film;
A gate wiring, a source wiring, and a drain wiring are formed on the opening and the interlayer insulating film, and the gate electrode and the gate wiring, the source region and the source wiring, and the drain region and the drain wiring are formed. A method of manufacturing a semiconductor device, comprising: a wiring formation step of electrically connecting each.   The said opening part formation process performs the said isotropic etching by wet etching using a mask, and performs the said anisotropic etching by dry etching using the same mask used by this wet etching. Semiconductor device manufacturing method.   The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film forming step forms the interlayer insulating film as a two-layer film in which a first insulating film and a second insulating film are stacked.   The method of manufacturing a semiconductor device according to claim 4, wherein the first insulating film is used as an etching stopper for isotropic etching for etching the second insulating film.   6. The method of manufacturing a semiconductor device according to claim 4, wherein a silicon nitride film is formed as the first insulating film, and a silicon oxide film is formed as the second insulating film. An upper electrode is provided on the lower electrode provided on the insulating substrate via an interlayer insulating film, and the lower electrode and the upper electrode are electrically connected through an opening provided in the interlayer insulating film. In semiconductor devices,
The opening is provided halfway in the depth direction of the interlayer insulating film, and is connected to the tapered opening that is wide open on the surface side, and the taper-shaped opening, and from the middle of the interlayer insulating film in the depth direction. A semiconductor device having a cylindrical opening on a wall surface perpendicular to the surface provided until the lower electrode is exposed. A semiconductor element in which a gate insulating film is provided between a semiconductor layer including a source region, a drain region, and a channel region and a gate electrode overlapping with the channel region is configured, and an interlayer insulating film is formed so as to cover the semiconductor element A gate wiring, a source wiring, and a drain wiring provided on the interlayer insulating film through the openings provided in the interlayer insulating film, the gate insulating film, and the interlayer insulating film, respectively. In the semiconductor device electrically connected to the gate electrode, the source region, and the drain region,
The opening is provided partway in the depth direction of the interlayer insulating film, and is connected to the tapered opening that opens widely on the surface side, and from the middle in the depth direction of the interlayer insulating film. A semiconductor device having a cylindrical opening on a wall surface perpendicular to the surface provided until the gate electrode, the source region, or the drain region are exposed. The interlayer insulating film is composed of a two-layer film in which a first insulating film and a second insulating film are laminated,
9. The semiconductor device according to claim 7, wherein a lower end of the tapered opening is located at an interface between the first insulating film and the second insulating film.   The semiconductor device according to claim 9, wherein a silicon nitride film is formed as the first insulating film, and a silicon oxide film is formed as the second insulating film.

Images