JP2008527743A5 - - Google Patents
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- Publication number
- JP2008527743A5 JP2008527743A5 JP2007551329A JP2007551329A JP2008527743A5 JP 2008527743 A5 JP2008527743 A5 JP 2008527743A5 JP 2007551329 A JP2007551329 A JP 2007551329A JP 2007551329 A JP2007551329 A JP 2007551329A JP 2008527743 A5 JP2008527743 A5 JP 2008527743A5
- Authority
- JP
- Japan
- Prior art keywords
- layer
- high temperature
- silicon material
- silicide
- temperature process
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/905,629 US7105440B2 (en) | 2005-01-13 | 2005-01-13 | Self-forming metal silicide gate for CMOS devices |
| PCT/US2006/000838 WO2006076373A1 (en) | 2005-01-13 | 2006-01-10 | Self-forming metal silicide gate for cmos devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2008527743A JP2008527743A (ja) | 2008-07-24 |
| JP2008527743A5 true JP2008527743A5 (https=) | 2008-12-04 |
Family
ID=36653783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007551329A Pending JP2008527743A (ja) | 2005-01-13 | 2006-01-10 | Ｃｍｏｓデバイスの自己形成金属シリサイド化ゲート |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7105440B2 (https=) |
| EP (1) | EP1856725A4 (https=) |
| JP (1) | JP2008527743A (https=) |
| KR (1) | KR20070095933A (https=) |
| CN (1) | CN100505187C (https=) |
| TW (1) | TW200636920A (https=) |
| WO (1) | WO2006076373A1 (https=) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4784734B2 (ja) * | 2005-09-12 | 2011-10-05 | 日本電気株式会社 | 半導体装置及びその製造方法 |
| US7687396B2 (en) * | 2006-12-29 | 2010-03-30 | Texas Instruments Incorporated | Method of forming silicided gates using buried metal layers |
| KR100852212B1 (ko) | 2007-06-12 | 2008-08-13 | 삼성전자주식회사 | 반도체 소자 및 이를 형성하는 방법 |
| US7615831B2 (en) * | 2007-10-26 | 2009-11-10 | International Business Machines Corporation | Structure and method for fabricating self-aligned metal contacts |
| US7964923B2 (en) | 2008-01-07 | 2011-06-21 | International Business Machines Corporation | Structure and method of creating entirely self-aligned metallic contacts |
| US9165826B2 (en) | 2011-08-01 | 2015-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a semiconductor device comprising titanium silicon oxynitride |
| US8765603B2 (en) * | 2011-08-01 | 2014-07-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a buffer layer |
| US12389616B2 (en) * | 2022-02-11 | 2025-08-12 | Globalfoundries U.S. Inc. | Transistors with multiple silicide layers |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950003233B1 (ko) * | 1992-05-30 | 1995-04-06 | 삼성전자 주식회사 | 이중층 실리사이드 구조를 갖는 반도체 장치 및 그 제조방법 |
| US5444302A (en) * | 1992-12-25 | 1995-08-22 | Hitachi, Ltd. | Semiconductor device including multi-layer conductive thin film of polycrystalline material |
| JPH06244136A (ja) * | 1992-12-25 | 1994-09-02 | Hitachi Ltd | 半導体装置及びその製造方法 |
| JPH1117182A (ja) * | 1997-06-26 | 1999-01-22 | Sony Corp | 半導体装置およびその製造方法 |
| JPH11135789A (ja) * | 1997-10-31 | 1999-05-21 | Nippon Steel Corp | 半導体装置およびその製造方法 |
| CN1222754A (zh) * | 1997-12-19 | 1999-07-14 | 西门子公司 | 在硅化物膜上进行化学汽相淀积的方法和设备 |
| JP2000252462A (ja) * | 1999-03-01 | 2000-09-14 | Toshiba Corp | Ｍｉｓ型半導体装置及びその製造方法 |
| US6562718B1 (en) | 2000-12-06 | 2003-05-13 | Advanced Micro Devices, Inc. | Process for forming fully silicided gates |
| US6555453B1 (en) | 2001-01-31 | 2003-04-29 | Advanced Micro Devices, Inc. | Fully nickel silicided metal gate with shallow junction formed |
| US6878623B2 (en) * | 2001-02-01 | 2005-04-12 | Chartered Semiconductor Manufacturing Ltd. | Technique to achieve thick silicide film for ultra-shallow junctions |
| US7029966B2 (en) * | 2003-09-18 | 2006-04-18 | International Business Machines Corporation | Process options of forming silicided metal gates for advanced CMOS devices |
-
2005
- 2005-01-13 US US10/905,629 patent/US7105440B2/en not_active Expired - Fee Related
-
2006
- 2006-01-04 TW TW095100297A patent/TW200636920A/zh unknown
- 2006-01-10 KR KR1020077015594A patent/KR20070095933A/ko not_active Ceased
- 2006-01-10 EP EP06717971A patent/EP1856725A4/en active Pending
- 2006-01-10 JP JP2007551329A patent/JP2008527743A/ja active Pending
- 2006-01-10 CN CNB2006800014309A patent/CN100505187C/zh not_active Expired - Fee Related
- 2006-01-10 WO PCT/US2006/000838 patent/WO2006076373A1/en not_active Ceased
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