JP2008268853A - Electrophoretic display device, driving method thereof, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrophoretic display device capable of suppressing a leakage current between pixels thereby allowing the reliability thereof as a product to be improved and also allows the manufacturing cost thereof to be suppressed and to provide a driving method thereof and an electronic apparatus. <P>SOLUTION: The electrophoretic display device is characterized in that a display part includes pixel electrodes 21, the pixel electrode 21 being formed in each of the pixel 2, opposite electrodes 22 opposed to the plurality of pixel electrodes 21 through electrophoretic elements 23 and first and second control lines 11, 12 connected to each of the pixels 2 and that each pixel 2 is provided with a driving TFT 23, an SRAM 25, and a switching circuit 35 which is switched by an output signal from the SRAM 25 to switch a connection state between the pixel electrode 21 and the first control line 11 or the second control line 12. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electrophoretic display device, an electrophoretic display device driving method, and an electronic apparatus.

In order to display an image on the electrophoretic display device, an image signal is temporarily stored in a memory circuit via a switching element. The image signal stored in the memory circuit is directly input to the pixel electrode, and when a potential is applied to the pixel electrode, a potential difference is generated between the counter electrode and the pixel electrode. Thus, the electrophoretic element can be driven to display an image (see, for example, Patent Document 1). Japanese Patent Application Laid-Open No. 2004-228561 has a configuration including an SRAM (Static Random Access Memory) as a memory circuit (a configuration including a latch that holds information as a potential in a pixel) and a DRAM (Dynamic Random Access Memory). (A configuration in which a potential is held by a capacitor) is described.
JP 2003-84314 A

  In order to display an image on the electrophoretic display device, a sufficient potential difference must be given between the electrodes sandwiching the electrophoretic element, so that the power supply voltage of the memory circuit needs to be 10 V or more. At this time, if different colors are displayed in adjacent pixels, different potentials are input to the pixel electrodes of the adjacent pixels. Therefore, since a large potential difference is generated between adjacent pixel electrodes, a leakage current flows between the adjacent first electrodes via an adhesive or the like that fixes the electrophoretic element to the substrate. Even if the leakage current per pixel is small, the leakage current of the entire display unit of the electrophoretic display device is large, leading to an increase in power consumption. The generation of this leakage current has been described in detail with reference to FIG. 10 in an embodiment described later.

  In addition, the occurrence of a leak current indicates the possibility of an electrochemical reaction occurring in the pixel electrode. That is, there is a possibility that the reliability of the pixel electrode is impaired due to the occurrence of ionic migration or corrosion. Thus, for example, when a chemically stable and corrosion-resistant material such as gold or platinum is used for the pixel electrode, the reliability can be improved, but the manufacturing cost increases.

  An object of the present invention is to provide an electrophoretic display device capable of suppressing leakage current between pixels and improving power saving and reliability, and is suitable for such an electrophoretic display device. Another purpose is to provide a method.

  Further, in the active matrix type electrophoretic display device, when the display is switched from the already displayed image (original image) to the next image to be displayed (new image), a preliminary display operation for preventing an afterimage from appearing. Execute. For example, an operation for displaying the entire display portion in white (all white display), an operation for displaying the entire display portion in black (all black display), an operation for repeatedly executing all white display and all black display, An operation for displaying a reverse image of the original image or the new image for a short period is performed. Then, after performing such a preliminary display operation, a new image is displayed.

The image switching sequence including the preliminary display operation is indispensable for realizing high-quality display (high contrast, afterimage free) in an environment where the electrophoretic display device is used. However, in such an image switching sequence, it is necessary to transfer all white, all black, or inverted image data to the pixel every time the image is switched, which increases the power consumption of the electrophoretic display device.
Therefore, the present invention has another object to provide an electrophoretic display device having a configuration capable of improving the efficiency of an image switching sequence and reducing power consumption, and a driving method having an efficient image switching sequence. One.

The electrophoretic display device of the present invention is an electrophoretic display device comprising an electrophoretic element containing electrophoretic particles sandwiched between a pair of substrates and having a display unit composed of a plurality of pixels. A pixel electrode formed for each pixel; a counter electrode facing the plurality of pixel electrodes through the electrophoretic element; and first and second control lines connected to each of the pixels. A pixel switching element; a memory circuit connected to the pixel switching element; and the pixel electrode and the first or second control line that are switched by an output signal of the memory circuit. And a switch circuit for switching the connection state between the first and second terminals.
According to this configuration, the image data input to the memory circuit is used for switching of the switch circuit that electrically connects the pixel electrode and the first and second control lines, and the potential input to the pixel electrode is the first. Alternatively, this is done via the second control line.
In such a configuration, the first and second control lines connected to the pixel electrode serve as a leakage path, but these control lines can be connected to the circuit and input signals only during the period of potential input to the pixel electrode. In other periods, an electrically disconnected high impedance state can be obtained. If at least one of the first and second control lines is in a high impedance state, the leakage path is cut off in the control line, so that occurrence of a leakage current between adjacent pixels can be suppressed.
As described above, according to the present invention, it is possible to suppress the leakage current between adjacent pixels, and to effectively prevent a decrease in reliability due to the leakage current.
In addition, as described above, in the present invention, the potential input to the pixel electrode from the first and second control lines can be controlled independently of the image data input to the memory circuit, and the display state of the pixel Can be controlled. That is, in the present invention, it is possible to perform a preliminary display operation such as an all-white display or an all-black display without transferring image data to the pixels, and power consumption related to the preliminary display operation can be saved.

A pixel driver connected to the pixel via a scanning line and a data line and supplying image data to the memory circuit via the pixel switching element; and the first and second control lines and the counter electrode. A voltage applied to the pixel electrode is supplied to the switch circuit via the first and second control lines, and is supplied to the first and second control lines with respect to the counter electrode. It is preferable to include a potential control unit that supplies a rectangular wave of one cycle or more that repeats the first and second potentials corresponding to the first potential.
That is, a pixel driving unit that supplies image data to be displayed to the pixel and a potential control unit that supplies a voltage applied to the pixel electrode and the counter electrode to perform display based on the image data are provided. It is preferable.
In the present invention, a rectangular wave that repeats the first potential and the second potential is supplied to the counter electrode, and a driving method referred to as “common swing driving” in this specification is employed. According to this common swing driving method, the potential applied to the pixel electrode and the counter electrode can be controlled by binary values of a high level (H) and a low level (L). The configuration can be simplified. Further, when a TFT (Thin Film Transistor) is used as the pixel switching element, there is an advantage that the reliability of the TFT can be secured by low voltage driving.

The memory circuit has first and second output terminals for outputting different signals, and the switch circuit is connected between the first control line and the pixel electrode, and the first A first transfer gate that is switched by the output of the second output terminal, and a second transfer that is connected between the second control line and the pixel electrode and that is switched by the output of the second output terminal. A structure including a gate can be employed.
According to this configuration, an electrophoretic display device that can selectively select the first or second control line to be connected to the pixel electrode by the transfer gate and control the potential of the pixel electrode can be obtained. In this case, the memory circuit has a plurality of output terminals, and can be, for example, a latch circuit in which inverters are combined.

A first transistor connected between the first control line and the pixel electrode; a second transistor connected between the second control line and the pixel electrode; And one of the first and second transistors may be a P-type transistor and the other transistor may be an N-type transistor.
Even in such a configuration, the first or second control line connected to the pixel electrode can be alternatively selected based on a signal output from the memory circuit.
Further, according to this configuration, since the switch circuit can be configured by two transistors, the area occupied by the switch circuit can be reduced, and the configuration can easily cope with the high definition of the pixel. Further, the configuration is advantageous in reducing parasitic capacitance and power consumption in the switch circuit.

The memory circuit has first and second output terminals for outputting different signals, and the switch circuit is connected between the first control line and the pixel electrode and the first A first transistor composed of an N-type transistor that is switched by the output of the second output terminal, and is connected between the second control line and the pixel electrode and is switched by the output of the second output terminal. And a second transistor including an N-type transistor.
As described above, even when the switch circuit includes two N-type transistors, the first or second control line connected to the pixel electrode is selected based on the signal output from the memory circuit. Can be selected automatically, and the same effects can be obtained. In such a configuration, by using the outputs from the first and second output terminals of the memory circuit, the first and second control lines can be selected by the same channel type transistor.

The memory circuit has first and second output terminals for outputting different signals, and the switch circuit is connected between the first control line and the pixel electrode, and the first A first transistor composed of a P-type transistor that is switched by the output of the second output terminal, and is connected between the second control line and the pixel electrode and is switched by the output of the second output terminal. And a second transistor including a P-type transistor.
As described above, even when the switch circuit is configured by two P-type transistors, the first or second control line connected to the pixel electrode is selected based on the signal output from the memory circuit. Can be selected automatically, and the same effects can be obtained. Also in such a configuration, the first and second control lines can be selected by the same channel type transistor by using the outputs from the first and second output terminals of the memory circuit.

  It is preferable that the first and second control lines are wirings common to the plurality of pixels. That is, it is preferable that the first and second control lines are global wirings. According to this configuration, the circuit pattern for controlling the control line and the wiring of the control line can be simplified, and the design and manufacturing costs can be reduced.

  The memory circuit is preferably a latch circuit. The latch circuit can be realized by a configuration similar to an SRAM cell in which two inverters are connected in a loop. According to this configuration, the image data input via the pixel switching element can be held as a potential, and the state of the switch circuit can be held without performing a refresh operation for every predetermined period. Can be maintained. In addition, since a plurality of output terminals for outputting different signals can be provided, appropriate control according to the configuration of the switch circuit is possible.

The potential control unit electrically connects the first control line from the switch circuit when shifting a part of the pixels from the first gradation to the second gradation as the first operation. It is preferable that only the second control line that is disconnected and supplied with the second potential is connected to the switch circuit. Thereby, even if the different potentials are input to the first electrodes of the adjacent pixels, the first control line is electrically disconnected. An electrophoretic display device that suppresses leakage current and reduces power consumption can be obtained.
As the second operation, the potential control unit electrically connects the second control line from the switch circuit when shifting some of the pixels from the second gradation to the first gradation. It is preferable that only the first control line that is disconnected and supplied with the first potential is connected to the switch circuit. Thereby, even if the different potentials are input to the first electrodes of the adjacent pixels, the second control line is electrically disconnected. An electrophoretic display device that suppresses leakage current and reduces power consumption can be obtained.
When the potential control unit holds the display state of the pixel, all the wirings connected to the memory circuit, the switch circuit, and the second electrode are connected to the memory circuit, the switch circuit, and the first circuit. It is preferable to electrically disconnect from the two electrodes. Thus, an electrophoretic display device that reduces power consumption when holding an image can be obtained.
The potential control unit electrically disconnects the first control line from the switch circuit, and connects only the second control line supplied with the second potential to the switch circuit. The first operation for shifting the pixels of the portion from the first gradation to the second gradation, and electrically disconnecting the second control line from the switch circuit, and the first potential The second operation for shifting a part of the pixels from the second gradation to the first gradation by connecting only the first control line supplied with the switch circuit to the switch circuit. It is preferable to update the image by repeating alternately. Thereby, it is possible to obtain an electrophoretic display device that reduces power consumption by reducing the leakage current in image updating.
It is preferable that different potentials are input to the second electrode in synchronization with the switching between the first operation and the second operation. This eliminates the need to control the potential input from the potential control unit to the second electrode in accordance with the two operations, simplifies the circuit pattern, and reduces the manufacturing cost. It can be a display device.
A period in which the first control line and the second control line are electrically disconnected from the switch circuit is provided between the period of the first operation and the period of the second operation. Is preferred. Thereby, since the first and second control lines are electrically disconnected, the leakage current can be further reduced, and an electrophoretic display device that updates an image with less power consumption can be obtained.

Next, a driving method of an electrophoretic display device according to the present invention includes an electrophoretic element including electrophoretic particles sandwiched between a pair of substrates, and includes a display unit including a plurality of pixels. A pixel electrode formed for each pixel; a counter electrode facing the plurality of pixel electrodes through the electrophoretic element; and first and second control lines connected to each of the pixels. A pixel switching element; a memory circuit connected to the pixel switching element; and the pixel electrode and the first or second control line that are switched by an output signal of the memory circuit. And a switch circuit for switching a connection state between the first switching circuit and the first switching step for inputting an image signal to the memory circuit via the pixel switching element. And supplying the first and second potentials to the first and second control lines, respectively, and operating the switch circuit on the basis of the output from the memory circuit, from the first or second control line. And a second step of inputting a rectangular wave that repeats the first and second potentials to the counter electrode for one period or more.
Such a driving method includes a step of inputting image data to the memory circuit and a step of performing a display operation based on the image data held in the memory circuit. That is, independent of the image data input to the memory circuit, the potential input to the pixel electrode from the first and second control lines is controlled to control the display state of the pixel.
Therefore, since the preliminary display operation such as the all white display or the all black display can be performed without updating the image data held in the memory circuit, the power consumption related to the preliminary display operation can be saved.

In the first step, a first image signal is input to the memory circuit of the pixel that displays a first gradation, and a second image signal is input to the memory circuit of the pixel that displays a second gradation. In the second step, an image signal is input, and the switch circuit is operated based on an output of the memory circuit holding the first image signal in the pixel that displays the first gradation. The switch circuit is operated based on the output of the memory circuit holding the second image signal in the pixel that displays the second gradation by connecting the first control line and the pixel electrode. It is preferable that the second control line and the pixel electrode are connected to each other.
That is, it is preferable to use a driving method that switches between the first and second control lines connected to the pixel electrode in accordance with the gradation value of the image data. By setting the potential of the first and second control lines to a potential corresponding to the gradation value, display based on image data can be performed.

The switch circuit includes a first transfer gate connected between the first control line and the pixel electrode, and a second transfer connected between the second control line and the pixel electrode. And in the second step, the low level signal output from the first output terminal of the memory circuit and the high level signal output from the second output terminal in the second step. By switching the transfer gate to the on state, the first control line and the pixel electrode are connected, and a high level signal supplied from the first output terminal and a low level signal output from the second output terminal are connected. A driving method in which the second control line is connected to the pixel electrode by switching the second transfer gate to an on state by a level signal may be employed.
In the case where the switch circuit includes the first and second transfer gates, it is preferable to input the two outputs of the memory circuit to the respective transfer gates and to switch the transfer gates with these two outputs. . Thereby, the voltage of the 1st and 2nd control line can be applied to a pixel electrode, without dropping.

The switch circuit is connected between a first transistor composed of a P-type transistor connected between the first control line and the pixel electrode, and between the second control line and the pixel electrode. A second transistor composed of an N-type transistor, and in the second step, the first transistor is switched to an ON state by a low level signal output from the memory circuit. A control line and the pixel electrode are connected to each other, and the second transistor is turned on by a high-level signal output from the memory circuit, whereby the second control line and the pixel electrode are connected to each other. The driving method can also be used.
Thus, when the switch circuit includes P-type and N-type transistors, the operation of the switch circuit can be controlled with one output of the memory circuit.

The switch circuit includes first and second transistors each of which is an N-type transistor, the first control line is connected to the pixel electrode through the first transistor, and the second control A line is connected to the pixel electrode via the second transistor, and in the second step, the first transistor is turned on by a high level signal output from the first output terminal of the memory circuit. By switching to the state, the first control line and the pixel electrode are connected to each other, and the second transistor is switched to the on state by a high level signal output from the second output terminal of the memory circuit. A driving method in which the second control line and the pixel electrode are connected may be employed.
When the switch circuit is composed of two N-type transistors as described above, the switch circuit can be controlled using the same channel type transistors by using two outputs of the memory circuit.

The switch circuit includes first and second transistors each made of a P-type transistor, the first control line is connected to the pixel electrode through the first transistor, and the second control A line is connected to the pixel electrode via the second transistor, and in the second step, the first transistor is turned on by a low level signal output from the first output terminal of the memory circuit. By switching to the state, the first control line and the pixel electrode are connected to each other, and the second transistor is switched to the on state by a low level signal output from the second output terminal of the memory circuit. A driving method in which the second control line and the pixel electrode are connected may be employed.
As described above, even when the switch circuit is composed of two P-type transistors, the switch circuit can be controlled using the same channel type transistors by using two outputs of the memory circuit.

  In the second step, it is also possible to employ a driving method in which all the pixels have the same gradation by supplying signals having the same potential to the first and second control lines. Thus, all black display or all white display can be performed regardless of the image data held in the memory circuit, so that an image erasing operation can be executed while suppressing power consumption.

In the second step, the first control line is placed in a high impedance state where the first control line is electrically disconnected, and the second potential is supplied to the second control line, whereby at least the display unit A first display step of shifting some of the pixels from the first gradation to the second gradation; and supplying the first potential to the first control line and performing the second control A second display step of shifting at least a part of the pixels of the display unit from the second gradation to the first gradation by setting the line in a high impedance state where the line is electrically disconnected; It is preferable to have.
The first control line for shifting the pixel from the first gradation to the second gradation and the second control line for shifting the pixel from the second gradation to the first gradation are substantially However, it does not contribute to the display operation, but rather serves as a leakage current path between the pixel electrodes.
Therefore, in this way, if a driving method for performing display while appropriately setting control lines that do not contribute to the display operation to a high impedance state, the leakage path can be cut off and the leakage current can be eliminated, resulting in a driving method with low power consumption. . In addition, since no leakage current occurs, the driving method does not cause a decrease in reliability in the pixel electrode.

In the second step, it is preferable to update the display image by repeating the first and second display steps.
In the first display step, for example, only pixels that are displayed in black are driven, and in the second display step, for example, only pixels that are displayed in white are driven, so that each display step is continued until the display operation of the pixels is completed. It takes time until an image to be displayed is visually recognized.
Therefore, by alternately repeating the first and second display steps, the same image as the display image can be displayed on the display unit although the contrast is lowered, so that the image can be updated without causing stress to the user. It can be performed.

Preferably, the method includes a step of placing the first and second control lines in a high impedance state electrically disconnected between the first display step and the second display step.
With this driving method, the first and second control lines are not connected to the pixel at the same time, so that the leak path can be reliably blocked.

Preferably, after the second step, there is a step of bringing the memory circuit, the switch circuit, and the counter electrode into an electrically disconnected high impedance state.
With such a driving method, an electrophoretic display device which can prevent current leakage in the pixel and can maintain a good display can be obtained. Further, since the electrophoretic element is electrically isolated, power consumption when holding an image can be reduced.

  The electrophoretic display device of the present invention includes a control unit that executes the driving method of the present invention described above. According to this configuration, it is possible to provide an electrophoretic display device that can reduce power consumption and perform a display operation without causing a decrease in reliability.

  An electronic apparatus according to the present invention includes the electrophoretic display device described above. According to this configuration, it is possible to provide an electronic device including a display device with low power consumption and excellent reliability.

(First embodiment)
Hereinafter, the electrophoretic display device 1 according to the present invention will be described with reference to the drawings.
FIG. 1 is a configuration diagram of an electrophoretic display device 1 according to an embodiment of the present invention. The electrophoretic display device 1 includes a display unit 3, a scanning line drive circuit (pixel drive unit) 6, a data line drive circuit (pixel drive unit) 7, a common power supply modulation circuit (potential control unit) 8, and a controller 10. ing.

  In the display unit 3, the pixels 2 are formed in a matrix of m pieces along the Y axis direction and n pieces along the X axis direction. The scanning line driving circuit 6 is connected to the pixel 2 through a plurality of scanning lines 4 (Y1, Y2,..., Ym) extending along the X-axis direction in the display unit 3. The data line driving circuit 7 is connected to the pixel 2 through the display unit 3 via a plurality of data lines 5 (X1, X2,..., Xn) extending along the Y-axis direction. The common power supply modulation circuit 8 is connected to the pixel 2 via a first control line 11, a second control line 12, a first power supply line 13, a second power supply line 14, and a common electrode power supply line 15. Yes. The scanning line driving circuit 6, the data line driving circuit 7, and the common power supply modulation circuit 8 are controlled by the controller 10. The control lines 11 and 12, the power supply lines 13 and 14, and the common electrode power supply line 15 are used as common lines in all the pixels 2.

FIG. 2 is a diagram illustrating a circuit configuration of the pixel 2.
The pixel 2 is common to a driving TFT (Thin Film Transistor) 24 (pixel switching element), an SRAM (Static Random Access Memory) 25, a switch circuit 35, and a pixel electrode (first electrode) 21. An electrode (counter electrode, second electrode) 22 and an electrophoretic element 23 are included.

  The driving TFT 24 is composed of an N-MOS (Negative Metal Oxide Semiconductor). The scanning TFT 4 is connected to the gate portion of the driving TFT 24, the data line 5 is connected to the source side, and the SRAM 25 is connected to the drain side. The driving TFT 24 connects the data line 5 and the SRAM 25 during the period when the selection signal is input from the scanning line driving circuit 6 through the scanning line 4, thereby connecting the data line driving circuit 7 through the data line 5. This is used for inputting an input image signal to the SRAM 25.

  The SRAM 25 is composed of two P-MOS (Positive Metal Oxide Semiconductors) 25p1 and 25p2 and two N-MOSs 25n1 and 25n2. The first power supply line 13 is connected to the source side of the P-MOSs 25p1 and 25p2, and the second power supply line 14 is connected to the source side of the N-MOSs 25n1 and 25n2. Therefore, the source sides of the P-MOS 25p1 and the P-MOS 25p2 are the high potential power terminal PH of the SRAM 25, and the source sides of the N-MOS 25n1 and the N-MOS n2 are the low potential power terminal PL of the SRAM 25.

The switch circuit 35 includes a first transfer gate 36 and a second transfer gate 37. The first transfer gate 36 includes a P-MOS 36p and an N-MOS 36n. The second transfer gate 37 includes a P-MOS 37p and an N-MOS 37n.
The source side of the first transfer gate 36 is connected to the first control line 11, and the source side of the second transfer gate 37 is connected to the second control line 12. The drain sides of the transfer gates 36 and 37 are connected to the pixel electrode 21.

The SRAM 25 includes an input terminal N1 connected to the drain side of the driving TFT 24, and a first output terminal N2 and a second output terminal N3 connected to the switch circuit 35.
The drain side of the P-MOS 25p1 and the drain side of the N-MOS 25n1 of the SRAM 25 function as the input terminal N1 of the SRAM 25. The input terminal N1 is connected to the drain side of the driving TFT 24, and is also connected to the second output terminal N3 of the SRAM 25 (the gate portion of the P-MOS 25p2 and the gate portion of the N-MOS 25n2).
Further, the second output terminal N 3 is connected to the gate portion of the N-MOS 36 n of the first transfer gate 36 and the gate portion of the P-MOS 37 p of the second transfer gate 37.

The drain side of the P-MOS 25p2 and the drain side of the N-MOS 25n2 of the SRAM 25 function as the first output terminal N2 of the SRAM 25.
The first output terminal N2 is connected to the gate portion of the P-MOS 25p1 and the gate portion of the N-MOS 25n1, and the gate portion of the P-MOS 36p of the first transfer gate 36 and the N of the second transfer gate 37. -It is connected to the gate part of the MOS 37n.

The SRAM 25 is used to hold the image signal sent from the driving TFT 24 and to input the image signal to the switch circuit 35.
The switch circuit 35 functions as a selector that selectively selects one of the first and second control lines 11 and 12 based on the image signal input from the SRAM 25 and connects to the pixel electrode 21. At this time, only one of the first and second transfer gates 36 and 37 operates according to the level of the image signal.

Specifically, when a high level (H) is input to the input terminal N1 of the SRAM 25 as an image signal, a low level (L) is output from the first output terminal N2, so the first output terminal N2 Among these transistors, the P-MOS 36p operates, and the N-MOS 36n connected to the second output terminal N3 (input terminal N1) operates to drive the transfer gate 36. Therefore, the first control line 11 and the pixel electrode 21 are electrically connected.
On the other hand, when a low level (L) is input to the input terminal N1 of the SRAM 25 as an image signal, a high level (H) is output from the first output terminal N2, so that it is connected to the first output terminal N2. Among the transistors, the P-MOS 37n operates, and the N-MOS 37p connected to the second output terminal N3 (input terminal N1) operates to drive the transfer gate 37. Therefore, the second control line 12 and the pixel electrode 21 are electrically connected.
Then, the control line 11 or 12 is electrically connected to the pixel electrode 21 through the operated transfer gate, and a potential is input to the pixel electrode 21.

The electrophoretic element 23 displays an image by the potential difference between the pixel electrode 21 and the common electrode 22. The common electrode 22 is connected to the common electrode power supply wiring 15.
FIG. 3 is a partial cross-sectional view of the display unit 3 in the electrophoretic display device 1. The display unit 3 has a configuration in which the electrophoretic element 23 is sandwiched between an element substrate 28 having a pixel electrode 21 and a counter substrate 29 having a common electrode 22. The electrophoretic element 23 is composed of a plurality of microcapsules 40. The electrophoretic element 23 is fixed between the substrates 28 and 29 using an adhesive 30. That is, the adhesive layer 30 is formed between the electrophoretic element 23 and both the substrates 28 and 29.
The adhesive layer 30 on the element substrate 28 side is necessary for bonding to the surface of the pixel electrode 21, but the adhesive layer 30 on the counter substrate 29 side is not essential. This is because the common electrode 22, the plurality of microcapsules 40, and the adhesive layer 30 on the counter substrate 29 side are pre-fabricated with respect to the counter substrate 29 in a consistent manufacturing process, and are handled as an electrophoretic sheet. In some cases, the reason why the adhesive layer is necessary is that only the adhesive layer 30 on the element substrate 28 side is assumed.

  The element substrate 28 is a substrate made of, for example, glass or plastic. A pixel electrode 21 is formed on the element substrate 28, and the pixel electrode 21 is formed in a rectangular shape for each pixel 2. Although not shown, the scanning lines 4, the data lines 5, and the control lines shown in FIGS. 11 and 12, power supply lines 13 and 14, common electrode power supply wiring 15, driving TFT 24, SRAM 25, switch circuit 35 and the like are formed.

Since the counter substrate 29 is on the image display side, the counter substrate 29 is a substrate having translucency such as glass. The common electrode 22 formed on the counter substrate 29 is made of a material having translucency and conductivity. For example, MgAg (magnesium silver), ITO (indium tin oxide), IZO (indium zinc). Oxide) or the like.
The electrophoretic element 23 is generally formed in advance on the counter substrate 29 side and is handled as an electrophoretic sheet including the adhesive layer 30. A protective release paper is attached to the adhesive layer 30 side.
In the manufacturing process, the display unit 3 is formed by attaching the electrophoretic sheet from which the release paper is peeled off to the separately manufactured element substrate 28 on which the pixel electrode 21 and the circuit are formed. Yes. For this reason, in a general configuration, the adhesive layer 30 exists only on the pixel electrode 21 side.

FIG. 4 is a configuration diagram of the microcapsule 40. The microcapsule 40 is formed of a polymer resin having a particle size of, for example, about 50 μm and having translucency such as acrylic resin such as polymethyl methacrylate and polyethyl methacrylate, urea resin, and gum arabic. The microcapsule 40 is sandwiched between the common electrode 22 and the pixel electrode 21 described above, and a plurality of microcapsules 40 are arranged vertically and horizontally in one pixel. A binder (not shown) for fixing the microcapsule 40 is provided so as to fill the periphery of the microcapsule 40.
Inside the microcapsule 40, a dispersion medium 41 and charged particles of a plurality of white particles 42 and a plurality of black particles 43 as electrophoretic particles are enclosed.

The dispersion medium 41 is a liquid that disperses the white particles 42 and the black particles 43 in the microcapsules 40.
Examples of the dispersion medium 41 include alcohol solvents such as water, methanol, ethanol, isopropanol, butanol, octanol, and methyl cellosolve, various esters such as ethyl acetate and butyl acetate, and ketones such as acetone, methyl ethyl ketone, and methyl isobutyl ketone. , Aliphatic hydrocarbons such as pentane, hexane and octane, alicyclic hydrocarbons such as cyclohexane and methylcyclohexane, benzene, toluene, xylene, hexylbenzene, hebutylbenzene, octylbenzene, nonylbenzene, decylbenzene , Aromatic hydrocarbons such as benzenes having a long-chain alkyl group such as undecylbenzene, dodecylbenzene, tridecylbenzene, tetradecylbenzene, etc., methylene chloride, chloroform, carbon tetrachloride, 1,2-dichloroethane, etc. Gen hydrocarbons include those obtained by blending a surfactant or the like alone or a mixture thereof such as carboxylic acid salts, or various other oils.

The white particles 42 are particles (polymer or colloid) made of a white pigment such as titanium dioxide, zinc white, and antimony trioxide, and are negatively charged, for example.
The black particles 43 are particles (polymer or colloid) made of a black pigment such as aniline black or carbon black, and are positively charged, for example.
For this reason, the white particles 42 and the black particles 43 can move in the electric field generated by the potential difference between the pixel electrode 21 and the common electrode 22 in the dispersion medium 41.

  These pigments include electrolytes, surfactants, metal soaps, resins, rubbers, oils, varnishes, charge control agents composed of particles such as compounds, titanium-based coupling agents, aluminum-based coupling agents, silanes as necessary. A dispersant such as a system coupling agent, a lubricant, a stabilizer, and the like can be added.

  The white particles 42 and the black particles 43 are covered with ions in the solvent, and an ion layer 44 is formed on the surfaces of these particles. An electric double layer is formed between the charged white particles 42 and black particles 43 and the ion layer 44. In general, it is known that charged particles such as the white particles 42 and the black particles 43 hardly react to the electric field and hardly move even when an electric field having a frequency of 10 kHz or higher is applied. It is known that ions around the charged particles have a particle diameter much smaller than that of the charged particles, and therefore move according to the electric field when an electric field having an electric field frequency of 10 kHz or more is applied.

FIG. 5 is a diagram for explaining the operation of the microcapsule 40. Here, an ideal case where the ion layer 44 is not formed will be described as an example.
A voltage is applied between the pixel electrode 21 and the common electrode 22 so that the voltage of the common electrode 22 becomes relatively high. Then, as shown in FIG. 5A, the positively charged black particles 43 are attracted toward the pixel electrode 21 in the microcapsule 40 by the Coulomb force. On the other hand, the negatively charged white particles 42 are attracted toward the common electrode 22 in the microcapsule 40 by the Coulomb force. As a result, the white particles 42 are collected on the display surface side (the common electrode 22 side) in the microcapsule 40, and the color (white) of the white particles 42 is displayed on the display surface.

  Conversely, a voltage is applied between the pixel electrode 21 and the common electrode 22 so that the potential of the pixel electrode 21 is relatively high. Then, as shown in FIG. 5B, the negatively charged white particles 42 are attracted toward the pixel electrode 21 by the Coulomb force. Further, the positively charged black particles 43 are attracted to the common electrode 22 side by Coulomb force. As a result, the black particles 43 gather on the display surface side of the microcapsule 40, and the color (black) of the black particles 43 is displayed on the display surface.

  In addition, it can be set as the electrophoretic display device 1 which displays red, green, blue, etc. by replacing the pigment used for the white particle 42 and the black particle 43 with pigments, such as red, green, and blue, for example.

[First driving method]
Next, a driving method of the electrophoretic display device 1 according to the present embodiment will be described with reference to the drawings.
FIG. 6 is a diagram illustrating a timing chart according to the first driving method. This figure shows a state in which an image is displayed by performing an operation in the order of the power-off period ST11, the image signal input period ST12, the black image display period ST13, the white image display period ST14, and the power-off period ST15. These operations are summarized in Table 1.

  In FIG. 6, the potential of the high potential power supply terminal PH of the SRAM 25 (the potential of the first power supply line 13) Vdd, the potential S1 of the first control line 11, and the potential S2 of the second control line 12 are common. The potential Vcom of the electrode power supply wiring 15 is shown. Further, specific voltage values (5 V, 15 V, 0 V, etc.) shown in Table 1 and FIG. 6 are merely illustrated for easy understanding of the description, and do not limit the technical scope of the present invention.

  In the power supply off period ST11 shown in Table 1 and FIG. 6, the first power supply line 13, the second power supply line 14, the first control line 11, the second control line 12, and the common electrode 22 are all other It is in an open state (high impedance state (Hi-Z)) electrically disconnected from the circuit. At this time, the display unit 3 holds a previously displayed image.

Next, the image signal input period ST12 (first step) will be described.
A potential of about 5 V (high level; indicated as H (5 V)) is input from the common power supply modulation circuit 8 of FIG. 1 to the SRAM 25 of FIG. The SRAM 25 is driven by inputting a low level (second potential) potential of approximately 0 V (shown as L (0 V)) through the power supply line 14.
At this time, the first control line 11, the second control line 12, and the common electrode power supply wiring 15 are electrically disconnected by the common power supply modulation circuit 8 (Hi-Z).

The scanning line driving circuit 6 in FIG. 1 inputs a selection signal to the scanning line Y1. By this selection signal, the driving TFT 24 of the pixel 2 connected to the scanning line Y1 is driven, and the SRAM 25 of the pixel 2 connected to the scanning line Y1 is connected to the data lines X1, X2,.
The data line driving circuit 7 in FIG. 1 inputs an image signal to the SRAM 25 of the pixel 2 connected to the scanning line Y1 by supplying the image signal to the data lines X1, X2,.

  When the image signal is input, the scanning line driving circuit 6 stops supplying the selection signal to the scanning line Y1, and cancels the selection state of the pixel 2 connected to the scanning line Y1. This operation is sequentially executed up to the pixels 2 connected to the scanning line Ym, and image signals are input to the SRAMs 25 of all the pixels 2. Thereby, the potential corresponding to the image data is stored in the SRAM 25 of the pixel 2 constituting the display unit 3.

Next, the process proceeds to the black image display period ST13 (second step).
The first power supply line 13 (high potential power supply terminal PH) is supplied with a potential of about 15 V (shown as H (15 V)) which is a high level (first potential) from the common power supply modulation circuit 8 of FIG. Is done. Therefore, the image signal input to the SRAM 25 at 5V is held at a higher potential (15V).
The first control line 11 is electrically connected to the common power supply modulation circuit 8, and a high level potential (H (15 V)) is supplied to the first control line 11. As a result, a high level is input to the source side of the first transfer gate 36. At this time, the second control line 12 is in a high impedance state that is electrically disconnected.
A pulse-like signal that repeats a high level (H (15 V)) period and a low level (L (0 V)) period at a constant cycle is input to the common electrode 22 via the common electrode power supply wiring 15. .

At this time, in the pixel 2 whose image signal is high level, the potential of the first output terminal N2 of the SRAM 25 is low level, and the potential of the second output terminal N3 (input terminal N1) is high level. Therefore, the first transfer gate 36 is driven to connect the pixel electrode 21 and the first control line 11. As a result, a high level potential (H (15 V)) is input to the pixel electrode 21.
When the potential Vcom of the common electrode 22 to which a pulse signal is input is at a low level (L (0 V)), a large potential difference is generated between the electrodes 21 and 22, and FIG. As shown, the black particles 43 of the electrophoretic element 23 are attracted to the common electrode 22, and the white particles 42 are attracted to the pixel electrode 21. As a result, black is displayed on the pixel 2.

  On the other hand, in the pixel 2 whose image signal is at low level, the potential of the first output terminal N2 of the SRAM 25 is at high level, and the potential of the second output terminal N3 (input terminal N1) is at low level. . Therefore, the second transfer gate 37 is driven to connect the pixel electrode 21 and the second control line 12. However, since the second control line 12 is electrically disconnected, the pixel electrode 21 holds the potential for displaying the previous image as it is. As a result, the electrophoretic element 23 of this pixel does not operate and holds the previous image as it is.

Next, the white image display period ST14 (second step) will be described.
When the white image display period ST14 is started, the common power supply modulation circuit 8 of FIG. (Hi-Z). As a result, a low-level potential (L (0 V)) is input from the second control line 12 to the source side of the second transfer gate 37.

At this time, in the pixel 2 whose image signal is at the low level, the potential of the first output terminal N2 of the SRAM 25 is at the high level, and the potential of the second output terminal N3 (input terminal N1) is at the low level. Therefore, the second transfer gate 37 is driven to connect the pixel electrode 21 and the second control line 12. As a result, a low-level potential is input to the pixel electrode 21.
When the potential Vcom of the common electrode 22 to which a pulse signal is input is at a high level (H (15 V)), a large potential difference is generated between the electrodes 21 and 22, and FIG. As shown, the white particles 42 are attracted to the common electrode 22, and the black particles 43 are attracted to the pixel electrode 21. As a result, white is displayed on the pixel 2.

  On the other hand, in the pixel 2 whose image signal is high level, the potential of the first output terminal N2 of the SRAM 25 is low level, and the potential of the second output terminal N3 (input terminal N1) is high level. . Therefore, the first transfer gate 36 is driven, and the pixel electrode 21 and the first control line 11 are connected. However, since the first control line 11 is electrically disconnected, the potential of the pixel electrode 21 does not change, and the black image displayed in the black image display period ST13 described above is held.

In the black image display period ST13 and the white image display period ST14 described above, a reference pulse that repeats a high level (H) and a low level (L) at a predetermined cycle is input to the common electrode 22.
This driving method is referred to as “common swing driving” in the present application. The common swing drive is defined as a drive method in which a pulse that repeats a high level and a low level is applied to the common electrode 22 for at least one cycle in the image rewriting period.

According to this common swing driving method, the black particles and the white particles can be moved to the desired electrode more reliably, so that the contrast can be increased. In addition, since the potential applied to the pixel electrode and the common electrode can be controlled by binary values of high level (H) and low level (L), the voltage can be reduced and the circuit configuration can be simplified. Further, when a TFT (Thin Film Transistor) is used as the switching element of the pixel electrode 21, there is an advantage that the reliability of the TFT can be secured by low voltage driving.
Note that the frequency and the number of cycles of the common swing drive are preferably determined as appropriate according to the specifications and characteristics of the electrophoretic element 23.

As described above, when a new image is displayed on the display unit 3, the process proceeds to the power-off period ST15.
In the power-off period ST15, the common power supply modulation circuit 8 shown in FIG. 1 has the first control line 11, the second control line 12, the first power supply line 13 (high potential power supply terminal PH), the second The power line 14 (low potential power terminal PL) and the common electrode common line 15 are electrically disconnected. As a result, each wiring connected to the pixel 2 enters a high impedance state.

  By providing the power-off period ST15, an image can be held without consuming power. Further, by electrically disconnecting the first control line 11 and the second control line 12 that are power sources of the pixel electrode 21, the leak path from the pixel electrode 21 to the wiring is cut off, so that the leakage current is reduced. It is also effective for reduction.

Furthermore, by repeating the image signal input period ST12, the black image display period ST13, the white image display period ST14, and the power-off period ST15 (ST11), the images can be updated and displayed sequentially.
Note that the order of the white image display period ST13 and the black image display period ST14 may be switched.

  In addition, a reverse image can be displayed by switching the potentials supplied to the first control line 11 and the second control line 12 to each other. In other words, if S1 is set to the low level and S2 is set to the high level, the display image can be inverted by a simple operation without inputting the inverted image signal to the SRAM 25 of all the pixels.

[Prevention of leakage current]
7, 8, and 9 schematically illustrate the adjacent pixels 2 of the display unit 3 in FIG. 1. FIG. 7 shows the states of the pixels 2A and 2B in the power-off period ST11, the image signal input period ST12, and the power-off period ST15. FIG. 8 shows the state of the pixels 2A and 2B in the black image display period ST13. FIG. 9 shows the state of the pixels 2A and 2B in the white image display period ST14.

In these drawings, the pixel 2A shown on the left side of the drawing includes a driving TFT 24a, an SRAM 25a, a switch circuit 35a including a first transfer gate 36a and a second transfer gate 37a, and a pixel electrode 21a. The pixel 2B shown on the right side of the drawing includes a driving TFT 24b, an SRAM 25b, a switch circuit 35b including a first transfer gate 36b and a second transfer gate 37b, and a pixel electrode 21b.
The pixels 2A and 2B have no structural difference from the pixel 2 shown in FIG. 2, and the subscripts “A” and “B” are added for the sake of convenience to identify adjacent pixels. In addition, the subscripts “a” and “b” attached to each component are added to clarify whether the component belongs to the pixel 2A or 2B, and there is no other intention.

In FIG. 7, FIG. 8, and FIG. 9, adjacent pixels 2 (2A, 2B) display different colors. For example, the pixel 2A displays black and the pixel 2B displays white.
At this time, a high level (H) potential is input to the pixel electrode 21a, and a low level (L) is input to the pixel electrode 21b. Since an electric field due to a large potential difference is generated between the pixel electrodes 21 a and 21 b arranged adjacent to each other, the pixel electrodes 21 a and 21 b try to flow a leak current through the adhesive layer 30.

  However, in the first driving method described above, in the image signal input period ST12 (FIG. 7), the black image display period ST13 (FIG. 8), the white image display period ST14 (FIG. 9), and the power-off period ST15 (FIG. 7). 1, at least one of the two control lines 11 and 12 is electrically disconnected by the common power supply modulation circuit 8 in FIG. 1. More specifically, in the state shown in FIG. 7, both the first and second control lines 11 and 12 are electrically disconnected. In the state shown in FIG. 8, the second control line 12 is electrically disconnected, and in the state shown in FIG. 9, the first control line 11 is electrically disconnected.

  For this reason, a leak current does not flow between the pixel electrodes 21a and 21b. Therefore, according to this driving method, leakage current between pixels can be suppressed. The operation capable of suppressing the leakage current in this way will be described below in comparison with the conventional circuit shown in FIG.

  FIG. 10 is a diagram showing a circuit configuration when a conventional circuit is used. In the figure, two adjacent pixels 102A and 102B are schematically shown.

A pixel 102A shown on the left side of FIG. 10 includes a driving TFT 124a, an SRAM 125a, and a pixel electrode 21a. A pixel 102B shown on the right side of FIG. 10 includes a driving TFT 124b, an SRAM 125b, and a pixel electrode 21b.
The SRAM 125a includes P-MOSs 125ap1 and 125ap2, and N-MOSs 125an1 and 125an2. The SRAM 125b includes P-MOSs 125bp1 and 125bp2, and N-MOSs 125bn1 and 125bn2.
That is, the pixels 102A and 102B are obtained by omitting the switch circuit 35 from the pixel 2 shown in FIG. 2 and directly connecting the output terminal of the memory circuit and the pixel electrode.

The adjacent pixels 102A and 102B display different colors. For example, the pixel 102A displays black, and the pixel 102B displays white.
The pixel electrode 21a receives a high level (H) potential Vdd from the first power supply line 13 via the P-MOS 125ap2, and the pixel electrode 21b receives the N-MOS 125bn1 from the second power supply line 14. A low-level (L) potential Vss is input through the terminal.

At this time, an electric field (lateral electric field) due to a large potential difference is generated between the pixel electrodes 21a and 21b. Thus, a leakage path from the first power supply line 13 to the second power supply line 14 via the P-MOS 125ap2 of the SRAM 125a, the pixel electrode 21a, the adhesive layer 30, the pixel electrode 21b, and the N-MOS 125bn2 of the SRAM 125b. And a leakage current LC flows between the pixels 102A and 102B.
When the leakage current LC flows, the power consumption of the entire device increases. Further, the leak current may become a corrosion current, which may corrode the pixel electrodes 21a and 21b, which affects the reliability of the electrophoretic display device.

  On the other hand, in the driving method of the present invention, when black image display and white image display are performed, one of the control lines 11 and 12 in FIG. 2 is electrically disconnected, so that no leakage current occurs.

More specifically, in the electrophoretic display device of the present invention, as shown in FIG. 7, the switch circuits 35a and 35b are provided so that the pixel electrodes 21a and 21b are not the SRAMs 25a and 25b but the switch circuits 35a and 35b. A potential is supplied from the first and second control lines 11 and 12 via the.
Therefore, the leakage path formed by the electric field between the pixel electrodes 21a and 21b is the first transfer gate 36a, the pixel electrode 21a, the adhesive layer 30, and the pixel from the first control line 11 in FIGS. This is a path that reaches the second control line 12 via the electrode 21b and the second transfer gate 37b.

  In the driving method of the present invention, both the first and second control lines 11 and 12 are electrically disconnected in the power-off period ST11 and the like shown in FIG. Further, in the black image display period ST13 and the white image display period ST14 shown in FIGS. 8 and 9, one of the first and second control lines 11 and 12 is electrically disconnected. Therefore, the leak path from the first control line 11 to the second control line 12 via the pixels 2A and 2B as described above is always cut off, and no leak current is generated.

[Second Driving Method]
Next, the second driving method will be described. The second driving method is a driving method in which the leak current can be more reliably prevented by further devising the first driving method. Therefore, in FIG. 11, the same reference numerals are given to the periods common to the first driving method, and duplicate descriptions are omitted.

  FIG. 11 is a timing chart according to the second driving method. In this figure, the operation is performed in the order of a power-off period ST11, an image signal input period ST12, a black image display period ST13, a display image holding period ST21, a white image display period ST14, a display image holding period ST22, and a power-off period ST15. This shows how the image is displayed. These operations are summarized in Table 2.

  In FIG. 11, the potential of the high potential power supply terminal PH of the SRAM 25 (the potential of the first power supply line 13) Vdd, the potential S1 of the first control line 11, and the potential S2 of the second control line 12 are common. The potential Vcom of the electrode power supply wiring 15 is shown. In addition, the specific voltage values (5 V, 15 V, 0 V, etc.) shown in Table 2 and FIG. 11 are merely shown for easy understanding, and do not limit the technical scope of the present invention.

  A difference from the first driving method described above is that a display image holding period ST21 is provided between the black image display period ST13 and the white image display period ST14, and the white image display period ST14 and the power-off period ST15. A display image holding period ST22 is provided between them. Since the operation in other periods is the same as the corresponding period in the first driving method, the period from the black image display period ST13 to the display image holding period ST22 will be described in detail below.

  In the black image display period ST13, the potential S1 of the first control line 11 is set to a high level (H (15V)), and the second control line 12 is set to a high impedance state where it is electrically disconnected. The common electrode 22 (Vcom) receives a pulse-like signal that repeats a high level (H (15 V)) and a low level (L (0 V)). Thereby, similarly to the first driving method, black display is performed in the pixel 2 to which a predetermined image signal (high level) is inputted.

Thereafter, the display image holding period ST21 is started.
In the display image holding period ST21, the first control line 11 and the second control line 12 are electrically disconnected by the common power supply modulation circuit 8 of FIG. 1, and these wirings are in a high impedance state (Hi-Z). Become. At this time, a pulse signal continues to be input to the common electrode 22.

  Thereafter, when the white image display period ST14 is entered, the first control line 11 maintains the electrically disconnected high impedance state, but the second control line 12 is connected to the low level (L from the common power supply modulation circuit 8). ) Is supplied. Further, a pulse-like signal continues to be input to the common electrode 22. Thereby, similarly to the first driving method, white display is performed in the pixel 2 to which a predetermined image signal (low level) is inputted.

  Thereafter, the process further proceeds to the display image holding period ST22. Also in this period, as in the previous display image holding period ST21, the first and second control lines 11 and 12 are in a high impedance state where they are electrically disconnected. In the present embodiment, the pulse signal is continuously input to the common electrode 22 even in the display image holding period ST22. However, the pulse input to the common electrode 22 may be stopped and the common electrode 22 may be in a high impedance state. .

  As described above, in the driving method of the present embodiment, the black image display period ST13 in which only the first control line 11 is connected and the white image display period ST13 in which only the second control line 12 is connected. Are provided with display image holding periods ST21 and ST22 in which both the first and second control lines 11 and 12 are cut to be in a high impedance state.

  When both the first and second control lines 11 and 12 are switched, even if both are instantaneously connected, a leak current is generated because the inter-pixel leakage path is connected. However, if an image is displayed by this driving method, both wirings are surely electrically disconnected before switching between the first control line 11 and the second control line 12, and therefore, as shown in FIGS. 7 to 9. As described above, at least one of the first and second control lines 11 and 12 is always in an electrically disconnected state. Therefore, the leakage path through the adhesive layer 30 is reliably cut off, so that no leakage current is generated.

In the present embodiment, after the display image holding period ST22, the black image display period ST13 and the white image display period ST14 may be repeated again without shifting to the power-off period ST15. In this case, if the black image display period ST13 and the white image display period ST14 are shortened and the number of repetitions is increased, the black display and the white display on the display unit 3 are repeated in a short time. Is in a state where it can be seen early.
Note that a display image holding period in which the first and second control lines 11 and 12 are in a high impedance state may be provided in all the periods between the black image display period ST13 and the white image display period ST14 that are repeated. preferable.

  In the present embodiment, the display image holding period ST22 does not necessarily have to be provided since the display image holding period ST22 is shifted to the power-off period ST15 immediately after the display image holding period ST22. However, if the black image display period ST13 and the immediately subsequent display image holding period and the white image display period ST14 and the immediately subsequent display image holding period are configured as a series of operations, the first operation is always performed after the display operation. Since the operation for setting the second control lines 11 and 12 in the high impedance state is inserted, a driving method that can reliably prevent the leakage current can be obtained.

[Third driving method]
Next, the third driving method will be described. The third driving method is a driving method for displaying white or black on all the pixels 2. That is, the driving method can be applied to an operation for erasing an image.
12 and 13 are examples of timing charts according to the third driving method. In this example, a state where an image is erased after being displayed by the first driving method is shown.

  12 and 13, the potential of the high potential power terminal PH of the SRAM 25 (the potential of the first power supply line 13) Vdd, the potential S1 of the first control line 11, and the potential S2 of the second control line 12 are shown. The potential Vcom of the common electrode power supply wiring 15 is shown. Moreover, the specific voltage values (5V, 15V, 0V, etc.) shown in FIGS. 12 and 13 are merely shown for ease of explanation, and do not limit the technical scope of the present invention.

  In FIG. 12, the image display period (1) by the first driving method and the all black erasing period (3-1) by the third driving method are executed. The all black erasing period (3-1) includes a black image display period ST31 for all pixels and a power-off period ST32.

As shown in FIG. 12, when the image display operation is completed in the image display period (1) by the first driving method, all the wirings are in a high impedance state where they are electrically disconnected (power-off period ST15). .
From this image holding state, the process proceeds to a black image display period ST31 for all the pixels 2 in the all black erasing period (3-1).

In the black image display period ST31, the common power supply modulation circuit 8 inputs a high level (H (15V)) to both the first control line 11 and the second control line 12.
At this time, in the pixel 2, the first transfer gate 36 or the second transfer gate 37 is driven by the image signal held in each SRAM 25. Specifically, in the pixel 2 whose image signal is high level, the potential of the first output terminal N2 of the SRAM 25 is low level, and the potential of the second output terminal N3 (input terminal N1) is high level. . Therefore, the first transfer gate 36 is turned on, and the pixel electrode 21 and the first control line 11 are connected.
On the other hand, in the pixel 2 whose image signal is at low level, the potential of the first output terminal N2 of the SRAM 25 is at high level, and the potential of the second output terminal N3 (input terminal N1) is at low level. Therefore, the second transfer gate 37 is turned on, and the pixel electrode 21 and the second control line 12 are connected.

Since the high level is supplied to both the control lines 11 and 12, the high level is input to the pixel electrodes 21 of all the pixels 2. The common electrode 22 receives a pulse-like signal that repeats a high level period and a low level period.
As a result, black is displayed in all the pixels 2 regardless of the potential (high level / low level) of the image signal held in the SRAM 25. Thereafter, the process proceeds to the power-off period ST32, and the state where all the pixels 2 are displayed in black is maintained.

  Next, in the driving method shown in FIG. 13, an image display period (1) by the first driving method and an all white erasing period (3-2) by the third driving method are executed. The all black erasing period (3-2) includes a white image display period ST33 for all pixels and a power off period ST32.

  As shown in FIG. 13, from the image holding state after the image display period (1) by the first driving method to the white image display period ST33 for all the pixels 2 in the all white erasing period (3-2). Migrate to

  When the white image display period ST33 is started, the common power supply modulation circuit 8 inputs a low level (L (0 V)) to both the first control line 11 and the second control line 12. The common electrode 22 receives a pulse-like signal that repeats a high-level period and a low-level period, and white is displayed in all the pixels 2 based on the potential difference between the pixel electrode 21 and the common electrode 22. The Thereafter, the process proceeds to the power-off period ST32, and the state where all the pixels 2 are displayed in white is maintained.

FIG. 14 is a diagram illustrating a state of two adjacent pixels 2A and 2B in the third driving method.
As described above, in the black image display period ST31 and the white image display period ST33, both the first and second control lines 11 and 12 are electrically connected. However, the pixel electrodes 21a and 21b are both input with a high level, or both are input with a low level. Therefore, there is no potential difference between the pixel electrodes 21a and 21b, and no leak current flows.

[Fourth Driving Method]
Next, a fourth driving method according to the first embodiment will be described with reference to FIG.
FIG. 17 is a diagram illustrating a timing chart according to the fourth driving method. In FIG. 17, the potential of the high potential power supply terminal PH of the SRAM 25 (the potential of the first power supply line 13) Vdd, the potential S1 of the first control line 11, and the potential S2 of the second control line 12 are common. The potential Vcom of the electrode power supply wiring 15 is shown. Moreover, the specific voltage values (5V, 15V, 0V, etc.) shown in FIG. 17 are merely shown for easy understanding, and do not limit the technical scope of the present invention.

  The fourth driving method is a driving method in which a display image holding period (4) is provided instead of the power-off period ST15 in the first driving method described above. Therefore, in FIG. 17, the same period as that of the first driving method is denoted by the same reference numeral, and redundant description is omitted.

  In the first driving method, after the display image of the display unit 3 is updated, the process proceeds to a power-off period ST15 in which all wirings are in a high impedance state. On the other hand, in the fourth driving method, the display image holding period (4) in which the interval period ST41 and the refresh period ST42 are alternately provided is entered. In other words, this is a driving method that allows a display image to be kept in good contrast for a long time.

  As shown in FIG. 17, after the white image display period ST14 by the first driving method ends, when the period shifts to the interval period ST41, the first control line 11, the second control line 12, and the common electrode 22 are The common power supply modulation circuit 8 is in a high impedance state electrically disconnected. On the other hand, the high-potential power supply terminal PH (first power supply line 13) of the SRAM 25 is not brought into a high impedance state, but is stepped down from 15V to 5V and maintained at a high level. Although not shown, the potential Vss of the low potential power supply terminal PL (second power supply line 14) is held at a low level (L (0 V)). That is, in the interval period ST41, the SRAM 25 maintains the low voltage drive power-on state, and holds the image signal input in the image signal input period ST12.

  Note that the specific voltage values (15 V, 5 V) of the high potential power supply terminal PH are merely examples, and are not limited to these voltage values. For example, Vdd in the interval period ST41 can be set to a lower potential (for example, 1 V) as long as an image signal can be held in the SRAM 25.

  Next, after the transition to the interval period ST41, the transition is made to the refresh period ST42 after a predetermined time has elapsed. The refresh period ST42 includes a black image display period ST43 and a white image display period ST44.

  First, when the black image display period ST43 starts, the potential Vdd of the high potential power supply terminal PH of the SRAM 25 is raised to 15V. Further, a high level (H (15 V)) is input to the first control line 11. The second control line 12 remains in a high impedance state.

At this time, in the pixel 2 holding the high-level image signal, the first transfer gate 36 is turned on based on the output of the SRAM 25, and the pixel electrode 21 and the first control line 11 are connected. As a result, a high level (H (15 V)) is input from the first control line 11 to the pixel electrode 21. Then, a pulse-like signal is input to the common electrode 22, and the black display operation of the pixel 2 is performed based on the potential difference between the pixel electrode 21 and the common electrode 22.
With this black display operation, it is possible to recover the contrast that has been decreasing with time in the black display pixel 2 to the state immediately after the display image is updated.
Note that in the pixel 2 holding the low-level image signal, the second transfer gate 37 is turned on, and the second control line 12 and the pixel electrode 21 are connected. However, the second control line 12 is in a high impedance state, and the potential of the pixel electrode 21 does not change. Therefore, the display does not change in this pixel 2.

Next, when the white image display period ST44 is started, the first control line 11 is set to a high impedance state while Vdd is maintained at 15 V, and the second control line 12 is set to a low level (L (0 V)). Entered. Thereby, in the pixel 2 holding the low-level image signal, the second transfer gate 37 is turned on based on the output of the SRAM 25, and the pixel electrode 21 and the second control line 12 are connected. As a result, a low level is input to the pixel electrode 21. Since the pulse signal is input to the common electrode 22, the white display operation of the pixel 2 is performed based on the potential difference between the pixel electrode 21 and the common electrode 22.
With this white display operation, the contrast that has been decreasing over time in the white display pixels 2 can be recovered to the state immediately after the display image is updated.
In the white image display period ST44, the display of the black display pixels 2 does not change.

  After the contrast of the display image is restored in the refresh period ST42, the process proceeds to the interval period ST41 again. That is, while the image signal is held with the minimum power consumption by reducing the drive voltage of the SRAM 25, the other wirings are in a high impedance state to prevent leakage and hold the display image for a long time. After that, if the interval period ST41 of the predetermined period and the refresh period ST42 are alternately repeated, the contrast can be satisfactorily maintained.

  As described above, according to the fourth driving method, by providing the interval period ST41 and the refresh period ST42, a display image can be held over a long period without reducing the contrast. In the interval period ST41, the SRAM 25 is kept in the operating state without being turned off, so that the refresh operation can be performed without inputting the image signal to the SRAM 25 again. Power consumption can be eliminated. Further, since the potential Vdd of the high potential power supply terminal PH is lowered in the interval period ST41, an increase in power consumption in the display image holding period (4) can be suppressed.

  Although the length of the interval period ST41 is not particularly limited, if the time is lengthened, the width of the contrast decrease becomes large, and accordingly, the refresh period ST42 has to be lengthened. In addition, the contrast change due to the refresh operation is noticeable and easily visible. Therefore, it is preferable to set the length of the interval period ST41 so that the refresh operation is performed when the contrast does not decrease excessively.

In the refresh period ST42, the order of the black image display period ST43 and the white image display period ST44 may be switched. Further, a period in which both the first and second control lines 11 and 12 are in a high impedance state may be provided between the black image display period ST43 and the white image display period ST44.
Further, as the refresh period ST42, a period in which black display and white display are simultaneously performed may be provided. In this case, in the refresh period ST42, a potential is simultaneously input to the first control line 11 and the second control line 12, and a pulse signal is input to the common electrode 22. In this driving method, since a potential is simultaneously input to the first and second control lines 11 and 12, leakage current is likely to occur. However, since the image refresh operation is completed in a short time, the display image is updated. Sometimes the effect on power consumption is less than when using a similar drive method.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the electrophoretic display device according to the present embodiment, a switch circuit including two transistors (first and second transistors) is used instead of the switch circuit 35 including four transistors in the first embodiment. It is provided. Hereinafter, a plurality of examples (first to third configuration examples) in which the configuration of the electrophoretic display device according to the second embodiment is changed will be described.

  In the first configuration example, a switch circuit using a P-MOS for the first transistor and an N-MOS for the second transistor is provided. The second configuration example includes a switch circuit using an N-MOS for both the first and second transistors. The third configuration example includes a switch circuit using a P-MOS for both the first and second transistors.

[First configuration example]
FIG. 18 is a circuit configuration diagram of the pixel 302 provided in the electrophoretic display device according to the first configuration example of the second embodiment. A pixel 302 shown in FIG. 18 has a switch circuit 335 including a P-MOS (first transistor) 336 and an N-MOS (second transistor) 337 instead of the switch circuit 35 of the pixel 2 shown in FIG. It is the structure provided with. Therefore, in the following, the same reference numerals are given to the same components as those in FIG. 2, and the detailed description thereof will be omitted.

  In the pixel 302, the switch circuit 335 is connected between the output terminal N <b> 2 of the SRAM 25 and the pixel electrode 21. The gate terminal of the P-MOS 336 and the gate terminal of the N-MOS 337 are connected to each other and to the output terminal N2 of the SRAM 25. The source terminal of the P-MOS 336 is connected to the first control line 11, and the drain terminal is connected to the pixel electrode 21. The source terminal of the N-MOS 337 is connected to the second control line 12, and the drain terminal is connected to the pixel electrode 21.

In the pixel 302 having the above configuration, when a high level (H) is input as an image signal, a low level potential (Vss) is output from the output terminal N <b> 2 of the SRAM 25. As a result, the P-MOS 336 is turned on, and the first control line 11 and the pixel electrode 21 are connected.
On the other hand, when a low level (L) is input as an image signal, a high level potential (Vdd) is output from the output terminal N2 of the SRAM 25. As a result, the N-MOS 337 is turned on, and the second control line 12 and the pixel electrode 21 are connected.

  Therefore, similarly to the pixel 2 according to the previous embodiment, the pixel 302 according to the present embodiment operates the switch circuit 335 based on the potential of the image signal input to the SRAM 25, and the first control line 11 or the second control line 11. By connecting the two control lines 12 and the pixel electrode 21, the potentials S <b> 1 and S <b> 2 of the first or second control lines 11 and 12 are input to the pixel electrode 21.

[Driving method]
Next, a driving method of the electrophoretic display device according to the first configuration example will be described with reference to Table 3 and FIGS. In the present embodiment, a plurality of driving modes (normal image display, counter image display, all white display, all black display) of the electrophoretic display device will be described.

  Table 3 shows normal image display (gradation display that matches the image data), reverse image display (display in which the image data is inverted in gradation), all white display (all pixels are displayed in white), all black display (all 5 is a table showing a comparison of potentials input to the pixel 302 in each operation of (display the black pixel).

  In Table 3, “image signal” is a high level (H) or low level (L) potential input to the data line 5. In Table 3 and FIGS. 19 to 29, “VH” is a high-level potential supplied to the first control line 11 or the second control line 12, and “VL” is the first control line. 11 or the low-level potential supplied to the second control line 12. “Vthp” is a threshold voltage of the P-MOS 336, and “Vthn” is a threshold voltage of the N-MOS 337.

<Normal image display>
FIG. 19 is a diagram illustrating a timing chart in normal image display. 20 and 21 are diagrams illustrating the state of two adjacent pixels in the normal image display.

Hereinafter, of the pixels 302 constituting the display unit 3, the description will be made on two adjacent pixels 302 </ b> A and 302 </ b> B shown in FIG. 20. The pixel 302A is a pixel that is displayed in black, and the pixel 302B is a pixel that is displayed in white.
The subscripts “A”, “B”, “a”, and “b” attached to the reference numerals of the components shown in FIGS. 20 and 21 are two adjacent pixels 302A and 302B, and those pixels. This is given to clearly identify the constituent element to which it belongs, and there is no structural difference from the pixel 302 shown in FIG.

  In FIG. 19, the potential S1 of the first control line 11, the potential S2 of the second control line 12, the potential Va of the pixel electrode 21a in the pixel 302A displayed in black, and the pixel in the pixel 302B displayed in white The potential Vb of the electrode 21b and the potential Vcom of the common electrode 22 are shown.

The normal image display sequence shown in FIG. 19 includes a normal image display period ST100 and a power-off period ST150. In the normal image display period ST100, a black image display period ST101 and a white image display period ST102 are sequentially executed.
FIG. 20 shows the state of the pixels 302A and 302B in the black image display period ST101. FIG. 21 shows the state of the pixels 302A and 302B in the white image display period ST102.

Although illustration is omitted, an image signal is input to the pixel 302 before the normal image display period ST100. Since the operation when inputting the image signal is the same as that in the image transmission signal input period ST12 described with reference to FIG. 6 in the first embodiment, the description is omitted here.
In the following description of each driving mode, it is assumed that a high level (L) image signal is held in the SRAM 25a of the pixel 302A, and a low level (L) image signal is held in the SRAM 25b of the pixel 302B. To do.

  First, in the black image display period ST101 in the normal image display period ST100, as shown in FIGS. 19 and 20, a high level potential VH is supplied to the first control line 11, and the second control line 12 is electrically connected. The high impedance state (Hi-Z) is disconnected.

Then, in the pixel 302A that holds a high level (H) image signal, the low level potential Vss is output from the output terminal N2 of the SRAM 25a. As a result, the P-MOS 336a is turned on, and the first control line 11 and the pixel electrode 21a are electrically connected, and the high-level potential VH is input to the pixel electrode 21a.
On the other hand, in the pixel 302B holding a low level (L) image signal, the high level potential Vdd is output from the output terminal N2 of the SRAM 25b, and the N-MOS 337b is turned on. However, since the second control line 12 is in a high impedance state, the pixel electrode 21b remains in a high impedance state.

The common electrode 22 receives a pulse-like signal that repeats a high level (VH) period and a low level (VL) period in a predetermined cycle.
As described above, based on the potential difference between the common electrode 22 and the pixel electrodes 21a and 21b, the pixel 302A is displayed in black, and the display of the pixel 302B is not changed.

Next, in the white image display period ST102, as shown in FIG. 19 and FIG. 21, the first control line 11 is brought into a high impedance state by being electrically disconnected, and the second control line 12 is set to the low level potential VL. Is supplied. As a result, the pixel electrode 21a connected to the first control line 11 via the P-MOS 336a is brought into a high impedance state, while the pixel electrode 21b connected to the second control line 12 via the N-MOS 337b. The low level potential VL is input to the input. Further, a pulsed signal continues to be input to the common electrode 22.
Thus, the pixel 302B is displayed in white while the display of the pixel 302A is maintained.

  Thereafter, when the process proceeds to the power-off period ST150, at least the first and second control lines 11 and 12 are electrically disconnected, and the image written in the normal image display period ST100 is held. Note that in the power-off period ST150, the scanning lines 4 and the data lines 5 may be in a high impedance state.

  Also, the first and second power supply lines 13 and 14 can be set in a high impedance state, and the SRAM 25 can be set in a power off state. However, when an operation based on the image signal input to the SRAM 25 is performed after the normal image display period ST100 (for example, an operation for inverting the display or a display refreshing operation), only the SRAM 25 is in a power-on state. This eliminates the need to transfer the image signal again when performing other operations. At this time, if the power supply voltage (Vdd) of the SRAM 25 is set to the minimum power supply voltage that can hold the stored potential, the power consumption accompanying the operation of the SRAM 25 can be suppressed.

As described above, the electrophoretic display device according to the first configuration example can display an image in the same sequence as the electrophoretic display device according to the first embodiment.
As shown in FIGS. 20 and 21, the second control line 12 is in a high impedance state in the black image display period ST101, and the first control line 11 is in a high impedance state in the white image display period ST102. Therefore, the leakage path due to the lateral electric field between the adjacent pixel electrodes 21a and 21b is always cut off, and no leakage current is generated due to the potential difference between the adjacent pixels.

<Anti-image display>
Next, the reverse image display will be described with reference to Table 3 and FIGS.
As shown in Table 3, the reverse image display can be executed by the same operation as the normal image display except that the potentials (VH, VL) of the first and second control lines 11 and 12 are exchanged with each other.

FIG. 22 is a diagram illustrating a timing chart in the inverted image display. FIG. 23 and FIG. 24 are diagrams illustrating a state of two adjacent pixels in the inverted image display, and correspond to FIG. 20 and FIG. 21 in the normal image display.
FIG. 22 shows a normal image display period ST100, a power-off period ST150, an anti-image display period ST110, and a power-off period ST151. That is, FIG. 22 shows a sequence in which the normal image display is performed and then the display is reversed.

The non-image display period ST110 includes a white inversion display period ST111 in which black display pixels are inverted to white display, and a black inversion display period ST112 in which white display pixels are inverted to black display.
FIG. 23 shows the state of the pixels 302A and 302B in the white color inversion display period ST111. FIG. 24 shows the state of the pixels 302A and 302B in the black color inversion display period ST112.

  In the power-off period ST150 after the normal image display period ST100, the pixel 302A is displayed in black and the pixel 302B is displayed in white. Then, when shifting from the power-off period ST150 to the white color inversion display period ST111, the low-level potential VL is supplied to the first control line 11, while the second control line 12 is in a high impedance state where it is electrically disconnected. Is done.

  In the pixel 302A that holds a high-level (H) image signal, the P-MOS 336a is turned on, the first control line 11 and the pixel electrode 21a are electrically connected, and the pixel electrode 21a has a low level. A potential (VL + Vthp) is input.

Here, not the potential VL of the first control line 11 but the potential (VL + Vthp) is input to the pixel electrode 21a for the following reason.
In the P-MOS 336a, the potential difference Vgs between the potential of the source terminal (the potential of the first control line 11) and the potential of the gate terminal (the potential of the output terminal N2) is larger than the threshold voltage Vthp of the P-MOS 336a. In this case, the P-MOS 336a is turned on. However, when the potential difference Vgs becomes smaller than the threshold voltage Vthp, the P-MOS 336a is turned off, so that the drain potential is reduced only to the lowest potential (VL + Vthp) at which the P-MOS 336a can be kept on. This potential is input as the low level potential of the pixel electrode 21a.

Then, a pulse-like signal that repeats a period of a high level potential (VH−Vthn) and a period of a low level potential (VL + Vthp) at a predetermined cycle is input to the common electrode 22. Thereby, the pixel 302A that has been displayed black in the normal image display period ST100 is inverted to white display.
On the other hand, in the pixel 302B holding a low-level (L) image signal, the N-MOS 337b is turned on and the second control line 12 and the pixel electrode 21b are electrically connected, and the pixel electrode 21b is A high impedance state is established and white display is maintained.

  Next, when the period proceeds to the black color inversion display period ST112, as shown in FIGS. 22 and 24, the first control line 11 is brought into a high impedance state where it is electrically disconnected, and the second control line 12 has a high impedance state. A level potential VH is supplied.

In the pixel 302A holding a high-level (H) image signal, the first control line 11 and the pixel electrode 21a are electrically connected, and the pixel electrode 21a enters a high impedance state.
On the other hand, in the pixel 302B holding a low-level (L) image signal, the second control line 12 and the pixel electrode 21b are electrically connected, and a high-level potential (VH−Vthn) is applied to the pixel electrode 21b. Entered.

Here, the reason that the potential (VH−Vthn) is input to the pixel electrode 21b instead of the potential VH of the second control line 12 is as follows.
If the potential difference Vgs between the potential of the gate terminal of the N-MOS 337b (potential of the output terminal N2) and the potential of the source terminal (potential of the second control line 12) is larger than the threshold voltage Vthn of the N-MOS 337b, N -The MOS 337b is turned on. However, since the N-MOS 337b is turned off when the potential difference Vgs becomes smaller than the threshold voltage Vthn, the drain potential only rises to the highest potential (VH−Vthp) at which the N-MOS 337b can be kept on. This potential is input as the high level potential of the pixel electrode 21b.

  The common electrode 22 continues to receive a pulse-like signal that repeats a high level (VH−Vthn) period and a low level (VL + Vthp) period in a predetermined cycle. As a result, the pixels 302B that were displayed in white in the normal image display period ST100 are inverted to black as shown in FIG.

  Thereafter, when the power-off period ST151 is entered, all the wirings connected to the pixels 302A and 302B are electrically disconnected, and the inverted image written in the anti-image display period ST110 is held.

  Note that in the anti-image display period ST110, the high-level potential and the low-level potential input to the common electrode 22 are the potential (VL) of the first control line 11 and the potential (VH) of the second control line 11, respectively. The difference is that the potential Va of the pixel electrode 21a of the pixel 302A in the white color inversion display period ST111 is (VL + Vthp), and the potential Vb of the pixel electrode 21b of the pixel 302B in the black color inversion display period ST112 is (VH−Vthn). It is to become.

More specifically, when the low level potential of a pulse input to the common electrode 22 is VL, the low level potential of the common electrode 22 is low in the pixel electrode 21 in the pixel 302A in which the pixel electrode 21b is at the low level potential (VL + Vthp). It becomes lower than the level potential. Then, an electric field similar to that in the black display operation is formed in the pixel 302A that originally performs the white display operation. As a result, the white particles move in the direction away from the common electrode 22 in the pixel during the white display operation, and the display quality is deteriorated.
When the high level potential of a pulse input to the common electrode 22 is VH, the high level potential of the common electrode 22 is the high level of the pixel electrode 21 in the pixel 302A in which the pixel electrode 21a is the high level potential (VH−Vthn). It becomes higher than the potential. Then, the black particles move in the direction away from the common electrode 22 in the pixel 302B during the black display operation, and the display quality is deteriorated.
For this reason, in the present invention, the potential of the pulse applied to the common electrode 22 is adjusted according to the low level potential (VL + Vthp) of the pixel electrode 21a and the high level potential (VH−Vthn) of the pixel electrode 21b. -ing

  If the potential difference Vgs can be sufficiently secured in the P-MOS 336a and the N-MOS 337b, the above-described fluctuation of the drain potential corresponding to the threshold voltage does not occur. However, when the drive voltage of each circuit is configured with only a positive power supply in order to ensure the potential difference applied to the electrophoretic element 23, the low level potential Vss of the SRAM 25 and the low level potential VL of the first control line 11 are the same. The high level potential Vdd of the SRAM 25 and the high level potential VH of the second control line 12 become the same potential (for example, 15 V). Then, since the drain potential fluctuation as described above occurs, in this embodiment, the potential of the common electrode 22 is adjusted so that the fluctuation of the drain potential does not cause a problem in display.

  As described above, in the electrophoretic display device according to the first configuration example, display can be easily performed by reversing the potentials of the first control line 11 and the second control line 12 from those in the normal image display. The image can be reversed. That is, it is not necessary to transfer the image data again to invert the display image, and various displays can be performed while reducing power consumption.

  As shown in FIGS. 23 and 24, the second control line 12 is in a high impedance state in the white color inversion display period ST111, and the first control line 11 is in a high impedance state in the black color inversion display period ST112. Therefore, the leakage path due to the horizontal electric field between the adjacent pixel electrodes 21a and 21b is always cut off, and no leakage current is generated due to the potential difference between the adjacent pixels.

<All white display>
Next, all white display will be described with reference to Table 3, FIG. 25, and FIG.
As shown in Table 3, all white display is performed by supplying a low level potential VL to both the first control line 11 and the second control line 12.

FIG. 25 is a diagram showing a timing chart in the all-white display, and corresponds to FIG. 22 in the previous anti-image display. FIG. 25 shows a normal image display period ST100, a power-off period ST150, an all-white display period ST120, and a power-off period ST151. That is, FIG. 25 shows a sequence in which the display image is erased by the all white display after the normal image display is performed.
FIG. 26 shows the state of the pixels 302A and 302B in the all white display period ST120.

  In the power-off period ST150 after the normal image display period ST100, the pixel 302A is displayed in black and the pixel 302B is displayed in white. Then, when the power-off period ST150 shifts to the all white display period ST120, the low-level potential VL is supplied to both the first control line 11 and the second control line 12.

In the pixel 302A that holds a high-level (H) image signal, the P-MOS 336a is turned on, the first control line 11 and the pixel electrode 21a are electrically connected, and the pixel electrode 21a has a low level. A potential (VL + Vthp) is input.
On the other hand, in the pixel 302B that holds a low-level (L) image signal, the N-MOS 337b is turned on, and the second control line 12 and the pixel electrode 21b are electrically connected to each other. A low level potential VL is input.
Then, a pulse-like signal that repeats the period of the high level potential VH and the period of the low level potential (VL + Vthp) at a predetermined cycle is input to the common electrode 22.
As a result, during the period in which the common electrode 22 is at the high level, the electrophoretic element 23 is driven based on the potential difference between the pixel electrode 21 and the common electrode 22, and the pixel 302A that has been displayed black in the normal image display period ST100 displays white. Is done. In addition, since the display of the pixel 302B originally displaying white is not changed, all the pixels are displayed in white.

In the all white display, since the low level potential of the pixel electrode 21a is (VL + Vthp), the low level potential of the pulse input to the common electrode 22 is adjusted to (VL + Vthp). Thereby, it is possible to prevent the display from being defective.
In the all white display, as shown in FIG. 26, a low level potential is simultaneously input to both the first and second control lines 11 and 12, and a slight potential difference (Vthp) is also generated between adjacent pixel electrodes. However, since the first control line 11 and the second control line 12 which are both ends of the leak path have the same potential, no leak current is generated.

<All black display>
Next, all black display will be described with reference to Table 3, FIG. 27, and FIG.
As shown in Table 3, all black display is performed by supplying a high level potential VH to both the first control line 11 and the second control line 12.

FIG. 27 is a diagram showing a timing chart in the all-black display, and corresponds to FIG. 22 in the previous anti-image display. FIG. 27 shows a normal image display period ST100, a power supply off period ST150, an all black display period ST130, and a power supply off period ST151. That is, FIG. 27 shows a sequence in which a display image is erased by an all black display after performing a normal image display.
FIG. 28 shows the state of the pixels 302A and 302B in the all black display period ST130.

  In the power-off period ST150 after the normal image display period ST100, the pixel 302A is displayed in black and the pixel 302B is displayed in white. Then, when the power-off period ST150 shifts to the all black display period ST130, the high-level potential VH is supplied to both the first control line 11 and the second control line 12.

In the pixel 302A that holds a high-level (H) image signal, the P-MOS 336a is turned on, the first control line 11 and the pixel electrode 21a are electrically connected, and the pixel electrode 21a has a high level. The potential VH is input.
On the other hand, in the pixel 302B that holds a low level (L) image signal, the N-MOS 337b is turned on, and the second control line 12 and the pixel electrode 21b are electrically connected to each other. A high level potential VH-Vthn is input.
Then, a pulse-like signal that repeats the period of the high level potential (VH−Vthn) and the period of the low level potential VL in a predetermined cycle is input to the common electrode 22.
As a result, during the period in which the common electrode 22 is at the low level, the electrophoretic element 23 is driven based on the potential difference between the pixel electrode 21 and the common electrode 22, and the pixel 302B that has been displayed in white in the normal image display period ST100 is displayed in black. Is done. Further, since the display of the pixel 302A that originally displayed black is not changed, all the pixels display black.

In the all black display, since the high level potential of the pixel electrode 21b is (VH−Vthn), the high level potential of the pulse input to the common electrode 22 is adjusted to (VH−Vthn). Thereby, it is possible to prevent the display from being defective.
In the all black display, as shown in FIG. 28, the high level potential VH is simultaneously input to both the first and second control lines 11 and 12, and a slight potential difference is also generated between adjacent pixel electrodes. Although (Vthn) occurs, the first control line 11 and the second control line 12 that are both ends of the leak path have the same potential, and therefore no leak current is generated.

  As described above in detail, the electrophoretic display device according to the first configuration example includes the switch circuit 335 including only two transistors, and thus the first embodiment shown in FIG. Compared with the pixel 2, the configuration of the pixel circuit can be simplified, and the area can be reduced by reducing the number of transistors. Therefore, an occupation area per pixel can be reduced, and an electrophoretic display device that can easily cope with high definition of pixels can be realized. Further, by reducing the number of transistors, the parasitic capacitance during energization can be reduced, so that power consumption can be reduced.

  In addition, display defects that may be caused by the reduction in the number of transistors can be effectively prevented. In other words, the potential of the pulse input to the common electrode 22 is adjusted according to the change in the potential input to the pixel electrode 21, and this causes a reverse electric field to act on the electrophoretic element, thereby reducing display quality. Can be prevented.

In this embodiment, the high level potential of the common electrode 22 is (VH−Vthn) and the low level potential is (VL + Vthp). However, the high level potential of the common electrode 22 is a potential lower than (VH−Vthn). The low level potential may be higher than (VL + Vthp). This is because when the potential difference Vgs between the gate and source of the P-MOS 336 and the N-MOS 337 approaches Vthp and Vthn, it takes time to saturate the drain potential. Therefore, when the pulse input to the common electrode 22 is started, It is because it is assumed that it will be in the state which is not saturated.
In this case, the high level potential of the pixel electrode 21 is lower than the above potential (VH−Vthn), and the low level potential is higher than the above potential (VL + Vthp). Therefore, in order to more surely prevent display defects, the high level potential of the common electrode 22 is set slightly lower than (VH−Vthn) and the low level potential is set slightly higher than (VL + Vthp). preferable.

[Second configuration example]
Next, a second configuration example of the second embodiment will be described.
FIG. 29 is a circuit configuration diagram of the pixel 402 provided in the electrophoretic display device according to the second configuration example. 29 replaces the switch circuit 35 of the pixel 2 shown in FIG. 2 with a switch circuit 435 including an N-MOS (first transistor) 436 and an N-MOS (second transistor) 437. It is the structure provided with. In the following, the same components as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the pixel 402, the switch circuit 435 is connected between the SRAM 25 and the pixel electrode 21. The gate terminal of the N-MOS 436 is connected to the second output terminal N3 of the SRAM 25, and the gate terminal of the N-MOS 437 is connected to the first output terminal N2 of the SRAM 25. The source terminal of the N-MOS 436 is connected to the first control line 11, and the drain terminal is connected to the pixel electrode 21. The source terminal of the N-MOS 437 is connected to the second control line 12, and the drain terminal is connected to the pixel electrode 21.

In the pixel 402 configured as described above, when a high level (H) is input as an image signal, the N-MOS 436 is turned on by the high level potential (Vdd) output from the second output terminal N3 of the SRAM 25, and the first The control line 11 and the pixel electrode 21 are connected.
On the other hand, when a low level (L) is input as an image signal, the N-MOS 437 is turned on by a high level potential (Vdd) output from the first output terminal N2 of the SRAM 25, and the second control line 12 and The pixel electrode 21 is connected.

  Therefore, similarly to the pixel 2 according to the previous embodiment, the pixel 402 according to the present embodiment operates the switch circuit 435 based on the potential of the image signal input to the SRAM 25, and the first control line 11 or the second control line 11. By connecting the two control lines 12 and the pixel electrode 21, the potentials S <b> 1 and S <b> 2 of the first or second control lines 11 and 12 are input to the pixel electrode 21.

[Driving method]
Next, a driving method of the electrophoretic display device according to the second configuration example will be described with reference to Table 4 and FIGS. 30 to 39. Also in this embodiment, a plurality of drive modes (normal image display, reverse image display, all white display, all black display) will be described, but portions common to the first configuration example will be omitted as appropriate.

  Table 4 is a table comparing and comparing the potentials input to the pixels 402 in the operations of normal image display, reverse image display, all white display, and all black display, and corresponds to Table 3 in the first configuration example. It is a table. However, “Vthn” shown in Table 4 is a threshold voltage of the N-MOSs 436 and 437.

<Normal image display>
FIG. 30 is a diagram illustrating a timing chart in normal image display, and corresponds to FIG. 19 according to the first configuration example. As shown in FIG. 30, the normal image display sequence includes a normal image display period ST200 and a power-off period ST250. In the normal image display period ST200, a black image display period ST201 and a white image display period ST202 are sequentially executed.

31 and 32 are diagrams corresponding to FIGS. 20 and 21 according to the first configuration example, respectively. That is, FIG. 31 is a diagram illustrating a state of the pixels 402A and 402B in the black image display period ST201, and FIG. 32 is a diagram illustrating a state of the pixels 402A and 402B in the white image display period ST202.
In the following description, it is assumed that a high level (L) image signal is held in the SRAM 25a of the pixel 402A and a low level (L) image signal is held in the SRAM 25b of the pixel 402B.

In the black image display period ST201, the high level potential VH is supplied to the first control line 11, and the second control line 12 is set to a high impedance state.
In the pixel 402A that holds a high-level (H) image signal, the N-MOS 436a is turned on, and the first control line 11 and the pixel electrode 21a are electrically connected. As a result, the high level potential VH is input to the pixel electrode 21a.
On the other hand, in the pixel 402B that holds a low level (L) image signal, the N-MOS 437b is turned on. However, since the second control line 12 is in a high impedance state, the pixel electrode 21b remains in a high impedance state.

The common electrode 22 receives a pulse-like signal that repeats a period of a high level potential (VH−Vthn) and a period of a low level potential VL in a predetermined cycle.
As described above, based on the potential difference between the common electrode 22 and the pixel electrodes 21a and 21b, the pixel 402A is displayed in black, and the display of the pixel 402B is not changed.

Next, in the white image display period ST <b> 202, the first control line 11 is in a high impedance state where the first control line 11 is electrically disconnected, and the low level potential VL is supplied to the second control line 12. As a result, the pixel electrode 21a connected to the first control line 11 via the N-MOS 436a is brought into a high impedance state, while the pixel electrode 21b connected to the second control line 12 via the N-MOS 437b. The low level potential VL is input to the input. Further, a pulsed signal continues to be input to the common electrode 22.
Thus, the pixel 402B is displayed in white while the display of the pixel 402A is maintained.

  Thereafter, when the power-off period ST250 is entered, all the wirings connected to the pixels 402A and 402B are electrically disconnected, and the image written in the normal image display period ST200 is held.

  In the black image display period ST201, the potential input to the pixel electrode 21a becomes (VH−Vthn) for the same reason as in the first configuration example. Since the high level potential of the pixel electrode 21a is lowered by Vthn, the high level potential of the pulse input to the common electrode 22 is set to (VH−Vthn), thereby preventing display defects.

As described above, the electrophoretic display device according to the second configuration example can display an image in the same sequence as the electrophoretic display device according to the first embodiment.
As shown in FIGS. 31 and 32, the second control line 12 is in a high impedance state in the black image display period ST201, and the first control line 11 is in a high impedance state in the white image display period ST202. Therefore, the leakage path due to the horizontal electric field between the adjacent pixel electrodes 21a and 21b is always cut off, and no leakage current is generated due to the potential difference between the adjacent pixels.

<Anti-image display>
FIG. 33 is a diagram showing a timing chart in the inverted image display. 34 is a diagram showing the state of the pixels 402A and 402B in the white color inversion display period ST211 shown in FIG. 33, and FIG. 35 is a diagram showing the state of the pixels 402A and 402B in the black color inversion display period ST212 shown in FIG. is there.
FIG. 33 shows a normal image display period ST200, a power-off period ST250, an anti-image display period ST210, and a power-off period ST251. The non-image display period ST200 includes a white color inversion display period ST211 and a black color inversion display period ST212.

The operation of the anti-image display in the electrophoretic display device according to the second configuration example is the same as that of the electrophoretic display device according to the first configuration example.
After the normal image display period ST200 described above, the pixel 402A is displayed in black and the pixel 402B is displayed in white in a state where the power-off period ST250 is entered.

When shifting from the power-off period ST250 to the white color inversion display period ST211, the low-level potential VL is supplied to the first control line 11, and the second control line 12 is held in a high impedance state.
In the pixel 402A, the low level potential VL is input from the first control line 11 to the pixel electrode 21a via the N-MOS 436a. On the other hand, in the pixel 402B, the pixel electrode 21b remains in a high impedance state. In addition, a pulse-like signal that repeats a high level potential (VH−Vthn) and a low level potential VL in a predetermined cycle is input to the common electrode 22.
As a result, the pixel 402A that has been displayed in black is inverted to white display.

Next, in the black inversion display period ST212, the first control line 11 is set to a high impedance state, and the high level potential VH is supplied to the second control line 12.
In the pixel 402A, the pixel electrode 21a connected to the first control line 11 via the N-MOS 436a is in a high impedance state. On the other hand, in the pixel 402B, the high level potential VH is input to the pixel electrode 21b connected to the second control line 12 via the N-MOS 437b.
Since the pulse-like signal is input to the common electrode 22, the pixel 402B displayed in white is inverted to black display. At this time, the display of the pixel 402A does not change.

By the above white inversion display period ST211 and black inversion display period ST212, a black and white inversion image of the image displayed in the normal image display period ST200 is displayed.
In the electrophoretic display device of the second configuration example, the potential input to the pixel electrode 21 differs from the potentials of the first and second control lines 11 and 12 due to the characteristics of the N-MOSs 436 and 437. Therefore, the high level potential of the pulse input to the common electrode 22 is adjusted to (VH−Vthn) in accordance with the high level potential of the pixel electrode 21 so as not to cause a display defect.

  As shown in FIGS. 34 and 35, the second control line 12 is set to a high impedance state during the white color inversion display period ST211, and the first control line 11 is set to a high impedance state during the black color inversion display period ST212. Therefore, at least one of the control lines is electrically disconnected during the display operation. Accordingly, since the leak path is always cut off, no leak current is generated between adjacent pixels.

<All white display>
FIG. 36 is a diagram showing a timing chart in the all white display. FIG. 37 is a diagram showing a state of the pixels 402A and 402B in the all white display period ST220 shown in FIG.
FIG. 36 shows a normal image display period ST200, a power off period ST250, an all white display period ST220, and a power off period ST251. That is, FIG. 36 shows a sequence in which the display image is erased by the all white display after the normal image display.

  In the power-off period ST250 after the normal image display period ST200, the pixel 402A is displayed in black and the pixel 402B is displayed in white. Then, when the power-off period ST250 shifts to the all white display period ST220, the low level potential VL is supplied to both the first control line 11 and the second control line 12.

In the pixel 402A, the first control line 11 and the pixel electrode 21a are electrically connected, and the low-level potential VL is input to the pixel electrode 21a. On the other hand, in the pixel 402B, the second control line 12 and the pixel electrode 21b are electrically connected, and the low-level potential VL is input to the pixel electrode 21b.
Then, a pulse-like signal that repeats the period of the high level potential VH and the period of the low level potential VL in a predetermined cycle is input to the common electrode 22.

As a result, during the period in which the common electrode 22 is at the high level potential VH, the electrophoretic element 23 is driven based on the potential difference between the pixel electrode 21 and the common electrode 22, and the pixel 402A that has been displayed black in the normal image display period ST200 Displayed in white. Further, since the display of the pixel 402B that originally displayed white is not changed, all the pixels display white.
In the all white display in the second configuration example, as shown in FIG. 37, since the pixel electrodes 21a and 21b are at the same potential, no leak current occurs between the pixel electrodes.

<All black display>
FIG. 38 is a diagram showing a timing chart in the all black display. FIG. 39 is a diagram showing a state of the pixels 402A and 402B in the all black display period ST230 shown in FIG.
FIG. 38 shows a normal image display period ST200, a power off period ST250, an all black display period ST230, and a power off period ST251. That is, FIG. 38 shows a sequence in which a display image is erased by an all black display after performing a normal image display.

  In the power-off period ST250 after the normal image display period ST200, the pixel 402A is displayed in black and the pixel 402B is displayed in white. Then, when the power-off period ST250 shifts to the all black display period ST230, the high level potential VH is supplied to both the first control line 11 and the second control line 12.

In the pixel 402A, the first control line 11 and the pixel electrode 21a are electrically connected, and a high level potential (VH−Vthn) is input to the pixel electrode 21a. On the other hand, in the pixel 402B, the second control line 12 and the pixel electrode 21b are electrically connected, and a high level potential (VH−Vthn) is input to the pixel electrode 21b.
Then, a pulse-like signal that repeats the period of the high level potential (VH−Vthn) and the period of the low level potential VL in a predetermined cycle is input to the common electrode 22.

  As a result, during the period in which the common electrode 22 is at the low level potential VL, the electrophoretic element 23 is driven based on the potential difference between the pixel electrode 21 and the common electrode 22, and the pixel 402B that has been displayed in white in the normal image display period ST200 Displayed in black. Further, since the display of the pixel 402A that originally displayed black is not changed, all the pixels display black.

  In the all black display in the second configuration example, the high level potential input to the pixel electrodes 21a and 21b is lower than the high level potential VH of the first and second control lines 11 and 12 by the threshold potential Vthn. For this reason, the high level potential of the common electrode 22 is set to (VH−Vthn) so as not to cause a problem in display. Further, in the all black display, as shown in FIG. 39, since the pixel electrodes 21a and 21b are at the same potential, no leakage current occurs between the pixel electrodes.

As described above in detail, in the electrophoretic display device according to the second configuration example, since the switch circuit 435 of the pixel 402 is configured with a small number of transistors, the area of the pixel 402 can be reduced. Therefore, the area occupied per pixel can be reduced, and an electrophoretic display device that can easily cope with higher definition of pixels can be realized. Further, by reducing the number of transistors by two as compared with the pixel 2 shown in FIG. 2, the parasitic capacitance during energization can be reduced, so that power consumption can be reduced.
Further, by adjusting the potential of the pulse input to the common electrode 22 as the potential input to the pixel electrode 21 changes depending on the display mode, the changing potential of the pixel electrode 21 can be used effectively. By performing image display, it is possible to prevent a display defect caused by reducing the number of transistors.

[Third configuration example]
Next, a third configuration example of the second embodiment will be described.
FIG. 40 is a circuit configuration diagram of the pixel 502 provided in the electrophoretic display device according to the third configuration example. A pixel 502 illustrated in FIG. 40 includes a switch circuit 535 including a P-MOS (first transistor) 536 and a P-MOS (second transistor) 537 instead of the switch circuit 35 of the pixel 2 illustrated in FIG. It is the structure provided with. In the following, the same components as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the pixel 502, the switch circuit 535 is connected between the SRAM 25 and the pixel electrode 21. The gate terminal of the P-MOS 536 is connected to the first output terminal N2 of the SRAM 25, and the gate terminal of the P-MOS 537 is connected to the second output terminal N3 of the SRAM 25. The source terminal of the P-MOS 536 is connected to the first control line 11, and the drain terminal is connected to the pixel electrode 21. The source terminal of the P-MOS 537 is connected to the second control line 12, and the drain terminal is connected to the pixel electrode 21.

In the pixel 502 configured as described above, when a high level (H) is input as an image signal, the P-MOS 536 is turned on by a low level potential (Vss) output from the first output terminal N2 of the SRAM 25, and the first The control line 11 and the pixel electrode 21 are connected.
On the other hand, when the low level (L) is input as the image signal, the P-MOS 537 is turned on by the low level potential (Vss) output from the second output terminal N3 of the SRAM 25, and the second control line 12 The pixel electrode 21 is connected.

  Therefore, similarly to the pixel 2 according to the previous embodiment, the pixel 502 according to the present embodiment operates the switch circuit 535 based on the potential of the image signal input to the SRAM 25, and the first control line 11 or the second control line 11. By connecting the two control lines 12 and the pixel electrode 21, the potentials S <b> 1 and S <b> 2 of the first or second control lines 11 and 12 are input to the pixel electrode 21.

[Driving method]
Next, a driving method of the electrophoretic display device according to the third configuration example will be described with reference to Table 5 and FIGS. 40 to 50. In the present embodiment, a plurality of driving modes (normal image display, counter image display, all white display, all black display) will be described. However, portions common to the first configuration example and the second configuration example are appropriately selected. Omitted.

  Table 5 is a table comparing and comparing the potentials input to the pixels 502 in each of the operations of normal image display, counter image display, all white display, and all black display, and corresponds to Table 3 in the first configuration example. It is a table. However, “Vthp” shown in Table 5 is a threshold voltage of the P-MOSs 536 and 537.

<Normal image display>
FIG. 41 is a diagram illustrating a timing chart in normal image display, and corresponds to FIG. 19 according to the first configuration example. As shown in FIG. 41, the sequence of normal image display includes a normal image display period ST300 and a power-off period ST350. In the normal image display period ST300, a black image display period ST301 and a white image display period ST302 are sequentially executed.

42 and 43 are diagrams corresponding to FIGS. 20 and 21 according to the first configuration example, respectively. That is, FIG. 42 is a diagram illustrating a state of the pixels 502A and 502B in the black image display period ST301, and FIG. 43 is a diagram illustrating a state of the pixels 502A and 502B in the white image display period ST302.
In the following description, it is assumed that a high level (L) image signal is held in the SRAM 25a of the pixel 502A and a low level (L) image signal is held in the SRAM 25b of the pixel 502B.

In the black image display period ST301, the high level potential VH is supplied to the first control line 11, and the second control line 12 is set to a high impedance state.
In the pixel 502A holding a high-level (H) image signal, the P-MOS 536a is turned on, and the first control line 11 and the pixel electrode 21a are electrically connected. As a result, the high level potential VH is input to the pixel electrode 21a.
On the other hand, in the pixel 502B that holds the low-level (L) image signal, the P-MOS 537b is turned on. However, since the second control line 12 is in a high impedance state, the pixel electrode 21b is also in a high impedance state.

The common electrode 22 receives a pulse-like signal that repeats the period of the high level potential VH and the period of the low level potential (VL + Vthp) at a predetermined cycle.
As described above, based on the potential difference between the common electrode 22 and the pixel electrodes 21a and 21b, the pixel 502A is displayed in black, and the display of the pixel 502B is not changed.

Next, in the white image display period ST <b> 302, the first control line 11 is in a high impedance state where the first control line 11 is electrically disconnected, and the low-level potential VL is supplied to the second control line 12. As a result, the pixel electrode 21a connected to the first control line 11 via the P-MOS 536a is brought into a high impedance state, while the pixel electrode 21b connected to the second control line 12 via the P-MOS 537b. The low level potential (VL + Vthp) is input to the input. Further, a pulsed signal continues to be input to the common electrode 22.
Thus, the pixel 402B is displayed in white while the display of the pixel 402A is maintained.

  Thereafter, when the process proceeds to the power-off period ST350, all the wirings connected to the pixels 502A and 502B are electrically disconnected, and a high-impedance state is maintained, and the image written in the normal image display period ST300 is held.

  Note that the potential input to the pixel electrode 21b in the black image display period ST301 becomes (VL + Vthp) for the same reason as in the first configuration example. Since the low level potential of the pixel electrode 21b is increased by Vthp, the low level potential of the pulse input to the common electrode 22 is set to (VL + Vthp), thereby preventing display problems.

As described above, the electrophoretic display device according to the third configuration example can display an image in the same sequence as the electrophoretic display device according to the first embodiment.
As shown in FIGS. 42 and 43, the second control line 12 is in a high impedance state in the black image display period ST301, and the first control line 11 is in a high impedance state in the white image display period ST302. Therefore, the leakage path due to the lateral electric field between the adjacent pixel electrodes 21a and 21b is always cut off, and no leakage current is generated due to the potential difference between the adjacent pixels.

<Anti-image display>
FIG. 44 is a diagram showing a timing chart in the inverted image display. 45 is a diagram showing the state of the pixels 502A and 502B in the white color inversion display period ST311 shown in FIG. 44, and FIG. 46 is a diagram showing the state of the pixels 502A and 502B in the black color inversion display period ST312 shown in FIG. is there.
FIG. 44 shows a normal image display period ST300, a power-off period ST350, an anti-image display period ST310, and a power-off period ST351. The non-image display period ST300 includes a white color inversion display period ST311 and a black color inversion display period ST312.

The operation of the anti-image display in the electrophoretic display device according to the third configuration example is the same as that of the electrophoretic display device according to the first configuration example.
After the normal image display period ST300 described above, the pixel 502A is displayed in black and the pixel 502B is displayed in white in a state where the power-off period ST350 is entered.

When the power-off period ST350 is shifted to the white color inversion display period ST311, the low level potential VL is supplied to the first control line 11, and the second control line 12 is held in the high impedance state.
In the pixel 502A, the low level potential (VL + Vthp) is input from the first control line 11 to the pixel electrode 21a via the P-MOS 536a. On the other hand, in the pixel 502B, the pixel electrode 21b remains in a high impedance state. In addition, a pulse-like signal that repeats a high level potential VH and a low level potential (VL + Vthp) at a predetermined cycle is input to the common electrode 22.
As a result, the pixel 502A that has been displayed in black is inverted to white display.

Next, in the black inversion display period ST312, the first control line 11 is set to a high impedance state, and the high level potential VH is supplied to the second control line 12.
In the pixel 502A, the pixel electrode 21a connected to the first control line 11 via the P-MOS 536a is in a high impedance state. On the other hand, in the pixel 502B, the high level potential VH is input to the pixel electrode 21b connected to the second control line 12 through the P-MOS 537b.
Since the pulse-like signal is input to the common electrode 22, the pixel 502B displayed in white is inverted to black display. At this time, the display of the pixel 502A does not change.

Through the above white inversion display period ST311 and black inversion display period ST312, a black and white inversion image of the image displayed in the normal image display period ST300 is displayed.
In the electrophoretic display device of the third configuration example, the potential input to the pixel electrode 21 differs from the potentials of the first and second control lines 11 and 12 due to the characteristics of the P-MOSs 536 and 537. Therefore, the potential of the pulse input to the common electrode 22 is adjusted in accordance with the potential of the pixel electrode 21 so as not to cause a problem in display.

  As shown in FIGS. 45 and 46, the second control line 12 is in a high impedance state in the white color inversion display period ST311 and the first control line 11 is in a high impedance state in the black color inversion display period ST311. Therefore, at least one of the control lines is electrically disconnected during the display operation. Therefore, since the leak path is always cut off, no leak current occurs between adjacent pixels.

<All white display>
FIG. 47 is a diagram showing a timing chart in the all white display. FIG. 48 is a diagram showing a state of the pixels 502A and 502B in the all white display period ST320 shown in FIG.
FIG. 47 shows a normal image display period ST300, a power off period ST350, an all white display period ST320, and a power off period ST351. That is, FIG. 47 shows a sequence in which the display image is erased by the all white display after the normal image display is performed.

  In the power-off period ST350 after the normal image display period ST300, the pixel 502A is displayed in black and the pixel 502B is displayed in white. Then, when the power-off period ST350 is shifted to the all white display period ST320, the low level potential VL is supplied to both the first control line 11 and the second control line 12.

In the pixel 502A, the first control line 11 and the pixel electrode 21a are electrically connected, and a low level potential (VL + Vthp) is input to the pixel electrode 21a. On the other hand, in the pixel 502B, the second control line 12 and the pixel electrode 21b are electrically connected, and a low level potential (VL + Vthp) is input to the pixel electrode 21b.
Then, a pulse-like signal that repeats the period of the high level potential VH and the period of the low level potential (VL + Vthp) at a predetermined cycle is input to the common electrode 22.

  As a result, during the period in which the common electrode 22 is at the high level potential VH, the electrophoretic element 23 is driven based on the potential difference between the pixel electrode 21 and the common electrode 22, and the pixel 502A that has been displayed black in the normal image display period ST300 is displayed. Displayed in white. In addition, since the display of the pixel 502B originally displaying white is not changed, all the pixels are displayed in white.

  In the all white display in the third configuration example, the low level potential input to the pixel electrodes 21a and 21b is higher than the low level potential VL of the first and second control lines 11 and 12 by the threshold potential Vthp. For this reason, the low level potential of the common electrode 22 is set to (VL + Vthp) so as not to cause a problem in display. Further, in the all white display in the third configuration example, as shown in FIG. 48, since the pixel electrodes 21a and 21b have the same potential, no leakage current occurs between the pixel electrodes.

<All black display>
FIG. 49 is a diagram showing a timing chart in the all black display. FIG. 50 is a diagram showing a state of the pixels 502A and 502B in the all black display period ST330 shown in FIG.
FIG. 49 shows a normal image display period ST300, a power off period ST350, an all black display period ST330, and a power off period ST351. That is, FIG. 49 shows a sequence in which a display image is erased by an all black display after performing a normal image display.

  In the power-off period ST350 after the normal image display period ST300, the pixel 502A is displayed in black and the pixel 502B is displayed in white. Then, when the power-off period ST350 shifts to the all black display period ST330, the high level potential VH is supplied to both the first control line 11 and the second control line 12.

In the pixel 502A, the first control line 11 and the pixel electrode 21a are electrically connected, and the high-level potential VH is input to the pixel electrode 21a. On the other hand, in the pixel 502B, the second control line 12 and the pixel electrode 21b are electrically connected, and the high-level potential VH is input to the pixel electrode 21b.
Then, a pulse-like signal that repeats the period of the high level potential VH and the period of the low level potential VL in a predetermined cycle is input to the common electrode 22.

As a result, during the period in which the common electrode 22 is at the low level potential VL, the electrophoretic element 23 is driven based on the potential difference between the pixel electrode 21 and the common electrode 22, and the pixel 502B that has been displayed in white in the normal image display period ST200 Displayed in black. Further, since the display of the pixel 502A that originally displayed black is not changed, all the pixels display black.
In the all black display of the third configuration example, as shown in FIG. 50, the pixel electrodes 21a and 21b are at the same potential, and therefore no leakage current occurs between the pixel electrodes.

  As described above in detail, the electrophoretic display device according to the third configuration example includes the switch circuit 535 including only two transistors, and thus the first embodiment shown in FIG. Compared with the pixel 2, the configuration of the pixel circuit can be simplified, and the area can be reduced by reducing the number of transistors. Therefore, an occupation area per pixel can be reduced, and an electrophoretic display device that can easily cope with high definition of pixels can be realized. Further, by reducing the number of transistors, the parasitic capacitance during energization can be reduced, so that power consumption can be reduced.

  In addition, display defects that may be caused by the reduction in the number of transistors can be effectively prevented. That is, the potential of the pulse input to the common electrode 22 is adjusted in accordance with the change in the potential input to the pixel electrode 21, and this causes a reverse electric field to act on the electrophoretic element, thereby reducing display quality. Can be prevented.

[Electronics]
FIG. 15 is an example of an electronic apparatus including the electrophoretic display device of the present invention. The electrophoretic display device described above is applied to various electronic devices, and an example of an electronic device including the above-described electrophoretic display device will be described below.
First, an example in which the electrophoretic display device of the present invention is applied to flexible electronic paper will be described. FIG. 15 is a perspective view showing the configuration of the electronic paper, and the electronic paper 1000 includes the electrophoretic display device 1 of the present invention as a display unit. The electronic paper 1000 has a configuration in which the electrophoretic display device 1 of the present invention is provided on the surface of a main body 1001 made of a sheet having the same texture and flexibility as conventional paper.
FIG. 16 is a perspective view illustrating a configuration of an electronic notebook 1100. The electronic notebook 1100 is formed by bundling a plurality of electronic papers 1000 illustrated in FIG. The cover 1101 includes display data input means (not shown) for inputting display data sent from an external device, for example. Thereby, according to the display data, the display contents can be changed or updated while the electronic paper 1000 is bundled.
In addition to the above-described examples, other examples include a liquid crystal television, a viewfinder type and a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a workstation, a videophone, and a POS terminal. And a device equipped with a touch panel. The electrophoretic display device according to the present invention can also be applied as a display unit of such an electronic device.
By providing the electrophoretic display device according to the present invention in the display portion, it is possible to provide an electronic device in which leakage current between adjacent pixels is suppressed, power consumption is reduced, and reliability is improved. Further, if the electrophoretic display device according to the second embodiment is provided, the size of one pixel can be reduced, so that an electronic apparatus including a higher-definition display unit is obtained.

1 is a configuration diagram of an electrophoretic display device according to a first embodiment. FIG. The figure which shows the circuit structure of a pixel similarly. Sectional drawing of a display part same as the above. The block diagram of a microcapsule. The figure explaining operation | movement of a microcapsule. The figure which shows the timing chart which concerns on a 1st drive method. The schematic diagram of 2 adjacent pixels in the 1st drive method. The schematic diagram of 2 adjacent pixels in the 1st drive method. The schematic diagram of 2 adjacent pixels in the 1st drive method. The conventional circuit block diagram. The figure which shows the timing chart which concerns on a 2nd drive method. The figure which shows the timing chart which concerns on a 3rd drive method. The figure which shows the timing chart which concerns on a 3rd drive method. The schematic diagram of 2 adjacent pixels in the 3rd drive method. 1 is a diagram showing an example of an electronic apparatus provided with an electrophoretic display device 1 according to the present invention. 1 is a diagram showing an example of an electronic apparatus provided with an electrophoretic display device 1 according to the present invention. The figure which shows the timing chart which concerns on a 4th drive method. The circuit block diagram of the pixel which concerns on the 1st structural example of 2nd Embodiment. The timing chart of the normal image display in the 1st example of composition. The figure which shows the state of the adjacent pixel in normal image display. The figure which shows the state of the adjacent pixel in normal image display. The timing chart which concerns on the reverse image display in the 1st structural example. The figure which shows the state of the adjacent pixel in a reverse image display. The figure which shows the state of the adjacent pixel in a reverse image display. The timing chart which concerns on the all-white display in a 1st structural example. The figure which shows the state of the adjacent pixel in all white display. The timing chart which concerns on the all black display of a 1st structural example. The figure which shows the state of the adjacent pixel in all black display. The circuit block diagram of the pixel which concerns on the 2nd structural example of 2nd Embodiment. The timing chart of the normal image display in the 2nd example of composition. The figure which shows the state of the adjacent pixel in normal image display. The figure which shows the state of the adjacent pixel in normal image display. The timing chart which concerns on the anti-image display in a 2nd structural example. The figure which shows the state of the adjacent pixel in a reverse image display. The figure which shows the state of the adjacent pixel in a reverse image display. The timing chart which concerns on the all white display in a 2nd structural example. The figure which shows the state of the adjacent pixel in all white display. The timing chart concerning the all black display of the 2nd example of composition. The figure which shows the state of the adjacent pixel in all black display. The circuit block diagram of the pixel which concerns on the 3rd structural example of 2nd Embodiment. The timing chart of the normal image display in the 3rd example of composition. The figure which shows the state of the adjacent pixel in normal image display. The figure which shows the state of the adjacent pixel in normal image display. The timing chart which concerns on the anti-image display in a 3rd structural example. The figure which shows the state of the adjacent pixel in a reverse image display. The figure which shows the state of the adjacent pixel in a reverse image display. The timing chart which concerns on the all white display in a 3rd structural example. The figure which shows the state of the adjacent pixel in all white display. The timing chart concerning the all black display of the 3rd example of composition. The figure which shows the state of the adjacent pixel in all black display.

Explanation of symbols

  2, 302, 402, 502 ... pixels, 3 ... display unit, 4 ... scanning line, 5 ... data line, 11 ... first control line, 12 ... second control line, 13 ... first power supply line, 14 2nd power line, 15 ... Common electrode power line, 21 ... Pixel electrode, 22 ... Common electrode, 23 ... Electrophoretic element, 24 ... Driving TFT (pixel switching element), 25 ... SRAM (memory circuit), 30 ... Adhesive layer, 35, 335, 435, 535 ... Switch circuit, 36 ... First transfer gate, 37 ... Second transfer gate, 40 ... Microcapsule, 336, 536, 537 ... P-MOS, 337, 436 , 437 ... N-MOS

Claims (20)

An electrophoretic display device comprising an electrophoretic element including electrophoretic particles sandwiched between a pair of substrates, and a display unit comprising a plurality of pixels,
The display unit includes a pixel electrode formed for each pixel, a counter electrode facing the plurality of pixel electrodes via the electrophoretic element, and first and second controls connected to each of the pixels. Lines are provided,
For each pixel, a pixel switching element, a memory circuit connected to the pixel switching element, and a connection state between the pixel electrode and the first or second control line are switched by an output signal of the memory circuit. An electrophoretic display device comprising a switch circuit for switching. A pixel driver connected to the pixel via a scanning line and a data line, and supplying image data to the memory circuit via the pixel switching element;
The first and second control lines and the counter electrode are connected to each other, the voltage applied to the pixel electrode is supplied to the switch circuit via the first and second control lines, and the counter electrode is supplied to the counter electrode. On the other hand, a potential control unit that supplies a rectangular wave of one cycle or more that repeats the first and second potentials corresponding to the potentials supplied to the first and second control lines;
The electrophoretic display device according to claim 1, comprising: The memory circuit has first and second output terminals for outputting different signals;
The switch circuit is connected between the first control line and the pixel electrode, and is switched by the output of the first output terminal; the second control line; 3. The electrophoretic display device according to claim 1, further comprising a second transfer gate that is connected to the pixel electrode and is switched by an output of the second output terminal. 4. A first transistor connected between the first control line and the pixel electrode; a second transistor connected between the second control line and the pixel electrode; Have
3. The electrophoretic display device according to claim 1, wherein one of the first and second transistors is a P-type transistor, and the other transistor is an N-type transistor. The memory circuit has first and second output terminals for outputting different signals;
A first transistor comprising an N-type transistor connected between the first control line and the pixel electrode and being switched by an output of the first output terminal; 3. A second transistor comprising an N-type transistor connected between a control line and the pixel electrode and switched by an output of the second output terminal. 4. The electrophoretic display device described. The memory circuit has first and second output terminals for outputting different signals;
A first transistor comprising a P-type transistor connected between the first control line and the pixel electrode and switched by an output of the first output terminal; and 3. A second transistor comprising a P-type transistor connected between a control line and the pixel electrode and switched by an output of the second output terminal. 4. The electrophoretic display device described.   The electrophoretic display device according to claim 1, wherein the first and second control lines are wirings common to the plurality of pixels. An electrophoretic element including electrophoretic particles is sandwiched between a pair of substrates, and includes a display unit including a plurality of pixels. The display unit includes a pixel electrode formed for each pixel, and the electrophoresis A counter electrode facing a plurality of the pixel electrodes via elements, and first and second control lines connected to each of the pixels are provided, and for each pixel, a pixel switching element, An electric circuit comprising: a memory circuit connected to the pixel switching element; and a switch circuit connected between the memory circuit and the pixel electrode and connected to the first and second control lines. A method for driving an electrophoretic display device, comprising:
A first step of inputting an image signal to the memory circuit via the pixel switching element;
The first and second potentials are supplied to the first and second control lines, respectively, and the switch circuit is operated based on an output from the memory circuit, thereby causing the pixels from the first or second control line to operate. A second step in which a potential is input to the electrode and a rectangular wave that repeats the first and second potentials is input to the counter electrode for one period or more;
A method for driving an electrophoretic display device, comprising: In the first step, a first image signal is input to the memory circuit of the pixel that displays the first gradation, and a second image signal is input to the memory circuit of the pixel that displays the second gradation. Input the image signal,
In the second step, in the pixel displaying the first gradation, the first control line is operated by operating the switch circuit based on an output of the memory circuit holding the first image signal. And the pixel electrode are connected to each other, and the pixel that displays the second gradation displays the second gradation by operating the switch circuit based on the output of the memory circuit holding the second image signal. The drive line of the electrophoretic display device according to claim 8, wherein the control line and the pixel electrode are connected to each other. The switch circuit includes a first transfer gate connected between the first control line and the pixel electrode, and a second transfer connected between the second control line and the pixel electrode. And have a gate
In the second step,
The first control line is switched on by the low level signal output from the first output terminal of the memory circuit and the high level signal output from the second output terminal. And the pixel electrode are connected,
The second control line and the second control line are switched by turning on the second transfer gate by a high level signal supplied from the first output terminal and a low level signal output from the second output terminal. The driving method of the electrophoretic display device according to claim 9, wherein the pixel electrode is connected. The switch circuit is connected between a first transistor composed of a P-type transistor connected between the first control line and the pixel electrode, and between the second control line and the pixel electrode. A second transistor composed of an N-type transistor,
In the second step,
The first transistor is switched to an ON state by a low level signal output from the memory circuit, thereby connecting the first control line and the pixel electrode, and a high level signal output from the memory circuit. The method for driving an electrophoretic display device according to claim 9, wherein the second control line and the pixel electrode are connected by switching the second transistor to an on state. The switch circuit includes first and second transistors each of which is an N-type transistor, the first control line is connected to the pixel electrode through the first transistor, and the second control A line is connected to the pixel electrode via the second transistor;
In the second step,
The first control line and the pixel electrode are connected by switching the first transistor on by a high level signal output from the first output terminal of the memory circuit,
The second control line and the pixel electrode are connected to each other by switching the second transistor to an on state by a high level signal output from a second output terminal of the memory circuit. The method for driving an electrophoretic display device according to claim 9. The switch circuit includes first and second transistors each made of a P-type transistor, the first control line is connected to the pixel electrode through the first transistor, and the second control A line is connected to the pixel electrode via the second transistor;
In the second step,
The first control line and the pixel electrode are connected by switching the first transistor on by a low level signal output from the first output terminal of the memory circuit,
The second control line and the pixel electrode are connected to each other by switching the second transistor to an on state by a low level signal output from the second output terminal of the memory circuit. The method for driving an electrophoretic display device according to claim 9.   14. The method according to claim 9, wherein, in the second step, all the pixels have the same gradation by supplying signals having the same potential to the first and second control lines. 2. A method for driving an electrophoretic display device according to item 1. In the second step,
The first control line is set to a high impedance state where the first control line is electrically disconnected, and the second potential is supplied to the second control line, whereby at least a part of the pixels of the display portion is A first display step of shifting from a first gradation to the second gradation;
By supplying the first potential to the first control line and setting the second control line to a high-impedance state where the second control line is electrically disconnected, at least a part of the pixels of the display portion is changed to the first control line. A second display step of shifting from the second gradation to the first gradation;
The method for driving an electrophoretic display device according to claim 9, comprising:   16. The method for driving an electrophoretic display device according to claim 15, wherein in the second step, the display image is updated by repeating the first and second display steps.   16. The method according to claim 15, further comprising a step of placing the first and second control lines in a high impedance state electrically disconnected between the first display step and the second display step. Or a driving method of the electrophoretic display device according to 16;   18. The method according to claim 9, further comprising a step of bringing the memory circuit, the switch circuit, and the counter electrode into an electrically disconnected high impedance state after the second step. The driving method of the electrophoretic display device according to the item.   An electrophoretic display device comprising a control unit that executes the driving method according to claim 8.   An electronic apparatus comprising the electrophoretic display device according to claim 1.

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