JP2009134244A - Electrophoresis display device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrophoresis display device wherein a leakage current between pixels is suppressed to enhance reliability, and to provide an electronic apparatus. <P>SOLUTION: The electrophoresis display device has, for every pixel 20, a pixel switching element 24, a diode 10 connected in a forward direction between the pixel switching element 24 and a pixel electrode 21 and a switching transistor 15 connected between the pixel electrode 21 and a low potential power source line 57 (a constant potential wiring line). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electrophoretic display device and an electronic apparatus.

As an active matrix type electrophoretic display device, one having a switching transistor and a memory circuit in a pixel is known (see, for example, Patent Document 1). In the display device described in Patent Document 1, an electrophoretic element including a plurality of microcapsules containing charged particles is bonded to an element substrate on which pixel switching transistors and pixel electrodes are formed, and a counter electrode is provided. The electrophoretic element was sandwiched between the counter substrate and the element substrate.
Then, an image is displayed by controlling charged particles by an electric field generated between a plurality of pixel electrodes sandwiching the microcapsule and the counter electrode.
JP 2003-84314 A

  However, in the conventional electrophoretic display device, since the electrophoretic element is disposed on the plurality of pixel electrodes via the adhesive layer, if a potential difference is generated between the adjacent pixel electrodes, a leakage current is generated via the adhesive layer. There was a problem that occurred. Although this leak current is small per one path, in the case of an active matrix electrophoretic display device having a plurality of pixels, there are a plurality of paths, so that the leak current of the entire electrophoretic display device Increased, leading to an increase in power consumption.

Here, the path of the leakage current in the pixel circuit of the conventional electrophoretic display device will be specifically described.
FIG. 19 is a diagram illustrating one mode of a circuit configuration of a pixel 1020 in a conventional electrophoretic display device.
A pixel switching element 24, a latch circuit 25, a pixel electrode 21, a common electrode 22, and an electrophoretic element 23 are provided in a pixel 1020 illustrated in FIG.
A scanning line 40 is connected to the gate terminal of the pixel switching element 24. The data line 50 is connected to the source terminal of the pixel switching element 24, and the input terminal N1 of the latch circuit 25 is connected to the drain terminal. The output terminal N2 of the latch circuit 25 is connected to the pixel electrode 21. The high potential power supply line 58 and the low potential power supply line 57 are wirings for supplying a power supply voltage to the latch circuit 25.
The individual specific configuration of these components has been described with reference to FIG. 2 and the like in the embodiment described later. Among the components shown in FIG. 19, the components having the same reference numerals as those in FIG. Is a common configuration.

FIG. 20 is an explanatory diagram showing a leak path between adjacent pixels in the electrophoretic display device having the pixel 1020. FIG. 20 shows a leak path LP when the black display pixel 1020B and the white display pixel 1020W are adjacent to each other.
The subscripts “B” and “W” attached to the reference numerals of the components in FIG. 20 clarify whether the component belongs to the black display pixel 1020B or the white display pixel 1020W. There is no other intention.

In the pixel 1020B which is a black display pixel, low level (low potential) image data is input to the latch circuit 25B. Accordingly, a high level (high potential) is output from the output terminal N2B of the latch circuit 25, and a high level is input to the pixel electrode 21B.
On the other hand, in the pixel 1020W that is a white display pixel, high-level image data is input to the latch circuit 25W. Therefore, the low level is output from the output terminal N2W of the latch circuit 25, and the low level is input to the pixel electrode 21W.

  As shown in FIG. 20, when the black display pixel 1020B and the white display pixel 1020W are adjacent to each other, a horizontal electric field is generated due to a potential difference between the pixel electrodes 21B and 21W, and the pixel electrodes 21B and 21W are electrically connected. A leak path LP as shown by an arrow is formed by the influence of slight moisture contained in the adhesive layer 30 fixing the electrophoretic element 23. In other words, the latch circuit 25B (P-type transistor 52B), the pixel electrode 21B, the adhesive layer 30, the pixel electrode 21W, the latch circuit 25W (N-type transistor 51W), and the low-potential power line 57 are leaked from the high-potential power line 58. A leak current is generated.

The above-described leak path LP also occurs in a pixel having a configuration in which a switch circuit is provided between the latch circuit 25 and the pixel electrode 21.
FIG. 21 is a diagram illustrating a circuit configuration of a pixel 1120 including two transmission gates that are switch circuits.
A pixel 1120 illustrated in FIG. 21 includes a pixel switching element 24, a latch circuit 25, transmission gates TG1 and TG2, a pixel electrode 21, a common electrode 22, and an electrophoretic element 23. The transmission gate TG1 is a potential control switch circuit provided between the first control line S1 and the pixel electrode 21, and is based on outputs from the input terminal N1 and the output terminal N2 of the latch circuit 25. The connection state between the control line S1 and the pixel electrode 21 is switched. The transmission gate TG2 is a potential control switch circuit provided between the second control line S2 and the pixel electrode 21, and is based on outputs from the input terminal N1 and the output terminal N2 of the latch circuit 25. The connection state between the control line S2 and the pixel electrode 21 is switched.
The individual specific configuration of these components has been described with reference to FIG. 14 and the like in the embodiment described later. Among the components shown in FIG. 21, the components having the same reference numerals as those in FIG. Is a common configuration.

FIG. 22 is an explanatory diagram showing a leak path between adjacent pixels in the electrophoretic display device having the pixel 1120. FIG. 22 shows a leak path LP between the black display pixel 1120B and the white display pixel 1120W arranged adjacent to each other.
In the following description, it is assumed that a high level (high potential) is input to the first control line S1, and a low level (low potential) is input to the second control line S2. Also, the suffixes “B” and “W” attached to the reference numerals of the components in FIG. 22 are the same as the suffixes in FIG.

In the black display pixel 1120 </ b> B, low-level image data is input to the latch circuit 25. In this case, since the input terminal N1 of the latch circuit 25 is at a low level and the output terminal N2 is at a high level, the transmission gate TG1B is turned on. Thereby, a high level is input to the pixel electrode 21 from the first control line S1.
On the other hand, in the white display pixel 1120 </ b> W, high level image data is input to the latch circuit 25. In this case, since the input terminal N1 of the latch circuit 25 is at a high level and the output terminal N2 is at a low level, the transmission gate TG2W is turned on. Thereby, a low level is inputted to the pixel electrode 21 from the second control line S2.

As shown in FIG. 22, when the high-level pixel electrode 21B and the low-level pixel electrode 21W are adjacent to each other, a horizontal electric field is generated due to the potential difference therebetween, and leakage indicated by an arrow between the pixels 1120B and 1120W. A path LP is formed. That is, a path from the first control line S1 on the pixel 1120B side to the second control line S2 via the transmission gate TG1B, the pixel electrode 21B, the adhesive layer 30, the pixel electrode 21W, and the transmission gate TG2W. Leakage current is generated.
Note that when the potential of the first control line S1 and the potential of the second control line S2 are interchanged, the leak path is reversed.

  As described above, in any of the two types of pixel configurations shown in FIGS. 19 and 21, a leak current between pixels is generated via the adhesive layer 30. The fact that a leak current is generated due to the influence of a slight amount of moisture indicates the possibility that an electrochemical reaction occurs between the pixel electrode 21 and the adhesive layer 30. That is, ionic migration or corrosion that impairs the reliability of the pixel electrode may occur. If noble metals such as gold and platinum are used as the material for forming the pixel electrode, the reliability is improved. However, using noble metals increases the cost and complicates the manufacturing process, so that the manufacturing cost is suppressed while increasing the reliability. It was difficult.

  SUMMARY An advantage of some aspects of the invention is that it provides an electrophoretic display device and an electronic apparatus that can suppress leakage current between pixels and improve reliability.

In order to solve the above problems, an electrophoretic display device according to the present invention includes an electrophoretic element including electrophoretic particles sandwiched between a pair of substrates, and a pixel electrode is formed for each pixel on one of the substrates. An electrophoretic display device in which a common electrode common to a plurality of the pixels is formed on the other substrate, wherein each pixel includes a pixel switching element and a gap between the pixel switching element and the pixel electrode. And a switching transistor connected between the pixel electrode and the constant potential wiring.
According to this configuration, since the forward diode is provided toward the pixel electrode, the reverse current from the pixel electrode to the pixel switching element can be blocked by the diode. In this case, since the leak path leading from the pixel electrode to the wiring or the like via the pixel switching element is blocked, the leak path becomes a path leading from the pixel electrode to the constant potential wiring via the switching transistor. However, since the switching transistor is used to supply a low potential to the pixel electrode or to extract charges from the pixel electrode, a switching transistor having a high resistance can be used. Therefore, in the configuration of the present invention, the leakage path is higher in resistance than the leakage path via the latch circuit and the transmission gate in the conventional pixel circuit, so that the leakage current is reduced. In addition, a reduction in leakage current can prevent a decrease in pixel electrode reliability due to the leakage current.
Therefore, according to the present invention, it is possible to provide an electrophoretic display device that can reduce power consumption and has high reliability.

Preferably, a memory circuit is provided between the pixel switching element and the diode.
According to this configuration, since the image data input to the pixel can be held in the memory circuit, the potential supply to the pixel electrode can be continued without performing data input to the pixel. In addition, since a diode is arranged between the memory circuit and the pixel electrode, the reverse current from the pixel electrode to the memory circuit can be blocked by the diode, and the reverse current can be prevented from affecting the data retained in the memory circuit. can do.

Preferably, the memory circuit is a latch circuit having a plurality of field effect transistors, and the on-resistance of the switching transistor is larger than the on-resistance of the field effect transistor constituting the memory circuit.
In the conventional circuit configuration (FIG. 19) that does not include a diode between the memory circuit and the pixel electrode, the memory circuit becomes a leak path between adjacent pixels. On the other hand, in the electrophoretic display device of the present invention, since the reverse current is blocked by the diode between the memory circuit and the pixel electrode, the switching transistor becomes a leakage path between adjacent pixels.
Therefore, when the on-resistance of the reset transistor is made larger than the on-resistance of the field effect transistor of the memory circuit as in this configuration, the leakage current is reduced at least as compared with the conventional electrophoretic display device. In the present invention, since the switching transistor is used for low-potential input or charge extraction, there are advantages in that the degree of freedom of design is greater than that of the field effect transistor constituting the memory circuit, and the on-resistance is easily increased.

The gate terminal of the switching transistor may be connected to the input terminal of the memory circuit.
In a configuration including a latch circuit as a memory circuit, the memory circuit outputs an inverted signal of the input signal. That is, when a low level is input to the input terminal of the memory circuit, a high level is output from the output terminal, and when a high level is input, a low level is output. Therefore, by connecting the gate terminal of the switching transistor to the input terminal of the memory circuit as in this configuration, the switching transistor is turned on when the low level is output from the memory circuit, and the high level is output from the memory circuit. When it is done, the switching transistor can be operated to be turned off.
Thus, when a high level is input to the pixel electrode, the switching transistor is turned off, so that the high level can be reliably input to the pixel electrode from the output terminal of the memory circuit via the diode. On the other hand, when a low level is input to the pixel electrode, the switching transistor is turned on, so that the pixel electrode and the constant potential wiring are connected and the low level can be input to the pixel electrode.
Therefore, according to the present invention, a potential based on image data input to the memory circuit via the pixel switching element can be reliably input to the pixel electrode.

The gate terminal of the switching transistor may be connected to a common scanning line with the gate terminal of the pixel switching element.
According to this configuration, the switching transistor and the pixel switching element operate in synchronization by the selection signal input via the scanning line. That is, the switching transistor is in an off state except for a period during which image data is input via the pixel switching element (data input period).
Therefore, according to the configuration of the present invention, in addition to blocking the leakage path to the pixel circuit by the diode, the leakage path from the pixel electrode to the constant potential wiring is also kept in the off state except during the data input period. It is interrupted by the switching transistor. As described above, according to the present invention, it is possible to provide an electrophoretic display device that can eliminate a leakage current between adjacent pixels, reduce power consumption, and improve reliability.

Moreover, it can also be set as the structure which has the reset line connected with the gate terminal of the said switching transistor.
According to this configuration, since the switching transistor is connected to the reset line independent of the scanning line, the switching transistor can be controlled independently of the pixel switching element. Therefore, the operation of extracting the charge from the pixel electrode by the switching transistor can be surely executed, and the potential based on the input image data can be reliably input to the pixel electrode. Therefore, according to the present invention, an electrophoretic display device excellent in operation reliability can be provided.

A potential control switch circuit connected to the first and second control lines may be provided between the memory circuit and the diode.
According to this configuration, the first control line or the second control line that is electrically connected to the pixel electrode by operating the potential control switch circuit based on the image data input through the pixel switching element. Can be selected. Accordingly, an electrophoretic display device that can easily control the potential of the pixel electrode can be obtained.
Since the diode is arranged between the potential control switch circuit and the pixel electrode, the reverse current path from the pixel electrode to the first or second control line via the potential control switch circuit is cut off. be able to. Therefore, it is possible to provide an electrophoretic display device in which leakage current between adjacent pixels is reduced and reliability is improved.

The potential control switch circuit includes first and second transmission gates, the first control line is connected to the first transmission gate, and the second control line is connected to the second transmission gate. Are connected, and the diode is preferably provided corresponding to each of the first and second transmission gates.
According to this configuration, when the first and second transmission gates connected to the pixel electrode are provided, the reverse current from one transmission gate to the other transmission gate can be prevented. The internal leakage path can be cut off and power consumption can be suppressed.

A data input period for inputting image data to the memory circuit via the pixel switching element, and an image display period for displaying the image by driving the electrophoretic element based on the output of the memory circuit, A high potential power supply line and a low potential power supply line for supplying a power supply voltage to the memory circuit are connected, and the potential of the low potential power supply line in the image display period is set higher than the potential in the data input period. Preferably it is.
In the electrophoretic display device according to the present invention, since the diode is provided between the memory circuit and the pixel electrode, the diode does not operate when the potential output from the memory circuit is lower than the threshold voltage of the diode, The potential of the pixel electrode does not become a potential corresponding to the output of the memory circuit. Therefore, by raising the potential of the low-potential power supply line during the image display period, the diode operates reliably, so that the potential corresponding to the image data held in the memory circuit can be input to the pixel electrode. .

  An electronic apparatus according to the present invention includes the electrophoretic display device. According to such a configuration, it is possible to provide an electronic device including a display unit with low power consumption and excellent reliability.

Embodiments of the present invention will be described below with reference to the drawings.
In the present embodiment, an electrophoretic display device driven by an active matrix method will be described. Each of the following embodiments shows one aspect of the present invention and does not limit the present invention, and can be arbitrarily changed within the scope of the technical idea of the present invention. Moreover, in the following drawings, in order to make each configuration easy to understand, the actual structure is different from the scale and number of each structure.

[First Embodiment]
FIG. 1 is a plan view schematically showing an electrophoretic display device 1 according to the first embodiment of the present invention. The electrophoretic display device 1 includes a display unit 3 in which a plurality of pixels 20 are arranged, a scanning line driving circuit 60, and a data line driving circuit 70.
The display unit 3 includes a plurality of scanning lines 40 (Y1, Y2,..., Ym) extending from the scanning line driving circuit 60 and a plurality of data lines 50 (X1, X2,..., Xn) extending from the data line driving circuit 70. And are formed. Corresponding to the intersection of the scanning line 40 and the data line 50, the pixel 20 connected to these wirings is provided.

FIG. 2 is a diagram illustrating a circuit configuration of the pixel 20.
As shown in FIG. 2, the pixel 20 includes a pixel switching element 24, a latch circuit (memory circuit) 25, a diode 10, a switching transistor 15, a pixel electrode 21, a common electrode 22, and an electrophoretic element 23. And are provided.
Note that the pixel 1020 illustrated in FIG. 19 corresponds to the pixel 20 illustrated in FIG. 2 in which the diode 10 and the switching transistor 15 are omitted.

  The pixel switching element 24 is a field effect N-type transistor. The scanning line 40 is connected to the gate terminal of the pixel switching element 24, and the data line 50 is connected to the source terminal. The input terminal N1 of the latch circuit 25 is connected to the drain terminal of the pixel switching element 24.

The latch circuit 25 includes a transfer inverter 25a and a feedback inverter 25b, and is a circuit corresponding to an SRAM (Static Random Access Memory) cell. That is, the pixel 20 according to the present embodiment has an SRAM configuration in which image data is held in the latch circuit 25 as a potential.
The output terminal of the transfer inverter 25a is connected to the input terminal of the feedback inverter 25b, and the output terminal of the feedback inverter 25b is connected to the input terminal of the transfer inverter 25a. That is, the transfer inverter 25a and the feedback inverter 25b have a loop structure in which the other output terminal is connected to each other's input terminal.
The input terminal of the transfer inverter 25a (the output terminal of the feedback inverter 25b) is the input terminal N1 of the latch circuit 25, and the output terminal of the transfer inverter 25a (the input terminal of the feedback inverter 25b) is the output terminal of the latch circuit 25. N2. The high potential power supply terminal N3 of the latch circuit 25 is connected to the high potential power supply line 58, and the low potential power supply terminal N4 is connected to the low potential power supply line 57.

  The transfer inverter 25 a includes an N-type transistor 51 and a P-type transistor 52. The gate terminals of the N-type transistor 51 and the P-type transistor 52 are connected to the input terminal N 1 of the latch circuit 25. The source terminal of the N-type transistor 51 is connected to the low potential power line 57, and the drain terminal is connected to the output terminal N2. The source terminal of the P-type transistor is connected to the high potential power supply line 58, and the drain terminal is connected to the output terminal N2.

  The feedback inverter 25 b has an N-type transistor 53 and a P-type transistor 54. The gate terminals of the N-type transistor 53 and the P-type transistor 54 are connected to the output terminal N2 of the latch circuit 25 (the drain terminals of the N-type transistor 51 and the P-type transistor 52). The source terminal of the N-type transistor 53 is connected to the low potential power line 57, and the drain terminal is connected to the input terminal N1. The source terminal of the P-type transistor 54 is connected to the high potential power supply line 58, and the drain terminal is connected to the input terminal N1.

  The diode 10 is connected between the latch circuit 25 and the pixel electrode 21. Specifically, the output terminal N2 of the latch circuit 25 and the anode terminal of the diode 10 are connected, and the cathode terminal of the diode and the pixel electrode 21 are connected. Therefore, the diode 10 is connected in the forward direction from the latch circuit 25 to the pixel electrode 21.

  The switching transistor 15 is a field effect N-type transistor. The source terminal of the switching transistor is connected to the low potential power supply line 57, and the drain terminal is connected to the pixel electrode 21. The gate terminal of the switching transistor 15 is connected to the input terminal N 1 of the latch circuit 25. In the present embodiment, the on-resistance of the switching transistor 15 is set to be larger than the on-resistance of the N-type transistor 51 constituting the latch circuit 25 within a range that does not hinder the potential control of the pixel electrode 21.

In the pixel 20 having the above configuration, when a low level is input to the latch circuit 25, the input terminal N1 is at a low level and the output terminal N2 is at a high level. Since the diode 10 connected to the output terminal N2 is connected in the forward direction from the output terminal N2 toward the pixel electrode 21, a current flows through the diode 10 and a high level is input to the pixel electrode 21.
At this time, since the low level is input to the gate terminal of the switching transistor 15 from the input terminal N1, the switching transistor 15 is in an OFF state. Therefore, the pixel electrode 21 and the low-potential power supply line 57 are not connected, and the potential of the pixel electrode 21 is held at a high level.

On the other hand, when a high level is input to the latch circuit 25, the input terminal N1 is at a high level and the output terminal N2 is at a low level. Accordingly, a low level is input to the anode terminal of the diode 10 connected to the output terminal N2, and no potential difference from the cathode terminal occurs, so the diode 10 is turned off. On the other hand, since the high level is input to the gate terminal of the switching transistor 15 from the output terminal N2, the switching transistor 15 is turned on. Therefore, a low level is input to the pixel electrode 21 from the low potential power supply line 57 via the switching transistor 15.
As described above, the potential based on the image data input to the latch circuit 25 is input to the pixel electrode 21.

FIG. 3 is a partial cross-sectional view of the electrophoretic display device 1 in the display unit 3. The electrophoretic display device 1 has a configuration in which an electrophoretic element 23 formed by arranging a plurality of microcapsules 80 is sandwiched between an element substrate 28 and a counter substrate 29.
In the display unit 3, a plurality of pixel electrodes 21 are arrayed on the electrophoretic element 23 side of the element substrate 28, and the electrophoretic elements 23 are bonded to the pixel electrodes 21 through an adhesive layer 30. A common electrode 22 having a planar shape facing the plurality of pixel electrodes 21 is formed on the counter substrate 29 on the electrophoretic element 23 side, and the electrophoretic element 23 is provided on the common electrode 22.

  The element substrate 28 is a substrate made of glass, plastic, or the like, and is not necessarily transparent because it is disposed on the side opposite to the image display surface. Although not shown, between the pixel electrode 21 and the element substrate 28, the scanning line 40, the data line 50, the pixel switching element 24, the latch circuit 25, the diode 10, and the like shown in FIGS. A switching transistor 15 and the like are formed.

The counter substrate 29 is a substrate made of glass, plastic, or the like, and is a transparent substrate because it is disposed on the image display side. The common electrode 22 formed on the counter substrate 29 is formed using a transparent conductive material such as MgAg (magnesium silver), ITO (indium tin oxide), IZO (indium zinc oxide) or the like.
The electrophoretic element 23 is generally formed in advance on the counter substrate 29 side and is handled as an electrophoretic sheet including the adhesive layer 30. A protective release paper is attached to the adhesive layer 30 side.
In the manufacturing process, the display unit 3 is formed by attaching the electrophoretic sheet from which the release paper is peeled off to the separately manufactured element substrate 28 on which the pixel electrode 21 and the circuit are formed. Yes. For this reason, the adhesive layer 30 exists only on the pixel electrode 21 side.

  FIG. 4 is a schematic cross-sectional view of the microcapsule 80. The microcapsule 80 has a particle size of about 50 μm, for example, and encloses therein a dispersion medium 81, a plurality of white particles (electrophoretic particles) 82, and a plurality of black particles (electrophoretic particles) 83. It is a spherical body. As shown in FIG. 3, the microcapsule 80 is sandwiched between the common electrode 22 and the pixel electrode 21, and one or a plurality of microcapsules 80 are arranged in one pixel 20.

  The outer shell (wall film) of the microcapsule 80 is formed using a transparent polymer resin such as acrylic resin such as polymethyl methacrylate or polyethyl methacrylate, urea resin, or gum arabic.

  The dispersion medium 81 is a liquid that disperses the white particles 82 and the black particles 83 in the microcapsules 80. Examples of the dispersion medium 81 include water, alcohol solvents (methanol, ethanol, isopropanol, butanol, octanol, methyl cellosolve, etc.), esters (ethyl acetate, butyl acetate, etc.), ketones (acetone, methyl ethyl ketone, methyl isobutyl ketone, etc.) ), Aliphatic hydrocarbons (pentane, hexane, octane, etc.), alicyclic hydrocarbons (cyclohexane, methylcyclohexane, etc.), aromatic hydrocarbons (benzene, toluene, benzenes having a long-chain alkyl group ( Xylene, hexylbenzene, hebutylbenzene, octylbenzene, nonylbenzene, decylbenzene, undecylbenzene, dodecylbenzene, tridecylbenzene, tetradecylbenzene)), halogenated hydrocarbons (methylene chloride, chloroform, tetrachloride) Element, and 1,2-dichloroethane), can be exemplified a carboxylate, it may be other oils. These substances can be used alone or as a mixture, and a surfactant or the like may be further blended.

The white particles 82 are particles (polymer or colloid) made of a white pigment such as titanium dioxide, zinc white, and antimony trioxide, and are used, for example, by being negatively charged. The black particles 83 are particles (polymer or colloid) made of a black pigment such as aniline black or carbon black, and are used by being charged positively, for example.
These pigments include electrolytes, surfactants, metal soaps, resins, rubbers, oils, varnishes, compound charge control agents, titanium-based coupling agents, aluminum-based coupling agents, silanes as necessary. A dispersant such as a system coupling agent, a lubricant, a stabilizer, and the like can be added.

Next, the driving method of the electrophoretic display device 1 of the present invention and the operation of the electrophoretic element 23 will be described.
FIG. 5 is a timing chart showing a driving method of the electrophoretic display device 1. FIG. 6 is a diagram for explaining specific operations of the white particles 82 and the black particles 83 in the driving method shown in FIG.

  In the following description, among the pixels 20 arranged in the display unit 3, the pixel 20B that is displayed in black and the pixel 20W that is displayed in white will be described. Therefore, in FIG. 5 and FIG. 6, for convenience of explanation, each symbol is indicated by subscripts “B” and “W”, and these subscripts indicate whether the constituent element belongs to the pixel 20B or 20W. There is no other intention.

FIG. 5 shows the scanning line 40, the data line 50, the high potential power supply line 58, the low potential power supply line 57, the common electrode 22, the pixel electrode 21B of the pixel 20B, and the pixel electrode 21W of the pixel 20W shown in FIG. It shows the potential change over time. “HiZ” in FIG. 5 represents a high impedance state that is electrically disconnected.
Further, FIG. 6 shows the movement mode of the white particles 82 and the black particles 83 in the black display pixel 20B and the white display pixel 20W, respectively.
In the following description, the high-level potential and the low-level potential will be described in detail, but these potential values are examples and can be changed as appropriate.

  First, in step S11 shown in FIG. 5, each wiring of the pixel 20 is electrically connected to the drive circuit so that a signal can be input. Specifically, a low level (0 V) is input to the scanning line 40, a high level (5 V) is supplied to the high potential power supply line 58, and a low level (0 V) is supplied to the low potential power supply line 57. As a result, the latch circuits 25W and 25B are turned on, and the image data input from the data line 50 can be stored.

Next, in step S12, a selection signal (high level of 7V) is input to the scanning line 40. As a result, the pixel switching element 24 is turned on, image data is input from the data line 50 to the latch circuit 25, and the latch circuit 25 stores the input image data.
In the pixel 20B displayed in black, a low level is input as image data, and a high level (5 V) is input from the output terminal N2B of the latch circuit 25 to the pixel electrode 21B. On the other hand, in the pixel 20W displayed in white, a high level is input as image data, and a low level (0 V) is input from the output terminal N2W of the latch circuit 25 to the pixel electrode 21W.
When the low level potential output from the output terminal N2W is the same potential as the potential of the pixel electrode 21W or lower than the pixel electrode 21W, the reset transistor 15 is turned off and the potential from the output terminal N2W is reduced. The output may be interrupted by the reset transistor 15. However, in this case as well, the reset transistor 15 is turned on by a high level signal output from the input terminal N1W of the latch circuit 25, and the pixel electrode 21W and the low-potential power supply line 57 have the same potential. Becomes a low level potential.

  Thereafter, in step S13, the potential of the high potential power supply line 58 is raised from 5V to 15V. The potential of the low potential power line 57 remains 0V. Thereby, in the pixel 20B displayed in black, the potential output from the output terminal N2B of the latch circuit 25B rises to a high level (15V), so the potential of the pixel electrode 21B also rises from 5V to 15V. Note that the potential does not vary in the pixel 20W that is displayed in white.

Next, in step S14, a rectangular reference pulse that repeats a low level (0V) period and a high level (15V) period is input to the common electrode 22 for a plurality of periods (four periods in the figure).
This driving method is referred to as “common swing driving” in the present application. The common swing drive is defined as a drive in which at least one cycle of a pulse that repeats a high level (H) period and a low level (L) period is applied to the common electrode 22 in a period during which the display image is rewritten. It is a method.
According to this common swing driving method, the potential applied to the pixel electrode and the common electrode can be controlled by binary values of a high level (H) and a low level (L). The configuration can be simplified. Further, when a TFT (Thin Film Transistor) is used as the switching element of each pixel electrode 21 (21B, 21W), there is an advantage that the reliability of the TFT can be secured by low voltage driving.

Here, the operation of the pixels 20B and 20W in the common swing drive will be described with reference to FIG.
FIG. 6A shows a mode when the low level (L; 0 V) of the first cycle pulse in the common swing drive is applied to the common electrode 22.
In the pixel 20B, a high level (H; 15V) is applied to the pixel electrode 21B, and a low level (L; 0V) is applied to the common electrode 22. Therefore, a vertical electric field is formed between the pixel electrode 21 </ b> B and the common electrode 22, and the positively charged black particles 83 are attracted to the common electrode 22. On the other hand, the negatively charged white particles 82 are attracted to the pixel electrode 21B.
At this time, in the pixel 20W, since the common electrode 22 and the pixel electrode 21W are both at a low level (L; 0V), an electric field is not formed between these electrodes, and thus each particle does not move.

FIG. 6B shows a mode when a high level (H; 15 V) in the first cycle pulse is applied to the common electrode 22.
In the pixel 20 </ b> W, a low level (0 V) is applied to the pixel electrode 21 </ b> W, and a high level (15 V) is applied to the common electrode 22. Accordingly, a vertical electric field is formed between the pixel electrode 21 </ b> W and the common electrode 22, and the negatively charged white particles 82 are attracted to the common electrode 22. On the other hand, the positively charged black particles 83 are attracted to the pixel electrode 21W.
At this time, in the pixel 20B, since both the common electrode 22 and the pixel electrode 21B are at a high level (15 V), an electric field is not formed between these electrodes, and thus each particle does not move.

FIG. 6C shows a mode immediately after a pulse of one period in the common swing drive is applied.
In the pixel 20B, the black particles 83 gather on the common electrode 22 side and the white particles 82 gather on the pixel electrode 21B side, so that a black display on the common electrode 22 side serving as a display surface is observed.
In the pixel 20W, the white particles 82 are gathered on the common electrode 22 side and the black particles 83 are gathered on the pixel electrode 21W side. Therefore, white display on the common electrode 22 side serving as a display surface is observed.
The above is the driving mode in one cycle pulse. By performing this for a plurality of cycles, the movement of the white particles 82 and the black particles 83 can be performed more reliably, so that the contrast can be increased. Note that the number and frequency of the common swing drive are preferably determined as appropriate according to the specifications and characteristics of the electrophoretic element.

  In addition, red, green, blue, etc. can be displayed on the display part 3 by replacing the pigment used for the white particle 82 and the black particle 83 with pigments, such as red, green, and blue, for example.

  When the image display operation in step S14 is completed, the process proceeds to step S15 as shown in FIG. In step S15, the high potential power supply line 58, the low potential power supply line 57, and the scanning line 40 are in a high impedance state, and each circuit is in an off state. Accordingly, the pixel electrodes 21W and 21B are also in a high impedance state.

  Through the above steps S11 to S15, white display and black display in each pixel 20 can be performed. And a display image can be updated sequentially by repeating step S11-S15.

(Leakage current)
Next, a leakage current between adjacent pixels in the electrophoretic display device 1 will be described.
FIG. 7 is an explanatory diagram of a leak path between adjacent pixels. FIG. 7 shows a leak path when the black display pixel 20B and the white display pixel 20W are arranged adjacent to each other.
In FIG. 7, the subscripts “B” and “W” attached to each reference sign clarify whether the constituent element belongs to the pixel 20B or 20W, and have no other meaning.

A high level is input to the pixel electrode 21B of the black display pixel 20B. At this time, since the low level is inputted as the image data to the input terminal N1B of the latch circuit 25B, the P-type transistor 52B is turned on and the output terminal N2B is at the high level. Accordingly, a high level is input from the output terminal N2B to the pixel electrode 21B via the diode 10B.
Further, since the low level is input from the input terminal N1B to the gate terminal of the switching transistor 15B, the switching transistor 15B is turned off, and the low-potential power line 57 and the pixel electrode 21B are electrically disconnected.

  On the other hand, a low level is input to the pixel electrode 21W of the white display pixel 20W. At this time, since the high level is inputted as image data to the input terminal N1W of the latch circuit 25W, the N-type transistor 51W is on and the output terminal N2W is at the low level. Further, since a high level is input to the gate terminal of the switching transistor 15W, the switching transistor 15W is turned on, and the low potential power line 57 and the pixel electrode 21W are electrically connected.

  Even in such a condition, when a horizontal electric field is formed by the potential difference between the pixel electrodes 21B and 21W, the pixel 20B passes through the adhesive layer 30 due to the influence of slight moisture contained in the adhesive layer 30. A current flowing to the pixel 20W is generated. This current is supplied from the high-potential power line 58 on the pixel 20B side through the P-type transistor 52B, the diode 10B, the pixel electrode 21B, the adhesive layer 30, the pixel electrode 21W, and the switching transistor 15W. This is the current that follows the leak path LP flowing to the line 57.

  The reason why the switching transistor 15W becomes a leakage path is that the diode 10W is provided between the pixel electrode 21W and the latch circuit 25W. That is, since the direction from the pixel electrode 21W toward the latch circuit 25W is the reverse direction of the diode 10W, no current flows, and a leakage current flows through the switching transistor 15W that is in the on state.

However, in this embodiment, the on-resistance of the switching transistor 15 is set higher than the on-resistance of the N-type transistors 51 and 53 forming the latch circuit 25, so that the case shown in FIGS. Leakage current is reduced. That is, in the leak path shown in FIG. 20, a leak current flows through the N-type transistor 51W of the latch circuit 25W, but in this embodiment, the switching transistor 15W having a higher resistance than the N-type transistor 51W becomes the leak path. Therefore, the leakage current is reduced by the higher resistance.
In the present embodiment, since the switching transistor 15 only supplies a low level potential to the pixel electrode 21, even if the on-resistance is increased, the operation hardly occurs. Therefore, if the on-resistance of the switching transistor 15 is increased within a range where the voltage application to the pixel electrode 21 can be sufficiently performed, the leakage current can be further reduced.

As described above in detail, according to the electrophoretic display device 1 of the present embodiment, the following operational effects can be obtained.
First, by providing the diode 10 between the latch circuit 25 and the pixel electrode 21, it is possible to prevent a reverse current from flowing from the pixel electrode 21 to the latch circuit 25. Therefore, the leak path between adjacent pixels via the latch circuit 25 in the conventional pixel circuit shown in FIGS. 19 and 20 can be blocked.
On the other hand, since the leakage path to the latch circuit 25 is cut off, the switching transistor 15 becomes a leakage path. In this embodiment, the on-resistance of the switching transistor 15 is set higher than the on-resistance of the N-type transistor 51 of the latch circuit 25. It is getting bigger. Therefore, in this embodiment, the leakage current can be reduced more than the conventional configuration in which at least the leakage path through the N-type transistor 51 of the latch circuit 25 is formed.
As described above, according to the electrophoretic display device 1 of the present embodiment, the leakage current between pixels can be reduced, and the power consumption of the entire display device can be reduced. In addition, since the occurrence of ionic migration and corrosion at the pixel electrode 21 due to current flowing through the adhesive layer 30 can be suppressed, reliability can be improved.

  Further, according to the present embodiment, since the diode 10 is provided, the reverse current from the pixel electrode 21 to the latch circuit 25 can be interrupted by the diode 10, so that the reverse current is stored in the latch circuit 25 and the operation Can be prevented.

  In this embodiment, since the latch circuit 25 that holds the image data is provided, a constant potential based on the image data can be continuously input to the pixel electrode 21 without performing a refresh operation. Note that the diode 10 does not operate when a low level is output from the output terminal N2 of the latch circuit 25. In this case, however, the switching transistor 15 is turned on by the output from the input terminal N1 of the latch circuit 25 to reduce the voltage. Since the potential power supply line 57 and the pixel electrode 21 are connected, the display operation is not hindered.

[Second Embodiment]
Next, a second embodiment will be described. In the second embodiment, the wiring form of the switching transistor 15 in the first embodiment is changed and the driving method thereof is devised.

  FIG. 8 is a diagram illustrating a circuit configuration of the pixel 120 provided in the electrophoretic display device according to the second embodiment of the invention. Since the basic configuration of the electrophoretic display device of the second embodiment is the same as that of the first embodiment, the same reference numerals are given to the same components in FIGS. Detailed description will be omitted.

  As shown in FIG. 8, the pixel 120 includes a pixel switching element 24, a latch circuit (memory circuit) 25, a diode 10, a reset transistor (switching transistor) 115, a pixel electrode 21, a common electrode 22, The electrophoretic element 23 is provided. Among these components, the pixel switching element 24, the latch circuit 25, the diode 10, the pixel electrode 21, the common electrode 22, and the electrophoretic element 23 have the same configuration as that of the pixel 20 shown in FIG.

  The reset transistor 115 is a field effect N-type transistor. The reset transistor 115 has a source terminal connected to the low potential power supply line 57, a drain terminal connected to the pixel electrode 21, and a gate terminal connected to the scanning line 40.

In the pixel 120, the gate terminal of the pixel switching element 24 and the gate terminal of the reset transistor 115 are connected to the same scanning line 40. Therefore, on / off switching of the pixel switching element 24 and the reset transistor 115 is performed in synchronization with a selection signal input via the scanning line 40.
Therefore, when a selection signal is input through the scanning line 40, the pixel switching element 24 is turned on and image data is input from the data line 50 to the latch circuit 25, and the reset transistor 115 is turned on and the pixel electrode. 21 and the low-potential power line 57 are connected, and an operation of inputting a low level to the pixel electrode 21 is performed in parallel.
That is, in the pixel 120, each time an image data input operation is performed, the reset transistor 115 operates to return (reset) the potential of the pixel electrode 21 to a low level. When the input of the image data is completed and the pixel switching element 24 is turned off, the reset transistor 115 is also turned off and the pixel electrode 21 and the low-potential power supply line 57 are disconnected, and the image is output to the pixel electrode 21. The potential corresponding to the data can be input.

After the pixel electrode 21 is returned to the low level in this way, the potential input from the latch circuit 25 to the pixel electrode 21 is performed.
First, when a low level is input as image data to the latch circuit 25, the input terminal N1 of the latch circuit 25 is at a low level and the output terminal N2 is at a high level. As a result, a high level is input to the anode terminal of the diode 10, and a high level is input to the pixel electrode 21 via the diode 10. At this time, since the reset transistor 115 is off, the high-level potential input to the pixel electrode 21 does not decrease.

On the other hand, when a high level is input as image data to the latch circuit 25, the input terminal N1 is at a high level and the output terminal N2 is at a low level. At this time, since the low level is input from the output terminal N2 to the anode terminal of the diode 10, both the anode terminal and the cathode terminal are at the low level. Then, since there is no potential difference between the anode terminal and the cathode terminal, the diode 10 is off and no current flows.
Therefore, in the present embodiment, by raising the potential of the low potential power supply line 57 after inputting image data, a potential difference is generated between the anode terminal and the cathode terminal of the diode 10 so that the diode 10 is reliably turned on. Yes. Thereby, a desired potential can be input to the pixel electrode 21. Such an operation will be described in detail in the following description of the driving method.

(Driving method of electrophoretic display device)
FIG. 9 is a diagram illustrating a sequence related to image rewriting according to the second embodiment. FIG. 10 is a diagram illustrating a timing chart according to the image display of the second embodiment. FIG. 11 is an explanatory diagram relating to potential input to the pixel electrode 21. FIG. 12 is an explanatory diagram showing adjacent black display pixels and white display pixels.

  Hereinafter, the driving method will be described in detail with reference to FIGS. 9 to 11. In the following description, as shown in FIG. 12, one of the two pixels 120 connected to the same scanning line 40 is displayed. A case where a pixel is displayed in white and the other pixel is displayed in black will be described. Note that description of portions common to the driving method in the first embodiment shown in FIG. 5 will be omitted as appropriate.

In addition, when it is necessary to clearly distinguish the constituent elements of the pixel 120 that is displayed in white from the constituent elements of the pixel 120 that is displayed in black, the reference numerals indicating the constituent elements of the white display pixel are used, as shown in FIG. The subscript “W” is attached, and the subscript “B” is added to the mark indicating the component of the black display pixel.
That is, the pixel 120 that is displayed in white is referred to as a pixel 120W, and similarly, is described as a latch circuit 25W, a reset transistor 115W, a diode 10W, and the like. On the other hand, the pixel 120 displayed in black is referred to as a pixel 120B, a latch circuit 25B, a reset transistor 115B, a diode 10B, and the like.

As shown in FIG. 9, in the driving method of this embodiment, step S101 for turning on the power of each circuit, input of image data to the latch circuits 25W and 25B, and removal of charges from the pixel electrodes 21W and 21B are performed. Step S102, step S103 in which the potential of the high potential power supply line 58 is raised to 15V and the potential of the low potential power supply line 57 to 1V, and a reference pulse for repeating the 1V period and the 15V period to the common electrode 22 a plurality of times. Step S104 for inputting, and Step S105 for turning off the power of each circuit are included.
In addition, the applied voltage value in FIG.9 and FIG.10 is an example, and is not limited to these.

  FIG. 10 shows a timing chart regarding the pixel 120W displayed in white and the pixel 120B displayed in black. Specifically, corresponding to the sequence of FIG. 9, the scanning line 40, the high potential power supply line 58, the low potential power supply line 57, the common electrode 22, the pixel electrode 21 </ b> B of the pixel displayed in black, and the white A waveform inputted to the pixel electrode 21W of the pixel to be displayed is shown. “HiZ” indicates an electrically disconnected high impedance state.

  First, in step S101, as in step S11 shown in FIG. 5, each circuit of the electrophoretic display device 1 is connected to each wiring of the display unit 3, and a signal can be supplied. At this time, since the scanning line 40 is at a low level (0 V), the reset transistors 115W and 115B are in an off state.

Next, the process proceeds to step S102 which is a data input period.
In step S102, the potential of the high potential power supply line 58 is held at a high level (5V), and the potential of the low potential power supply line 57 is held at a low level (0V). Then, a high level (7 V) potential is input to the gate terminals of the pixel switching elements 24W and 24B and the gate terminals of the reset transistors 115W and 115B via the scanning line 40. Accordingly, the pixel switching elements 24W and 24B and the reset transistors 115W and 115B are turned on.

  Here, when the reset transistors 115W and 115B are turned on, as shown in FIG. 11B, the pixel electrodes 21W and 21B and the low-potential power line 57 are connected, and the charges of the pixel electrodes 21W and 21B are low. The power supply line 57 is pulled out. As a result, as shown in FIG. 10, the potentials of the pixel electrode 21 </ b> W of the white display pixel and the pixel electrode 21 </ b> B of the black display pixel are both at the same low level (0 V) as that of the low potential power line 57.

When the pixel switching elements 24W and 24B are turned on by the selection signal, potentials based on the image data are input from the data line 50 to the latch circuits 25W and 25B in the pixels 120W and 120B, respectively.
Accordingly, a high level (5V) is input as image data to the latch circuit 25W of the pixel 120W that displays white, and a low level (0V) is output from the output terminal N2W of the latch circuit 25W.
On the other hand, a low level (0V) is input as image data to the latch circuit 25B of the pixel 120B displayed in black, and a high level (5V) is output from the output terminal N2B of the latch circuit 25B.

  Note that, during the selection period of the pixel switching elements 24W and 24B, the reset transistors 115W and 115B are also in the on state. Therefore, as shown in FIG. The potential of 21B remains at a low level (0 V).

  Thereafter, after a lapse of a predetermined period, the potential of the scanning line 40 shifts from a high level (7 V) to a low level (0 V). Accordingly, the pixel switching elements 24W and 24B and the reset transistors 115W and 115B are turned off.

During this period, in the pixel 120W that displays white, the potential of the output terminal N2W of the latch circuit 25W and the potential of the pixel electrode 21W are both low (0 V), so that no potential difference occurs between the anode terminal and the cathode terminal of the diode 10W. The diode 10W is off. Therefore, as shown in FIG. 10, the pixel electrode 21W is in a high impedance state electrically disconnected from other circuits and wirings.
On the other hand, in the pixel 120B displayed in black, the high level (5 V) output from the output terminal N2B of the latch circuit 25B is input to the pixel electrode 21B via the diode 10B. That is, as shown in FIG. 11A, after the reset transistor 115B is turned off, a high level (5 V) is input from the latch circuit 25B to the pixel electrode 21B via the diode 10B. As a result, the potential of the pixel electrode 21B rises to a high level (5 V) as shown in FIG.

Next, the process proceeds to step S103.
In step S103, the potential of the high potential power supply line 58 is raised from 5V to 15V, and the potential of the low potential power supply line 57 is raised from 0V to 1V.

Then, in the pixel 120W that displays white, the potential output from the output terminal N2W of the latch circuit 25W rises to a low level (1V) as shown in FIG. As a result, the potential difference between the anode terminal and the cathode terminal of the diode 10W becomes 1V, the diode 10W is turned on, and a low level (1V) is input to the pixel electrode 21W via the diode 10W.
On the other hand, in the pixel 120B displayed in black, the potential output from the output terminal N2B of the latch circuit 25B rises to a high level (15V), so that the pixel is passed through the diode 10B as shown in FIG. This potential is input to the electrode 21B. Thereby, as shown in FIG. 10, the potential of the pixel electrode 21B rises to a high level (15V).

Next, the process proceeds to step S104, which is an image display period.
In step S104, as shown in FIG. 10, the potential of the high potential power supply line 58 is held at a high level (15V), and the potential of the low potential power supply line 57 is held at a low level (1V). A rectangular pulse that repeats a low level (1 V) period and a high level (15 V) period is input to the common electrode 22 for a plurality of periods (four periods in the figure). (Common swing drive)

Thereby, in the pixel 120W that displays white, the electrophoretic element 23 is driven with the maximum potential difference (14V in the present embodiment) that can be used between the pixel electrode 21W and the common electrode 22.
Specifically, since a low level (1V) is input to the pixel electrode 21W, a potential difference is generated between the electrodes during a period in which the common electrode 22 is at a high level (15V). Due to this potential difference, the white particles 82 move to the common electrode 22 side, and the black particles 83 move to the pixel electrode 21W side, whereby the pixel 120W is displayed in white.
In this embodiment, the low level of the pulse input to the common electrode 22 is 1V. This is because the low level potential of the pixel electrode 21W is set to 1V. Therefore, if the low level of the common electrode 22 is set to 0V, the potential of the common electrode 22 becomes lower than the pixel electrode 21W during the low level period. This is because the pixel 120W temporarily performs a black display operation.

On the other hand, also in the pixel 120 </ b> B displaying black, the electrophoretic element 23 is driven with the maximum potential difference (14 V in this example) that can be used between the pixel electrode 21 </ b> B and the common electrode 22.
Specifically, since a high level (15V) is input to the pixel electrode 21B, a potential difference is generated between the electrodes during a period in which the common electrode 22 is at a low level (1V). Due to this potential difference, the black particles 83 move to the common electrode 22 side, and the white particles 82 move to the pixel electrode 21B side, whereby the pixel 120B is displayed in black.

Next, the process proceeds to step S105, which is an image holding period.
In step S105, as in S15 shown in FIG. 5, each circuit is turned off, and the pixel electrodes 21W and 21B are also in a high impedance state.
Furthermore, the display image can be sequentially updated by repeating the above steps S101 to S105.

  In the present embodiment, the operation of increasing the potential of the low potential power supply line 57 from 0V to 1V is performed together with the operation of increasing the potential of the high potential power supply line 58 from 5V to 15V in step S103. The operation of raising the potential of the low potential power supply line 57 can be arbitrarily set independently of the timing of raising the potential of the high potential power supply line 58. Specifically, the process can be executed at any timing after the input of the image data to the latch circuit 25 is completed and until the input of the reference pulse to the common electrode 22 is started.

(Leakage current)
Next, a leakage current in the electrophoretic display device according to the present embodiment will be described with reference to FIG. FIG. 12 shows a black display pixel 120B and a white display pixel 120W which are arranged adjacent to each other, and also a leak path assumed.

In FIG. 12, low level image data is input to the latch circuit 25B of the pixel 120B, and the high level output from the output terminal N2B of the latch circuit 25B is input to the pixel electrode 21B via the diode 10B. Further, since the scanning line 40 is at a low level, the reset transistor 115B is in an off state.
On the other hand, high level image data is input to the latch circuit 25W of the pixel 120W, and low level is input from the output terminal of the latch circuit 25W to the pixel electrode 21W via the diode 10W. Further, since the scanning line 40 is at a low level, the reset transistor 115W is in an off state.

As a leak path in the state described above, a path indicated by a dotted line in FIG. 12 can be assumed. That is, this is a path from the high potential power supply line 58 on the black display pixel 120B side to the reset transistor 115W via the P-type transistor 52B, the diode 10B, the pixel electrode 21B, the adhesive layer 30, and the pixel electrode 21W. .
However, in the pixel 120W, since the reset transistor 115W is in the off state, the leak path is blocked. Further, the current toward the latch circuit 25W is also blocked by the diode 10W. Therefore, in the electrophoretic display device of the present embodiment, no leak current occurs between adjacent pixels.

  As described above in detail, in the electrophoretic display device of this embodiment, the reset transistor 115 operates in synchronization with the pixel switching element 24 because the gate terminal of the reset transistor 115 is connected to the scanning line 40. That is, the reset transistor 115 maintains an off state except for a period during which image data is input to the latch circuit 25, and holds the pixel electrode 21 and the low potential power supply line 57 in a disconnected state. Therefore, the diode 10 and the reset transistor 115 provided between the latch circuit 25 and the pixel electrode 21 can completely block the leak path. Therefore, according to the electrophoretic display device of the present embodiment, the leakage current between adjacent pixels can be eliminated, and further reduction of power consumption can be realized. Moreover, since the possibility of ionic migration and corrosion in the pixel electrode 21 is reduced by eliminating the leak path, reliability can be improved.

  In this embodiment, after image data is input to the latch circuit 25, the potential of the low-potential power supply line 57 is raised, and the low level output from the latch circuit 25 is set to 1V. Thus, even when a low level is output from the latch circuit 25, the diode 10 can be reliably turned on, and a predetermined potential can be reliably input to the pixel electrode 21.

  On the other hand, when the potential of the low potential power supply line 57 is increased, the low level potential input to the pixel electrode 21 is also increased. Therefore, as in the first embodiment, a 0-15 V reference pulse is input to drive the common oscillation. Doing so may cause problems in the display. Therefore, in the present embodiment, the low level potential of the reference pulse input to the common electrode 22 is set to 1 V so that the low level potential of the common electrode 22 does not fall below the low level potential of the pixel electrode 21, and malfunction in image rewriting. Is preventing.

(Modification)
Next, a modification of the second embodiment will be described with reference to FIG. FIG. 13 is a diagram illustrating a circuit configuration of the pixel 220 according to the present modification.
The pixel circuit configuration in the electrophoretic display device of this modification is provided with a capacitor instead of the latch circuit 25 in the pixel 120 of FIG. Note that components common to the pixel 120 in FIG. 8 are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 13, the pixel 220 includes a pixel switching element 24, a capacitor 225, a diode 10, a reset transistor 115, a pixel electrode 21, a common electrode 22, and an electrophoretic element 23. Among the above components, the configuration of the pixel switching element 24, the diode 10, the reset transistor 115, the pixel electrode 21, the common electrode 22, and the electrophoretic element 23 is the same as that of the pixel 120 illustrated in FIG.

One electrode of the capacitor 225 is connected to the drain terminal of the pixel switching element 24 and the anode terminal of the diode 10. The other electrode of the capacitor 225 is connected to a capacitor line (not shown). In the pixel 220, a potential based on image data input from the data line 50 via the pixel switching element 24 is held in the capacitor 225 for a certain period.
Note that the other electrode of the capacitor 225 may be connected to the low-potential power line 57.

  Also in the pixel 220 having the above configuration, the reset transistor 115 can be turned on and off in synchronization with the pixel switching element 24 because the gate terminal of the reset transistor 115 is connected to the scanning line 40. Then, the potential of the pixel electrode 21 can be controlled similarly to the pixel 120 by switching the reset transistor 115 on and off.

Further, since the reset transistor 115 is turned off except during a period in which image data is written to the capacitor 225 and the pixel electrode 21 through the pixel switching element 24, the current from the pixel electrode 21 toward the low potential power supply line 57 is cut off. Is done. In addition, since the diode 10 is provided between the capacitor 225 and the pixel electrode 21, the current from the pixel electrode 21 toward the capacitor 225 is also cut off.
Therefore, also in the electrophoretic display device of this example, the leakage current due to the potential difference between adjacent pixels can be eliminated, and the power consumption can be reduced. Moreover, since the possibility of ionic migration and corrosion in the pixel electrode 21 is reduced by eliminating the leak path, reliability can be improved.

[Third Embodiment]
Next, a third embodiment of the present invention will be described with reference to FIGS.
FIG. 14 is a diagram illustrating a circuit configuration of a pixel 320 according to the third embodiment, and FIG. 15 is an operation explanatory diagram of the electrophoretic display device according to the third embodiment.
In the electrophoretic display device of the third embodiment, the pixel 120 according to the second embodiment shown in FIG. 8 is provided with a transmission gate as a potential control switch circuit. Therefore, in the drawings to be referred to below, the same components as those of the pixel 120 in FIG. 8 are denoted by the same reference numerals, and detailed description thereof is omitted.
Note that the pixel 1120 illustrated in FIG. 21 corresponds to a pixel in which the diode and the reset transistor are omitted from the pixel 320 illustrated in FIG.

  As shown in FIG. 14, the pixel 320 includes a pixel switching element 24, a latch circuit (memory circuit) 25, transmission gates TG1 and TG2 which are potential control switch circuits, diodes 331 and 332, and a reset transistor (switching). Transistor) 115, pixel electrode 21, common electrode 22, and electrophoretic element 23.

  Among the above components, the pixel switching element 24, the latch circuit 25, the pixel electrode 21, the common electrode 22, the electrophoretic element 23, and the reset transistor 115 have the same configuration as the pixel 120 in FIG.

The transmission gate TG1 includes a field effect type P-type transistor T11 and a field effect type N-type transistor T12. The source terminals of the P-type transistor T11 and the N-type transistor T12 are connected to each other, and these are connected to the first control line S1. The drain terminals of the P-type transistor T11 and the N-type transistor T12 are connected to each other, and these are connected to the diode 331.
The gate terminal of the P-type transistor T11 is connected to the input terminal N1 of the latch circuit 25, and the gate terminal of the N-type transistor T12 is connected to the output terminal N2 of the latch circuit 25.

The transmission gate TG2 includes a field effect type P-type transistor T21 and a field effect type N-type transistor T22. The source terminals of the P-type transistor T21 and the N-type transistor T22 are connected to each other, and these are connected to the second control line S2. The drain terminals of the P-type transistor T21 and the N-type transistor T22 are connected to each other, and these are connected to the diode 332.
The gate terminal of the P-type transistor T21 is connected to the output terminal N2 of the latch circuit 25 together with the gate terminal of the N-type transistor T12 of the transmission gate TG1, and the gate terminal of the N-type transistor T22 is connected to the transmission gate TG1. The gate terminal of the P-type transistor T11 is connected to the input terminal N1 of the latch circuit 25.

  The diode 331 is connected in the forward direction between the transmission gate TG1 and the pixel electrode 21. That is, the anode terminal of the diode 331 is connected to the drain terminals of the P-type transistor T11 and the N-type transistor T12, and the cathode terminal is connected to the pixel electrode 21 and the drain terminal of the reset transistor 115.

  The diode 332 is connected in the forward direction between the transmission gate TG2 and the pixel electrode 21. That is, the anode terminal of the diode 332 is connected to the drain terminals of the P-type transistor T21 and the N-type transistor T22, and the cathode terminal is connected to the pixel electrode 21 and the drain terminal of the reset transistor 115.

  In the pixel 320 having the above-described configuration, when low level image data is input from the data line 50 to the latch circuit 25 via the pixel switching element 24, the low level is output from the input terminal N1 and the output terminal N2 of the latch circuit 25. High level is output. Accordingly, only the P-type transistor T11 and the N-type transistor T12 constituting the transmission gate TG1 are turned on. Thereby, the anode terminal of the diode 331 is electrically connected to the first control line S1.

  On the other hand, when high level image data is input from the data line 50 to the latch circuit 25 via the pixel switching element 24, a high level is output from the input terminal N1 and a low level is output from the output terminal N2. Accordingly, only the P-type transistor T21 and the N-type transistor T22 constituting the transmission gate TG2 are turned on. As a result, the anode terminal of the diode 332 is electrically connected to the second control line S2.

  Also in the present embodiment, the reset transistor 115 is turned on together with the pixel switching element 24 during the period in which the image data is input to the latch circuit 25. Therefore, as shown in FIG. The low potential power supply line 57 is connected, and a low level is input to the pixel electrode 21.

Thereafter, by inputting a high level (15 V) to the first control line S1 and a low level (1 V) to the second control line S2, the electrophoretic element 23 is driven to perform a desired display for each pixel. Can do.
In the pixel 320 to which the low level is input to the latch circuit 25, the transmission gate TG1 is turned on, and a high level (15 V) is input to the anode terminal of the diode 331. As a result, a current flows through the diode 331 and the pixel electrode 21 A high level (15 V) is input to.
On the other hand, in the pixel 320 to which the high level is input to the latch circuit 25, the transmission gate TG2 is turned on, and the low level (1 V) is input to the anode terminal of the diode 332, whereby the diode 332 is turned on. A low level (1 V) is input to the pixel electrode 21.
The reason why the low level potential of the second control line S2 is 1V is that the anode terminal of the diode 332 is 0V when the low level potential is 0V, as in the second embodiment. This is because the diode 332 is turned off and the second control line S2 and the pixel electrode 21 are not connected.

  Then, in a state where a predetermined potential is input to the pixel electrode 21 from the first control line S1 or the second control line S2, a reference for repeating the low level (1V) and the high level (15V) to the common electrode 22 By inputting a pulse, the pixel 320 can perform predetermined black display or white display (common swing drive).

  In the present embodiment, the case where the high level is input to the first control line S1 and the low level is input to the second control line S2 has been described. However, the mode of the image data (normal image data) input to the latch circuit 25 is described. , Inverted image data, gradation image data), the potential levels of the first control line S1 and the second control line S2 can be changed.

Further, if the potential levels of the first control line S1 and the second control line S2 are switched and a reference pulse is input to the common electrode 22 while the image data is held in the latch circuit 25, the latch circuit 25 Inverted image display can be performed without updating the image data.
Further, if a reference pulse is input to the common electrode 22 with the first control line S1 and the second control line S2 being at the same potential, the entire white line is used regardless of the image data held in the latch circuit 25. Display or all black display can be easily performed.

(Leakage current)
In the pixel 320 having such a circuit configuration, a leak path when a potential difference is generated between the pixel electrodes 21 of the adjacent pixels 320 can be eliminated.
FIG. 15 shows a black display pixel 320B and a white display pixel 320W arranged adjacent to each other. In FIG. 15, the subscripts “B” and “W” attached to the constituent elements of the pixel 320 are intended to clarify whether the constituent element belongs to the pixels 320B and 320W, and have no other meaning.

  In the pixel 320B, the transmission gate TG1B is on, and the high level of the first control line S1 is input to the pixel electrode 21B. On the other hand, in the adjacent pixel 320W, the transmission gate TG2W is in the on state, and the low level of the second control line S2 is input to the pixel electrode 21W.

In this state, assuming that a leakage current is generated in the adhesive layer 30 due to a horizontal electric field formed between the adjacent pixel electrodes 21B and 21W, the leakage path is from the transmission gate TG1B of the pixel 320B. This is a path that reaches the transmission gate TG2W of the pixel 320W via the pixel electrode 21B, the adhesive layer 30, and the pixel electrode 21W.
However, in the present embodiment, the diode 332W is provided between the pixel electrode 21W and the transmission gate TG2W, and the direction from the pixel electrode 21W toward the transmission gate TG2W is the reverse direction of the diode 332W. Is blocked by a diode 332W. At this time, since the reset transistor 115 of the pixel 320W is off, the leakage path through the reset transistor 115 is also blocked.

  Therefore, in the electrophoretic display device of this embodiment, the leakage path between adjacent pixels is blocked by the diode 332 and the reset transistor 115. That is, there is no leak path as in the conventional pixel circuit shown in FIGS. 21 and 22, and no leak current flows between adjacent pixels.

  As described above in detail, according to the electrophoretic display device of this embodiment, the diodes 331 and 332 are provided between the pixel electrode 21 and the transmission gates TG1 and TG2, so that the transmission gates TG1 and TG2 are interposed. Since the leakage path between adjacent pixels can be blocked, the leakage current between adjacent pixels can be eliminated and the power consumption can be reduced. Further, this can reduce the possibility of ionic migration and corrosion in the pixel electrode 21, so that reliability can be improved.

  In the present embodiment, the diodes 331 and 332 are provided corresponding to the transmission gates TG1 and TG2, respectively. As a result, the drain terminal side of the transmission gate in the off state can always be in a high impedance state. Therefore, when new image data is input to the latch circuit 25, or when the potential of the low potential power supply line 57 and the potential of the high potential power supply line 58 fluctuate, even if the transmission gates TG1 and TG2 are simultaneously turned on, the transmission gate Leakage current generation in the same pixel through TG1 and TG2 can be prevented.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described with reference to FIG.
FIG. 23 is a diagram illustrating a circuit configuration of a pixel 120A according to the fourth embodiment.
In the electrophoretic display device according to the fourth embodiment, the pixel 120 according to the second embodiment illustrated in FIG. 8 is provided with a reset line 41 that controls on / off of the reset transistor 115. Therefore, in the drawings to be referred to below, the same components as those of the pixel 120 in FIG. 8 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The pixel 120A is provided with a pixel switching element 24, a latch circuit 25, a diode 10, a reset transistor 115, a pixel electrode 21, a common electrode 22, and an electrophoretic element 23. A reset line 41 is provided at a position along the scanning line 40. The gate terminal of the reset transistor 115 connected to the scanning line 40 in the pixel 120 shown in FIG. 8 is connected to the reset line 41 in this embodiment. In the present embodiment, the reset line 41 is connected to the scanning line driving circuit 60, and a reset signal output from the scanning line driving circuit 60 is input to the reset transistor 115. Alternatively, a drive circuit for the reset line 41 may be provided.

  In the electrophoretic display device according to the present embodiment, since the reset line 41 independent of the scanning line 40 is provided, the reset transistor 115 is operated at an arbitrary timing by a reset signal input via the reset line 41. Can be made. Therefore, the charge of the pixel electrode 21 can be reliably released, and the potential input to the pixel electrode 21 through the latch circuit 25 and the diode 10 is prevented from competing with the potential held in the pixel electrode 21. It is possible to prevent unintended display.

(Driving method)
Hereinafter, the driving method of the electrophoretic display device of this embodiment will be described with reference to FIGS.
FIG. 24 is a diagram illustrating a sequence related to image rewriting in the electrophoretic display device according to the fourth embodiment. FIG. 25 is a diagram illustrating a timing chart according to the image display of the second embodiment. FIG. 26 is an explanatory diagram showing black display pixels and white display pixels. FIGS. 24 to 26 correspond to FIGS. 9 to 11 used in the description of the second embodiment.
Note that description of portions common to the driving method in the second embodiment will be omitted as appropriate.

  First, FIG. 26 shows two pixels 120A connected to the same scanning line 40 to be described. When it is necessary to clearly distinguish the constituent elements of the pixel 120A displayed in white and the constituent elements of the pixel 120A displayed in black, the subscript “W” ", And a subscript" B "is added to a symbol indicating a component of a black display pixel. That is, the pixel 120A that is displayed in white is referred to as a pixel 120W, and is similarly expressed as a latch circuit 25W, a reset transistor 115W, a diode 10W, and the like. On the other hand, the pixel 120A displayed in black is referred to as a pixel 120B, a latch circuit 25B, a reset transistor 115B, a diode 10B, and the like.

As shown in FIG. 24, according to the driving method of the present embodiment, step S201 for turning on the power of each circuit, step S202 for removing charges from the pixel electrodes 21W and 21B, and images to the latch circuits 25W and 25B. Step S203 for inputting data, Step S204 for raising the potential of the high potential power supply line 58 to 15V and the potential of the low potential power supply line 57 to 1V, and a reference pulse for repeating the 1V period and the 15V period for the common electrode 22 Is input a plurality of times, and step S206 is a step of powering off each circuit.
In addition, the applied voltage value in FIG.24 and FIG.25 is an example, and is not limited to these.

  FIG. 25 shows a timing chart regarding the pixel 120W (120A) displayed in white and the pixel 120B (120A) displayed in black. Specifically, corresponding to the sequence of FIG. 24, the scanning line 40, the reset line 41, the high-potential power line 58, the low-potential power line 57, the common electrode 22, and the pixel of the pixel to be displayed in black. The waveforms input to the electrode 21B and the pixel electrode 21W of the pixel displayed in white are shown. “HiZ” indicates an electrically disconnected high impedance state.

  First, in step S201, as in step S101 shown in FIG. 10, each circuit of the electrophoretic display device is connected to each wiring of the display unit 3, and a signal can be supplied. At this time, since the reset line 41 is at a low level (0 V), the reset transistors 115W and 115B are in an off state.

Next, in step S202, as shown in FIG. 25, a high level (7V) pulse as a reset signal is supplied to the reset line 41 and input to the gate terminals of the reset transistors 115W and 115B. Thereby, the reset transistors 115W and 115B are turned on.
When the reset transistors 115W and 115B are turned on, as shown in FIG. 11B, the pixel electrodes 21W and 21B and the low-potential power line 57 are connected, and the charges of the pixel electrodes 21W and 21B are reduced to the low-potential power supply. It is pulled out to the line 57. Thereby, the potentials of the pixel electrode 21 </ b> W of the white display pixel and the pixel electrode 21 </ b> B of the black display pixel are both at the same low level (0 V) as that of the low potential power supply line 57.

  Next, the process proceeds to step S203, which is a data input period, and a high level (5 V) is input as image data to the latch circuit 25W of the pixel 120W by the same operation as in step S102 shown in FIG. A low level (0 V) is input to the latch circuit 25B as image data.

  In the present embodiment, the reset transistors 115W and 115B are in the OFF state during the selection period of the pixel switching elements 24W and 24B, and therefore the output based on the data held in the latch circuits 25W and 25B is transmitted via the diode 10. Input to the pixel electrodes 21W and 21B. Thereby, the potential of the pixel electrode 21B becomes high level (5V). Further, the potential of the pixel electrode 21 </ b> W holds the potential (low level (0 V)) when connected to the low potential power supply line 57 via the reset transistor 115.

  Next, in step S204, a low level (1 V) potential is input to the pixel electrode 21W via the diode 10W and the pixel electrode 21B is set to a high level (by the same operation as step S103 shown in FIG. 15V) is input via the diode 10W.

  Thereafter, when the process proceeds to step S205, which is an image display period, the common electrode 22 has a rectangular shape that repeats a low level (1V) period and a high level (15V) period as in step S104 shown in FIG. Pulses are input for a plurality of cycles (four cycles in the figure) (common swing drive). Thereby, the pixel 120W is displayed in white, and the pixel 120B is displayed in black.

In step S206, which is an image retention period, each circuit is turned off, and the pixel electrodes 21W and 21B are also brought into a high impedance state. As a result, a display image is retained without consuming power.
Furthermore, the display image can be sequentially updated by repeating the above steps S201 to S206.

As described above in detail, in the driving method of the present embodiment, step S202 for releasing the charge of the pixel electrode 21 is provided prior to step S203 for inputting image data to the latch circuit 25. Thus, when image data is input to the latch circuit 25, the pixel electrode 21 is once brought to the same potential as the low potential power line 57. Therefore, the potential output from the latch circuit 25 can be surely input to the pixel electrode 21 regardless of the timing of image data input to the latch circuit 25 (selection timing of the pixel switching element 24), and excellent operation reliability is achieved. Sex can be obtained.
Also, in the electrophoretic display device of this embodiment, it is needless to say that the same effects as the electrophoretic display device according to the second embodiment can be obtained.

(Modification)
Next, a modification of the fourth embodiment will be described with reference to FIG. FIG. 27 is a diagram illustrating a circuit configuration of the pixel 220A according to the present modification, and corresponds to FIG. 13 in the second embodiment.
The pixel circuit configuration in the electrophoretic display device of the present modification is provided with a capacitor instead of the latch circuit 25 in the pixel 120A of FIG. In the following description, the same components as those of the pixel 120A in FIG.

  The pixel 220 </ b> A includes a pixel switching element 24, a capacitor 225, a diode 10, a reset transistor 115, a pixel electrode 21, a common electrode 22, and an electrophoretic element 23. The gate terminal of the reset transistor 115 is connected to the reset line 41 extending along the scanning line 40. Only the gate terminal of the pixel switching element 24 is connected to the scanning line 40.

Also in the pixel 220 </ b> A having the above-described configuration, the reset transistor 115 can be turned on / off independently of the pixel switching element 24 by connecting the gate terminal of the reset transistor 115 to the reset line 41. . Then, the potential of the pixel electrode 21 can be controlled by switching the reset transistor 115 on and off, similarly to the pixel 120A. Therefore, also in the electrophoretic display device of this example, the charge of the pixel electrode 21 can be reliably released, and excellent operation reliability can be obtained.
Also, in the electrophoretic display device of this example, it is needless to say that the same operational effects as those of the electrophoretic display device according to the modification of the second embodiment can be obtained.

[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described with reference to FIG.
FIG. 28 is a diagram illustrating a circuit configuration of a pixel 320A according to the fifth embodiment.
In the electrophoretic display device of the fifth embodiment, the pixel 320 according to the third embodiment shown in FIG. 14 is provided with a reset line 41 that controls on / off of the reset transistor 115. Therefore, in the drawings referred to below, the same components as those of the pixel 320 in FIG. 14 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The pixel 320A includes a pixel switching element 24, a latch circuit 25, transmission gates TG1 and TG2, diodes 331 and 332, a reset transistor 115, a pixel electrode 21, a common electrode 22, and an electrophoretic element 23. ing. In the pixel 320 shown in FIG. 14, the gate terminal of the reset transistor 115 connected to the scanning line 40 is connected to the reset line 41 in this embodiment.

  In the electrophoretic display device according to the present embodiment, since the reset line 41 independent of the scanning line 40 is provided, the reset transistor 115 is operated at an arbitrary timing by a reset signal input via the reset line 41. Can be made. Therefore, the charge of the pixel electrode 21 can be reliably released, and the potential input to the pixel electrode 21 via the transmission gates TG1 and TG2 and the diodes 331 and 332 is the same as the potential held in the pixel electrode 21. You can prevent conflicts. As a result, unintended display can be prevented and excellent operational reliability can be obtained.

[Electronics]
Next, an electronic apparatus provided with the electrophoretic display device of the present invention will be described.

First, FIG. 16 is a front view of the wristwatch 400. The wristwatch 400 includes a watch case 402 and a pair of bands 403 connected to the watch case 402.
A display body 405, a second hand 421, a minute hand 422, and an hour hand 423 are provided on the front face of the watch case 402, and a crown 410 and an operation button 411 as operating elements are provided on the side of the watch case 402. ing. The crown 410 is connected to a winding stem (not shown) provided inside the case, and is integrated with the winding stem so that it can be pushed and pulled in multiple stages (for example, two stages) and can be rotated. .
The display body 405 includes the electrophoretic display device according to the present invention, and can display a background image, a character string such as date and time, a second hand, a minute hand, and an hour hand. Since the wristwatch 400 includes the electrophoretic display device of the present invention, the wristwatch 400 includes a table itself that has low power consumption and excellent reliability.

FIG. 17 is a perspective view showing the electronic paper 500.
The electronic paper 500 includes the electrophoretic display device of the present invention as the display unit 501. The electronic paper 500 has flexibility, and includes a main body 502 formed of a rewritable sheet having the same texture and flexibility as conventional paper.

FIG. 18 is a perspective view showing an electronic notebook 600.
An electronic notebook 600 is obtained by bundling a plurality of electronic papers 500 shown in FIG. The cover 601 includes display data input means (not shown) for inputting display data sent from an external device, for example. Thereby, according to the display data, the display content can be changed or updated while the electronic paper is bundled.

Since the electronic paper 500 and the electronic notebook 600 are provided with the electrophoretic display device of the present invention, the electronic paper 500 and the electronic notebook 600 are provided with display means with low power consumption and excellent reliability.
Note that the electrophoretic display device of the present invention is not limited to the electronic devices exemplified above, and can be used as a display means of, for example, a mobile phone and a portable audio device. It functions as a display means with excellent reliability.

1 is a schematic configuration diagram of an electrophoretic display device according to a first embodiment. The circuit block diagram of a pixel. The fragmentary sectional view of an electrophoretic display device. The cross-sectional block diagram of a microcapsule. 6 is a timing chart showing a method for driving an electrophoretic display device. The operation explanatory view of a microcapsule. Explanatory drawing of a leak path | route. The circuit block diagram of the pixel of the electrophoretic display device which concerns on 2nd Embodiment. The sequence diagram which concerns on an electrophoretic display apparatus. 6 is a timing chart showing a method for driving an electrophoretic display device. Explanatory drawing which shows the electric potential input to a pixel electrode. Explanatory drawing which shows a leak path | route. The circuit block diagram of the pixel which concerns on the modification of 2nd Embodiment. The circuit block diagram of the pixel of the electrophoretic display device which concerns on 3rd Embodiment. Explanatory drawing which shows a leak path | route. The front view of a wristwatch. The perspective view of electronic paper. The perspective view of an electronic notebook. FIG. 10 is a circuit configuration diagram of a pixel in a conventional electrophoretic display device. Explanatory drawing of a leak path | route. FIG. 10 is a circuit configuration diagram of a pixel in a conventional electrophoretic display device. Explanatory drawing of a leak path | route. The circuit block diagram of the pixel which concerns on 4th Embodiment. The flowchart which shows the drive method which concerns on 4th Embodiment. The timing chart in the drive method which concerns on 4th Embodiment. The figure which shows the electric potential state in two adjacent pixels. The circuit block diagram of the pixel which concerns on the modification of 4th Embodiment. FIG. 10 is a circuit configuration diagram of a pixel according to a fifth embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Electrophoretic display device, 3 ... Display part, 10 ... Diode, 15 ... Reset transistor, 20 ... Pixel, 21 ... Pixel electrode, 22 ... Common electrode, 23 ... Electrophoretic element, 24 ... Pixel switching element, 25 ... Latch Circuit: 30 ... Adhesive layer 40 ... Scanning line 41 ... Reset line 50 ... Data line 57 ... Low potential power line 58 ... High potential power line 60 ... Scanning line driving circuit 70 ... Data line driving circuit 80 ... microcapsule, 82 ... white particle, 83 ... black particle, 115 ... reset transistor, 120,120A ... pixel, 220,220A ... pixel, 225 ... capacitor, 320,320A ... pixel, 331,332 ... diode, 400 ... wristwatch, 500 ... electronic paper, 600 ... electronic notebook, TG1, TG2 ... transmission gate, S1 ... first control line, 2 ... the second control line

Claims (10)

An electrophoretic element including electrophoretic particles is sandwiched between a pair of substrates, a pixel electrode is formed for each pixel on one of the substrates, and a common electrode common to a plurality of the pixels on the other substrate An electrophoretic display device in which is formed,
For each pixel, a pixel switching element, a diode connected in a forward direction between the pixel switching element and the pixel electrode, and a switching transistor connected between the pixel electrode and a constant potential wiring, An electrophoretic display device comprising: The electrophoretic display device according to claim 1,
An electrophoretic display device, wherein a memory circuit is provided between the pixel switching element and the diode. The electrophoretic display device according to claim 2,
The memory circuit is a latch circuit having a plurality of field effect transistors;
An electrophoretic display device, wherein an on-resistance of the switching transistor is larger than an on-resistance of the field effect transistor constituting the memory circuit. The electrophoretic display device according to claim 3,
An electrophoretic display device, wherein a gate terminal of the switching transistor is connected to an input terminal of the memory circuit. The electrophoretic display device according to any one of claims 1 to 3,
An electrophoretic display device, wherein a gate terminal of the switching transistor is connected to a scanning line common to the gate terminal of the pixel switching element. The electrophoretic display device according to any one of claims 1 to 3,
An electrophoretic display device comprising a reset line connected to a gate terminal of the switching transistor. The electrophoretic display device according to any one of claims 2 to 6,
An electrophoretic display device, wherein a potential control switch circuit connected to the first and second control lines is provided between the memory circuit and the diode. The electrophoretic display device according to claim 7,
The potential control switch circuit has first and second transmission gates,
The first control line is connected to the first transmission gate, and the second control line is connected to the second transmission gate,
An electrophoretic display device, wherein the diode is provided corresponding to each of the first and second transmission gates. The electrophoretic display device according to any one of claims 3 to 8,
A data input period for inputting image data to the memory circuit via the pixel switching element, and an image display period for displaying the image by driving the electrophoretic element based on the output of the memory circuit,
A high potential power supply line and a low potential power supply line for supplying a power supply voltage to the memory circuit are connected,
An electrophoretic display device, wherein a potential of the low potential power supply line in the image display period is set higher than a potential in the data input period.   An electronic apparatus comprising the electrophoretic display device according to claim 1.

Images