JP2007206543A - Electro-optical device, driving method, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means for making all pixels display off with a simple configuration and instantly, in a configuration having a memory circuit in each pixel. <P>SOLUTION: The pixel 110 includes the memory circuit for holding one bit; a selection circuit for selecting an on-signal Von, when the held one bit is at H level and for selecting off-signal Voff, when the held one bit is at low level; and a pixel electrode to which the selected on-signal Von or the off-signal Voff is applied. Moreover, a common electrode 185 is faced to these pixel electrodes and is applied with a common signal Vcom. A drive voltage generating circuit 50 outputs the common signal Vcom and the off-signal Voff at the same logical level; and when a signal/Doff is at H level, the circuit makes the on-signal Von to an inversion logical level of the off-signal Voff, while the circuit sets the on-signal to be identical logic level as the off-signal Voff, when the signal/Doff is at L level. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for reducing power consumption of an electro-optical device having a memory circuit for each pixel.

Since portable electronic devices are required to be thinner and lighter, electro-optical devices such as liquid crystal elements and organic EL elements suitable for this requirement are used in electro-optical devices used as display devices for electronic devices. Used. Here, since this type of electro-optical device rewrites (refreshes) the state of each pixel for each frame regardless of the display content, power is consumed by the drive circuit for driving each pixel and its control circuit. Therefore, there was a factor that hindered low power consumption.
Therefore, a technique has been proposed in which a static memory circuit that stores 1 bit for each pixel is incorporated, and pixels are turned on or off in accordance with the bits stored in the memory circuit (see Patent Document 1).
In this technique, refreshing of the memory circuit is not required, so that if a still image is displayed, it is not necessary to operate the drive circuit and the like, and accordingly, power consumption can be reduced.
Japanese Patent Publication No. 3-5724

By the way, the display device of an electronic device may turn off all pixels during the execution of some processing. For example, when switching the menu screen or switching to another application program operation, the screen may be temporarily turned off. This is to consciously notify the user that the switching is being performed by temporarily turning off the screen (for a moment). In addition, before stopping the operation of the display device, it is necessary to display all pixels off by an off sequence operation.
However, in a configuration in which a memory circuit is built in each pixel, there is a situation in which attempting to display all the pixels off may lead to a complicated configuration. For example, a logic circuit that supplies an off signal to all the pixels and ignores the bits stored in the memory circuit and performs an off display according to the off signal is required.

  The present invention has been made in view of the above-described circumstances, and an object thereof is to drive an electro-optical device capable of displaying pixels off in a relatively simple manner in a configuration having a memory circuit for each pixel, and driving thereof. It is to provide a method and an electronic device.

  In order to solve the above-described problem, the present invention includes a plurality of pixels and a common electrode that is common to the plurality of pixels and to which a common signal having a predetermined voltage is applied. And the one-bit logic level held in the memory circuit is selected, an off signal having the same voltage as the common signal is selected, and the held one-bit logic level is An electro-optical device comprising: a selection circuit that selects a predetermined ON signal when it is the other; and a pixel electrode that is opposed to the common electrode and to which an ON signal or an OFF signal selected by the selection circuit is applied A first mode in which display is performed on a pixel based on one bit held by the memory circuit, and the memory circuit holds the first mode. Regardless of the bit, the pixel has a second mode in which the pixel is turned off. When the first mode is designated, the on signal is set to a voltage different from that of the common signal. When specified, the ON signal is set to the same voltage as the common signal. According to the present invention, it is possible to instantaneously display all pixels off with a very simple configuration.

In the present invention, when the first mode is designated, the logic level of the common signal and the off signal is inverted at a constant period, and the logic level of the common signal and the off signal is inverted for the on signal. Is preferably reversed.
In this method, when the second mode is designated, the common signal and the off signal may be fixed to one of logic levels, and the common signal and the off signal may be fixed. The logic level may be inverted in a cycle of the above, and the ON signal may have the same logic level as the common signal and the OFF signal.
The present invention can be conceptualized not only as a method for driving an electro-optical device but also as an electro-optical device. In the electro-optical device, the pixel is provided corresponding to an intersection of a plurality of word lines and a plurality of bit lines, and the pixel corresponding to the selected word line among the plurality of word lines is the pixel. A configuration may be employed in which one bit supplied to the corresponding bit line is held.
The present invention can also be conceptualized as an electronic apparatus having the electro-optical device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The electro-optical device according to the first embodiment of the present invention is a liquid crystal device using a liquid crystal element as an electro-optical element, and includes an element substrate on which various transistors and pixel electrodes are formed, and a counter substrate on which a common electrode is formed. Are attached with a certain gap so that the electrode forming surfaces face each other, and a TN (twisted nematic) type liquid crystal is sandwiched between the gaps.

FIG. 1 is a block diagram showing an electrical configuration of the electro-optical device in this state.
As shown in this figure, in the display region 100 of the electro-optical device 10, 240 word lines 121 each extend in the row (X) direction, while 320 sets of bit lines 131 and complementary bit lines 132 exist. , Each extending in the column (Y) direction. The pixels 110 are provided corresponding to the intersections of the 240 word lines 121 and the 320 bit lines 131 (complementary bit lines 132). For this reason, in the present embodiment, the pixels 110 are arranged in a matrix of 240 rows × 320 columns, but the present invention is not limited to this arrangement.

The Y address decoder 20 exclusively outputs an H level row selection signal to the word line 121 of the row designated by the Y address Ady supplied from the upper control circuit (not shown).
For convenience, in the display area 100, row selection signals supplied to the word lines 121 in the first, second, third,..., 240th rows from the top are denoted as S1, S2, S3,. is doing. In addition, when the row selection signal is generally described without particularly specifying a row, it is expressed as Si. Here, i is an integer satisfying 1 ≦ i ≦ 240. The signal line to which the Y address Ady is supplied is shown by one thick line in the figure, but is actually composed of 8 (2 to the 8th power = 256 ≧ 240).

On the other hand, the X address decoder 30 exclusively outputs the column selection signals X1, X2, X3,..., X320 corresponding to the column specified by the X address Adx supplied from the upper control circuit as the H level. . Note that the column selection signal is expressed as Xj when it is generally described without specifying a column. Here, j is an integer satisfying 1 ≦ j ≦ 320.
The sample and hold circuit 40 samples and supplies the data bit Da supplied from the upper control circuit to the bit line 131 of the j-th column when the column selection signal Xj of a certain column becomes H level, A bit obtained by inverting the logic of the data bit Da is supplied to the complementary bit line 132 in the j-th column. Note that the sample-and-hold circuit 40 causes both the bit line 131 and the complementary bit line 132 to be in the H level or the high impedance state for the column corresponding to the column selection signal whose logic level is the L level.
For convenience, the bits supplied to the bit lines 131 in the first, second, third,..., 320 columns in the display area 100 from the left are denoted as D1, D2, D3,. Inverted bits supplied to the complementary bit lines 132 are denoted as / D1, / D2, / D3,..., / D320, and are denoted as Dj and / Dj when generally described without specifying a column. In addition, the signal line to which the X address Adx is supplied is shown by one thick line in the figure. However, when only one bit is designated by one address, nine (2 9 = 512 ≧ 320) Consists of.

On the other hand, the electro-optical device 10 is further supplied with a clock signal CLK and a signal / Doff that defines an operation mode from the upper control circuit. Among these, the clock signal CLK is a logic signal having a frequency of 30 Hz and a duty ratio of 50%. Here, for convenience, when the cycle of the clock signal CLK is 2F, the logic level of the clock signal CLK is inverted every period F. In the present embodiment, this period F is referred to as a frame period.
In the present embodiment, as the operation mode, a display mode (first mode) in which all pixels are displayed in accordance with data bits held in a memory circuit described later, and data held in the memory circuit are displayed. Regardless of the bit, it has an off mode (second mode) for displaying off. Here, if the signal / Doff is at the H level, the display mode is designated, and if the signal / Doff is at the L level, the off mode is designated.

The drive voltage generation circuit 50 is a circuit formed by a polysilicon process on the element substrate, and generates an off signal Voff (common signal Vcom) and an on signal Von by a logical operation of the clock signal CLK and the signal / Doff. Is.
Specifically, the drive voltage generation circuit 50 includes a NOT circuit 502, AND circuits 504 and 506, and buffer circuits 508 and 510, as shown in FIG. Among these, the NOT circuit 502 outputs a negative signal of the clock signal CLK, the AND circuit 504 outputs a logical product signal of the clock signal CLK and the signal / Doff, and the AND circuit 506 outputs a negative signal of the clock signal CLK. AND signal / Doff is output. Note that the buffer circuit 508 performs buffering so as to increase the driving capability of the AND signal by the AND circuit 504. Similarly, the buffer circuit 510 performs buffering so as to increase the driving capability of the AND signal by the AND circuit 506.

In this configuration, when the signal / Doff is at the H level and the display mode is designated, the off signal Voff has the same logic level as the clock signal CLK, and the on signal Von inverts the logic level of the clock signal CLK. On the other hand, when the signal / Doff is at the L level and the off mode is designated, the off signal Vof f and the on signal Von are forcibly set to the L level.
2B illustrates the positive logic circuit illustrated in FIG. 2A as a negative logic circuit. The AND circuit 504 includes a NOT circuit 522 and a NOR circuit 524, a NOT circuit 502, and an AND circuit. The circuit 506 is replaced with a NOR circuit 526 and a NOR circuit 528, respectively.

The off signal Voff output from the drive voltage generation circuit 50 in the element substrate is supplied to the signal line 142 formed in the display region 100, and is guided to the counter substrate through a conductive material or the like, and is supplied to the common electrode 185. Applied as a common signal Vcom. For this reason, the logic levels of the off signal Voff and the common signal Vcom are the same. The on signal Von output from the drive voltage generation circuit 50 is supplied to the signal line 141 formed in the display region 100.
Of the logical levels of the off signal Voff (common signal Vcom) and the on signal Von, the H level corresponds to the power supply voltage Vdd, and the L level corresponds to the voltage-referenced ground potential Gnd (0 volt).

Next, details of the pixel 110 will be described. Each pixel 110 is structurally identical to each other, and therefore will be described by using the pixel 110 located in i row and j column as a representative. FIG. 3 is a circuit diagram showing a configuration of the pixel 110 in i row and j column.
As shown in FIG. 3, the pixel 110 includes a static memory circuit 150, a selection circuit 160, and a liquid crystal element 180.
Among these, the memory circuit 150 includes n-channel TFTs (thin film transistors) 151 and 152 and NOT circuits 155 and 156. Regarding the TFT 151, its source is connected to the bit line 131 in the j-th column, its drain is connected to the input terminal of the NOT circuit 155, and its gate is connected to the i-th word line 121. The output terminal of the NOT circuit 155 is connected to the input terminal of the NOT circuit 156, and the output terminal of the NOT circuit 156 is fed back to the input terminal of the NOT circuit 155.
Since the memory circuit 150 is a complementary type, the source of the TFT 152 is connected to the complementary bit line 132 in the j-th column, the drain is connected to the input terminal of the NOT circuit 156, and the gate is the i-th row. Are connected to the word line 121.

Therefore, in the memory circuit 150, when the row selection signal Si supplied to the word line 121 becomes H level, the TFTs 151 and 152 are turned on and the bit Dj supplied to the bit line 131 is stored at the terminal Q ( The inversion bit / Dj supplied to the complementary bit line 132 is stored at the terminal / Q). Thereafter, even if the row selection signal Si becomes L level and the TFTs 151 and 152 are turned off, the stored contents are static. It becomes the structure held by.
Even when the row selection signal Si supplied to the word line 121 becomes H level, if both the bit line 131 and the complementary bit line 132 are at H level or in a high impedance state, the stored contents can be rewritten. Therefore, the characteristics of the NOT circuits 155 and 156 are defined.

The selection circuit 160 includes transmission gates 162 and 164. Here, the input terminal of the transmission gate 162 is connected to the signal line 141 to which the ON signal Von is supplied, while the input terminal of the transmission gate 164 is connected to the signal line 142 to which the OFF signal Voff is supplied. The output ends of the gates 162 and 164 are commonly connected to pixel electrodes 181 formed individually for each pixel.
Also, the control gate of transmission gate 162 and the inversion control gate of transmission gate 164 are connected to terminal Q in memory circuit 150, while the inversion control gate of transmission gate 162 and the control gate of transmission gate 164 are in memory circuit 150. Connected to terminal / Q.
Therefore, if the terminal Q is at the H level (if the terminal / Q is at the L level), the transmission gates 162 and 164 are turned on and off, respectively, and the on signal Von is applied to the pixel electrode 181, while the terminal When Q is at L level (when terminal / Q is at H level), the transmission gates 162 and 164 are turned off and on, respectively, and an off signal Voff is applied to the pixel electrode 181.

The liquid crystal element 180 has a configuration in which a TN liquid crystal 183 is sandwiched between an individual pixel electrode 181 for each pixel and a common electrode 185 common to the pixels.
Although not particularly illustrated, each opposing surface of both substrates is provided with an alignment film that is rubbed so that the major axis direction of the liquid crystal molecules is continuously twisted, for example, by about 90 degrees between the two substrates. A polarizer corresponding to the orientation direction is provided on each back side of both substrates. For this reason, the light passing between the pixel electrode 181 and the common electrode 185 rotates about 90 degrees along the twist of the liquid crystal molecules if the voltage effective value between the two electrodes is zero, while the voltage effective value As is increased, the liquid crystal molecules are tilted in the direction of the electric field, and as a result, their optical rotation disappears. For this reason, for example, in the transmission type, when the polarizer is disposed on the incident side and the back side so that the polarization axes coincide with the alignment direction, the light transmittance increases if the voltage effective value is small, If the effective voltage value is large, the transmittance is low (normally white mode).

  In the present embodiment, the drive voltage generation circuit 50 is as described above, but the Y address decoder 20, the X address decoder 30, and the sample and hold circuit 40 are also components (memory) of the pixel 110 in the display region 100. The circuit 150 and the selection circuit 160) are formed by a common polysilicon process.

Next, the operation of the electro-optical device 10 according to this embodiment will be described.
First, since the electro-optical device 10 is based on the premise that the data bits are stored in the memory circuit 150 of each pixel 110, the operation of storing the data bits in the memory circuit 150 will be described.
Here, for example, when data bits are stored in the pixel 110 in the i-th row and j-th column, the upper control circuit outputs the X-address Adx specifying the j-th column together with the Y-address Ady specifying the i-th row, The data bit Da to be stored in the pixel 110 in the i row and j column is output.

  With this X address Adx, the X address decoder 30 sets the column selection signal Xj to the H level. As a result, the sample and hold circuit 40 samples the data bit Da to be stored, and at the j-th bit line 131 as the bit Dj, and logically inverts the sampled data bit Da as the inverted bit / Dj. These are supplied to the complementary bit lines 132 in the j-th column. The bit lines 131 and the complementary bit lines 132 other than the j-th column are in the H level or high impedance state.

On the other hand, with the Y address Ady designating the i-th row, the Y address decoder 20 sets only the row selection signal Si to the H level.
In the pixel 110 in the i row and j column, since the row selection signal Si becomes H level, the TFTs 151 and 152 are turned on, and the bit Dj supplied to the bit line 131 is supplied to the terminal Q and the complementary bit line 132. The inverted bits / Dj are written to the terminals / Q, respectively.
In this state, when the row selection signal Si becomes L level, in the pixel 110 in the i row and j column, the TFTs 151 and 152 are turned off, the terminal Q in the memory circuit 150 is from the bit line 131, and the terminal / Q is the complementary bit. Although electrically disconnected from each line 132, the memory circuit 150 will continue to hold the written bits.

Immediately after the power is turned on, such a writing operation is performed on all the pixels 110, and thereby, either the H or L level data bit is held in the memory circuit 150 in all the pixels. The
When the display content is changed, the data bit Da that defines the display content after the change is supplied from the upper control circuit together with the X address Adx and the Y address Ady, and is designated by the X address Adx and the Y address Ady. The data bits held in the memory circuit 150 of the selected pixel are rewritten.

Next, a description will be given in terms of what happens to the liquid crystal element 180 in each of the display mode and the off mode when the data bits are held in the respective pixels 110 as described above. FIG. 4 is a diagram illustrating a voltage applied to the liquid crystal element in the display mode and the off mode.
First, when the display mode is designated, as described above and as shown in FIG. 4, the off signal Voff and the on signal Von are in a relationship in which the logic levels are inverted.
Here, in the memory circuit 150 of the pixel 110, when the L level data bit is held at the terminal Q (when the H level is held at the terminal / Q), the transmission gates 162 and 164 are turned off and on, respectively. Therefore, the off signal Voff having the same logical level as the common signal Vcom applied to the common electrode 185 is applied to the pixel electrode 181 of the pixel. Therefore, the voltage VLC applied to the liquid crystal element 180, here the voltage obtained by subtracting the potential of the common electrode 185 from the potential of the pixel electrode 181 is zero as shown in FIG. If so, the pixel is turned off.

On the other hand, in the memory circuit 150, when the H level data bit is held at the terminal Q (when the L level is held at the terminal / Q), the transmission gates 162 and 164 are turned on and off, respectively. An on signal Von having a logical inversion relationship with respect to the common signal Vcom is applied to the pixel electrode 181 of the pixel.
For this reason, the voltage VLC applied to the liquid crystal element 180 is + Vdd or -Vdd, so that in the normally white mode, the pixel is turned on.

Subsequently, when the off mode is designated, as described above and as shown in FIG. 4, both the off signal Voff and the on signal Von are forcibly set to the L level.
In the memory circuit 150 of the pixel 110, when the L level data bit is held at the terminal Q (when the H level is held at the terminal / Q), the off signal Voff is supplied to the pixel electrode 181 of the pixel. On the other hand, when the H level data bit is held at the terminal Q (when the L level is held at the terminal / Q), the ON signal Von is applied to the pixel electrode 181 of the pixel. However, if the off mode is designated, the off signal Voff and the on signal Von are both at the L level, so that the voltage VLC applied to the liquid crystal element 180 is forced regardless of the retained data bits. Will be zero.
For this reason, in the off mode, all the pixels 110 are in an off state that becomes brighter in the normally white mode.

According to the electro-optical device 10, when the off mode is designated, all the pixels 110 can be instantaneously turned off with a relatively simple configuration.
This effect will be described in comparison with the conventional technique. For example, when the off mode is designated as in the present embodiment, the effect of causing all the pixels 110 to be instantaneously turned off is as follows. It is also possible to provide a logic circuit that supplies the signal / Doff to each pixel 110 and supplies the signal / Doff to each pixel 110 in accordance with the signal / Doff regardless of the data bit stored in the memory circuit 150. However, a configuration in which such a logic circuit is provided in all the pixels 110 causes enlargement and complexity of the entire circuit, and is not realistic.
In addition, the sample and hold circuit 40 is provided with a logic circuit for supplying a logical sum signal of the data bit and the signal / Doff to the bit line 131 for each column, and the word line 121 is sequentially selected, so that the memory circuit of each pixel. Although a method of writing data bits to be displayed off in 150 is conceivable, this method complicates the configuration of the sample and hold circuit 40 and requires a certain amount of time until data bits to be displayed off in all pixels are written. Cost.
On the other hand, in this method, if all the word lines are simultaneously selected and data bits to be displayed off in the memory circuits 150 of all the pixels are simultaneously written, it is possible to display off instantaneously. Therefore, it is necessary to greatly increase the driving capability of the bit line 131 by the sample and hold circuit 40 (the output impedance of the final stage buffer circuit needs to be lowered).
On the other hand, according to the electro-optical device 10 according to the present embodiment, the drive voltage generation circuit 50 is common to all the pixels 110 without adding any configuration to the sample and hold circuit 40 or the display region 100. In addition, since it is not necessary to supply the signal / Doff for designating the mode to the display area 100, when the off mode is designated, all the pixels 110 can be instantly turned off with a relatively simple configuration. It is possible to make it.

In the first embodiment described above, when the off mode is designated, the on signal Von, the off signal Voff, and the common signal Vcom are fixed at the L level, but may be fixed at the H level.
In the first embodiment, when the off mode is designated, the logic levels of the off signal Voff and the common signal Vcom are fixed to one, and the on signal is set to the same level as the fixed logic level. Since Von is generated, there is an advantage that power consumed by inversion of the logic level can be suppressed. However, in order to instantaneously turn off all the pixels, it is not necessarily fixed.
Therefore, a description will be given of a second embodiment in which when the off mode is designated, the logic levels of the off signal Voff and the common signal Vcom are not fixed.

  FIG. 5 is a block diagram illustrating a configuration of the electro-optical device according to the second embodiment. 5 is different from FIG. 1 in a drive voltage generation circuit 50. Specifically, in the second embodiment, the drive voltage generation circuit 50 outputs the clock signal CLK as it is as the off signal Voff (common signal Vcom), while the on signal Von is obtained by a logical operation of the clock signal CLK and the signal / Doff. Includes an ON signal generation circuit 60.

  Specifically, the ON signal generation circuit 60 includes NOT circuits 602 and 604, NAND circuits 606, 608, and 610 and a buffer circuit 612, as shown in FIG. Among these, the NOT circuit 602 outputs a negative signal of the clock signal CLK, and the NOT circuit 604 outputs a negative signal of the signal / Doff. The NAND circuit 606 outputs a negative logical product signal of the clock signal CLK and the negative signal of the signal / Doff, and the NAND circuit 608 outputs a negative logical product signal of the negative signal of the clock signal CLK and the signal / Doff. To do. Further, the NAND circuit 610 outputs a negative logical product signal of the output signals of the NAND circuits 606 and 608. The buffer circuit 612 buffers the NAND circuit 610 so as to enhance the driving capability of the NAND signal.

  In this configuration, when the signal / Doff is H level and the display mode is designated, the ON signal Von is a signal obtained by inverting the logic level of the clock signal CLK, while the signal / Doff is L level and OFF. When the mode is designated, the ON signal Von has the same logic level as the clock signal CLK.

  Note that such an ON signal generation circuit that generates the ON signal Von may have a configuration as shown in FIG. 6B in addition to the configuration shown in FIG. That is, the ON signal generation circuit 60 includes NOT circuits 622 and 624, transmission gates 626 and 628, and a buffer circuit 612. If the signal / Doff is at the H level, the transmission gate 628 is turned on and the NOT circuit 622 A negative signal of the clock signal CLK, and if the signal / Doff is at the L level, the transmission gate 626 is turned on to select the clock signal CLK and output it as the on signal Von via the buffer circuit 612. good.

In the second embodiment, when the signal / Doff is at the H level and the display mode is designated, the ON signal Von has the logic level inverted from that of the clock signal CLK, that is, the OFF signal Voff and the common signal Vcom. Therefore, as in the first embodiment, each pixel 110 is turned off or turned on according to the data bits held in the memory circuit 150.
On the other hand, in the second embodiment, when the signal / Doff is at the L level and the off mode is designated, the clock signal CLK is directly used as the off signal Voff and the common signal Vcom. As shown in FIG. 7, the signal Vcom is logically inverted every frame period F without being fixed at the L level.
However, when the off mode is designated, the on signal Von is changed to the same logical relationship as the off signal Voff and the common signal Vcom, so that each pixel 110 has a memory as in the first embodiment. Regardless of the data bits held in the circuit 150, the display is forcibly turned off.

  According to the second embodiment, the clock signal CLK is supplied as it is to the display area as the off signal Voff (common signal Vcom), so that a buffer circuit for outputting the off signal Voff (common signal Vcom) becomes unnecessary. Accordingly, the circuit area can be reduced.

  By the way, the off signal Voff and the common signal Vcom are fixed to Vdd, for example, and when the display mode is designated, the on signal Von is alternately changed between 0 volt and 2 Vdd, while the off mode is designated. In this case, the same effect as that of the second embodiment can be obtained in that the buffer circuit for outputting the off signal Voff (common signal Vcom) is not required even if the on signal Von is fixed at Vdd. It is possible. However, in this configuration, in addition to 0 volts (Gnd) and Vdd as the voltage, 2 Vdd is required, so it is necessary to note that the configuration of the power supply circuit is somewhat complicated.

In the first and second embodiments described above, the drive voltage generation circuit 50 is formed on the element substrate. However, the drive voltage generation circuit 50 may be formed outside the element substrate (that is, externally attached).
In the above description, the pixel 110 can only perform binary display of ON display or OFF display according to the data bit, but one pixel is expressed by a plurality of subpixels having the same configuration as the pixel 110 described above. In addition, one pixel may be displayed in grayscale according to the number (area) of ON display (or OFF display) of the plurality of subpixels. Furthermore, the pixel 110 may be turned on / off for each color so as to correspond to the three primary colors RGBRGB, for example, in the X direction, or may be configured to perform color display in combination with the area gradation. good.
In the embodiment or the like, when the clock signal CLK whose level is inverted in the cycle of the frame period F is input, the off signal Voff (common signal Vcom) is supplied to the display area 100, and the display mode is designated. The ON signal Von is inverted from the logic level of the OFF signal Voff (common signal Vcom). The reason is merely to drive the liquid crystal element 180 by alternating current. For this reason, for example, the clock signal CLK may be configured to invert the level at a period of, for example, two frame periods or more, or at another fixed period.
Further, although the liquid crystal element 180 is in the normally white mode, it may be in a normally black mode in which the liquid crystal element 180 becomes dark when no voltage is applied. When the normally black mode is selected, in the off mode, all pixels are black, which is off display.

  In addition, the present invention is not limited to the transmission type, and may be a reflection type or a semi-transmission semi-reflection type intermediate between the two. Furthermore, in addition to the TN type, a dye (guest) having anisotropy in absorption of visible light in the major axis direction and the minor axis direction of the molecule, such as STN type, is dissolved in a liquid crystal (host) having a certain molecular arrangement. Alternatively, a guest-host type liquid crystal in which dye molecules are arranged in parallel with liquid crystal molecules may be used. In addition, the liquid crystal molecules are aligned vertically with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned horizontally with respect to both substrates when voltage is applied. Also, a so-called IPS (including in-plane switching method and FSS) method may be used.

<Electronic equipment>
Next, an electronic apparatus having the electro-optical device 10 according to the above-described embodiment as a display device will be described. FIG. 8 is a diagram illustrating a configuration of a mobile phone 1200 using the electro-optical device 10 according to the embodiment.
As shown in this figure, the mobile phone 1200 includes a plurality of operation buttons 1202, the earpiece 1204 and the mouthpiece 1206, and the display area 100 of the electro-optical device 10 described above. Note that components of the electro-optical device 10 other than the display area 100 do not appear as appearance.

  As an electronic apparatus to which the electro-optical device 10 is applied, in addition to the mobile phone shown in FIG. 8, a digital still camera, a notebook personal computer, a liquid crystal television, a viewfinder type (or a monitor direct view type) video recorder. , Car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, devices equipped with touch panels, and the like. Needless to say, the above-described electro-optical device 1 is applicable as a display device of these various electronic devices. In any electronic device, the electro-optical device 10 can benefit from low power consumption.

1 is a block diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. It is a figure which shows the structure of the drive voltage generation circuit in the same electro-optical apparatus. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. FIG. 6 is a diagram illustrating an operation in the electro-optical device. FIG. 6 is a block diagram illustrating a configuration of an electro-optical device according to a second embodiment of the invention. It is a figure which shows the structure of the ON signal production | generation circuit in the same electro-optical apparatus. FIG. 6 is a diagram illustrating an operation in the electro-optical device. It is a figure which shows the structure of the mobile telephone to which the electro-optical apparatus which concerns on embodiment is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 20 ... Y address decoder, 30 ... X address decoder, 40 ... Sample hold circuit, 50 ... Drive voltage generation circuit, 60 ... On signal generation circuit, 100 ... Display area, 110 ... Pixel, 150 ... Memory circuit, 160 ... selection circuit, 180 ... liquid crystal element, 181 ... pixel electrode, 183 ... liquid crystal, 185 ... common electrode, 1200 ... mobile phone

Claims (7)

A plurality of pixels;
A common electrode that is common to the plurality of pixels and to which a common signal having a predetermined voltage is applied;
The pixel is
A memory circuit holding one bit;
When the one-bit logic level held in the memory circuit is one, the OFF signal having the same voltage as the common signal is selected, and when the held one-bit logic level is the other A selection circuit for selecting the ON signal of
A pixel electrode facing the common electrode and applied with an on signal or an off signal selected by the selection circuit;
A method for driving an electro-optical device comprising:
There is a first mode in which display is performed on the pixel based on one bit held by the memory circuit, and a second mode in which the pixel is turned off regardless of the one bit held by the memory circuit. And
When the first mode is designated, the on signal is set to a voltage different from the common signal,
When the second mode is designated, the ON signal is set to the same voltage as the common signal. When the first mode is designated,
For the common signal and the off signal, the logic level is inverted at a constant cycle,
The driving method of the electro-optical device according to claim 1, wherein the logic level of the common signal and the off signal is inverted for the on signal. When the second mode is designated,
The method of driving an electro-optical device according to claim 2, wherein the common signal and the off signal are fixed to one of logic levels. When the second mode is designated,
For the common signal and the off signal, the logic level is inverted at a constant cycle,
For the ON signal, the same logic level as the common signal and the OFF signal,
The method of driving an electro-optical device according to claim 2. A plurality of pixels each having a memory circuit holding one bit;
A common electrode that is common across the plurality of pixels and to which a common signal of a predetermined voltage is applied;
While outputting an off signal of the same voltage as the common signal,
When the first mode for displaying each pixel based on one bit held by the memory circuit is designated, an ON signal having a voltage different from the common signal is output.
A drive voltage generation circuit that outputs the on signal at the same voltage as the common signal when the second mode for displaying the pixel in an off state is specified regardless of the one bit held by the memory circuit;
With
The pixel is
A memory circuit holding one bit;
Selection to select the off signal when the one-bit logic level held in the memory circuit is one, and to select the on-signal when the one-bit logic level held is the other Circuit,
A pixel electrode facing the common electrode and applied with an on signal or an off signal selected by the selection circuit;
An electro-optical device comprising: The pixel is
Provided corresponding to the intersection of a plurality of word lines and a plurality of bit lines,
The electro-optical device according to claim 5, wherein a pixel corresponding to the selected word line among the plurality of word lines holds one bit supplied to a bit line corresponding to the pixel. An electronic apparatus comprising the electro-optical device according to claim 5.

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