JP4747805B2 - Electro-optical device, driving method, and electronic apparatus - Google Patents

Description

  The present invention relates to a technique for reducing power consumption of an electro-optical device having a memory circuit for each pixel.

Since portable electronic devices are required to be thinner and lighter, electro-optical devices such as liquid crystal elements and organic EL elements suitable for this requirement are used in electro-optical devices used as display devices for electronic devices. Used. Here, since this type of electro-optical device rewrites (refreshes) the state of each pixel for each frame regardless of the display content, power is consumed by the drive circuit for driving each pixel and its control circuit. Therefore, there was a factor that hindered low power consumption.
Therefore, a technique has been proposed in which a static memory circuit that stores 1 bit for each pixel is incorporated, and pixels are turned on or off in accordance with the bits stored in the memory circuit (see Patent Document 1).
In this technique, refreshing of the memory circuit is not required, so that if a still image is displayed, it is not necessary to operate the drive circuit and the like, and accordingly, power consumption can be reduced.
Japanese Patent Publication No. 3-5724

By the way, an electro-optical device using such an electro-optical element originally has low power consumption. However, in recent electronic devices, the electro-optical device has various reasons such as an extended continuous use time and a reduction in battery size. There is also a strong demand for further lower power consumption of a single unit.
The present invention has been made in view of the above-described circumstances, and an object thereof is to provide an electro-optical device, a driving method thereof, and an electronic apparatus that can further reduce power consumption in a configuration having a memory circuit for each pixel. Is to provide.

In order to solve the above-described problem, the present invention provides a plurality of pixels, a common electrode that is common to the plurality of pixels, to which an off signal for turning off the pixels is applied, and the off signal. An on signal generation circuit that generates an on signal that is delayed and inverts the logic level of the off signal, and wherein the pixel is held in the memory circuit and a memory circuit that holds 1 bit When the 1-bit logic level is one, the ON signal is selected, and when the logic level is the other, the selection circuit that selects the OFF signal, and the ON signal selected by the selection circuit or And a pixel electrode facing the common electrode to which an off signal is applied. In the present invention, since the ON signal is delayed with respect to the OFF signal and the logic level is inverted, the current consumed when the ON signal is applied to the pixel electrode can be reduced. Become.
Here, in the present invention, the on signal generation circuit is formed on the same substrate together with the memory circuit and the selection circuit in the pixel, and the off signal is supplied to the substrate from the outside. preferable.

In this configuration, the ON signal generation circuit is a cascade connection of a plurality of stages of NOT circuits, and each of the NOT circuits includes a P-channel type and an N-channel type thin film transistor, and among the plurality of stages, In some stages, the channel length of one of the channel-type thin film transistors may be larger than the channel length of the other channel-type transistor.
In this configuration, the plurality of pixels are arranged in a matrix in the horizontal direction and the vertical direction, and the signal lines for supplying the ON signal are adjacent to the two rows adjacent to the horizontal direction or the vertical direction. In addition, the matrix arrangement of the plurality of pixels is a repetition of a basic pattern of four pixels in two rows adjacent in the horizontal direction and two columns adjacent in the vertical direction. Also good.
Further, in this configuration, the plurality of pixels are arranged in a matrix form in a horizontal direction and a vertical direction, and signal lines for supplying the ON signals are arranged corresponding to the matrix arrangement of the pixels, and the pixels May be connected to output terminals of buffer circuits or NOT circuits respectively arranged at the four corners of the matrix arrangement.
The present invention can be conceptualized not only as an electro-optical device, but also as a driving method of the electro-optical device, and further as an electronic apparatus having the electro-optical device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a first embodiment of the present invention will be described. The electro-optical device according to the first embodiment is a liquid crystal device having a liquid crystal element as an electro-optical element, in which an element substrate on which various transistors and pixel electrodes are formed and a counter substrate on which a common electrode is formed are mutually connected. The electrode is formed with a certain gap so that the electrode forming surfaces face each other, and a TN (twisted nematic) type liquid crystal is sandwiched between the gaps.

FIG. 1 is a block diagram showing an electrical configuration of the electro-optical device 10.
As shown in this figure, in the display region 100 of the electro-optical device 10, 240 word lines 121 each extend in the row (X) direction, while 320 sets of bit lines 131 and complementary bit lines 132 exist. , Each extending in the column (Y) direction. The pixels 110 are provided corresponding to the intersections of the 240 word lines 121 and the 320 bit lines 131 (complementary bit lines 132). For this reason, in the present embodiment, the pixels 110 are arranged in a matrix of 240 rows × 320 columns, but the present invention is not limited to this arrangement.

The Y address decoder 20 exclusively outputs an H level row selection signal to the word line 121 of the row designated by the Y address Ady supplied from the upper control circuit (not shown).
For convenience, in the display area 100, row selection signals supplied to the word lines 121 in the first, second, third,..., 240th rows from the top are denoted as S1, S2, S3,. is doing. In addition, when the row selection signal is generally described without particularly specifying a row, it is expressed as Si. Here, i is an integer satisfying 1 ≦ i ≦ 240. The Y address Ady is shown as a single line in the figure, but is actually composed of 8 (2 ⁸ = 256 ≧ 240) signal lines.

On the other hand, the X address decoder 30 exclusively outputs the column selection signals X1, X2, X3,..., X320 corresponding to the column specified by the X address Adx supplied from the upper control circuit as the H level. . Note that the column selection signal is expressed as Xj when it is generally described without specifying a column. Here, j is an integer satisfying 1 ≦ j ≦ 320.
The sample and hold circuit 40 samples and supplies the data bit Da supplied from the upper control circuit to the bit line 131 of the j-th column when the column selection signal Xj of a certain column becomes H level, A bit obtained by inverting the logic of the data bit Da is supplied to the complementary bit line 132 in the j-th column. The sample and hold circuit 40 sets the bit line 131 and the complementary bit line 132 to the H level or the high impedance state for the column corresponding to the L level column selection signal.
For convenience, the bits supplied to the bit lines 131 in the first, second, third,..., 320 columns in the display area 100 from the left are denoted as D1, D2, D3,. Inverted bits supplied to the complementary bit lines 132 are denoted as / D1, / D2, / D3,..., / D320, and are denoted as Dj and / Dj when generally described without specifying a column. The X address Adx is shown by one line in the figure, but when only one bit is designated by one address as described above, it is constituted by ^nine (2 ⁹ = 512 ≧ 320) signal lines. .

The delay circuit 50 and the NOT circuit (inverter) 60 are both formed on the element substrate. Among these, the delay circuit 50 delays the signal Vcom supplied from the external circuit to the element substrate by a time Td. The circuit 60 inverts the logic level of the delayed signal Vcom and outputs the inverted signal as the ON signal Von. Therefore, both the delay circuit 50 and the NOT circuit 60 function as an ON signal generation circuit.
Note that the signal Vcom is supplied as it is as the off signal Voff in the display region 100. Further, the signal Vcom supplied to the element substrate is guided to the counter substrate via a conductive material or the like and applied to the common electrode 185.

  In the present embodiment, as shown in FIG. 3, the signal Von is inverted in polarity every frame (denoted as 1F, approximately 16.7 milliseconds, corresponding to the reciprocal of 60 Hz). The H level of the signal Von corresponds to the power supply voltage Vdd, and the L level corresponds to the ground potential Gnd. Since the delay circuit 50 and the NOT circuit 60 also use the voltage (Vdd−Gnd) as a power source, the H level of the signal Von corresponds to the voltage Vdd and the L level corresponds to the ground potential Gnd.

  Next, details of the pixel 110 will be described. Each pixel 110 is structurally identical to each other, and therefore will be described by using the pixel 110 located in i row and j column as a representative. FIG. 2 is a circuit diagram illustrating a configuration of the pixel 110 in i row and j column.

As shown in FIG. 2, the pixel 110 includes a static memory circuit 150, a selection circuit 160, and a liquid crystal element 180.
Among these, the memory circuit 150 includes n-channel TFTs (thin film transistors) 151 and 152 and NOT circuits 155 and 156. Regarding the TFT 151, its source is connected to the bit line 131 in the j-th column, its drain is connected to the input terminal of the NOT circuit 155, and its gate is connected to the i-th word line 121. The output terminal of the NOT circuit 155 is connected to the input terminal of the NOT circuit 156, and the output terminal of the NOT circuit 156 is fed back to the input terminal of the NOT circuit 155.
Since the memory circuit 150 is a complementary type, the source of the TFT 152 is connected to the complementary bit line 132 in the j-th column, the drain is connected to the input terminal of the NOT circuit 156, and the gate is the i-th row. Are connected to the word line 121.

Therefore, in the memory circuit 150, when the row selection signal Si supplied to the word line 121 becomes H level, the TFTs 151 and 152 are turned on and the bit Dj supplied to the bit line 131 is stored at the terminal Q ( The inverted bit / Dj supplied to the complementary bit line 132 is stored at the terminal / Q), and the stored contents are retained even when the row selection signal Si becomes L level and the TFTs 151 and 152 are turned on thereafter. It becomes the composition to be done.
Even when the row selection signal Si supplied to the word line 121 becomes H level, if both the bit line 131 and the complementary bit line 132 are at H level or in a high impedance state, the stored contents are not rewritten. Absent.

The selection circuit 160 includes transmission gates 162 and 164. Here, the input end of the transmission gate 162 is connected to the signal line 141 to which the signal Von is supplied, while the input end of the transmission gate 164 is connected to the signal line 142 to which the signal Voff is supplied. The output terminal 164 is commonly connected to pixel electrodes 181 formed individually for each pixel.
Also, the control gate of transmission gate 162 and the inversion control gate of transmission gate 164 are connected to terminal Q in memory circuit 150, while the inversion control gate of transmission gate 162 and the control gate of transmission gate 164 are in memory circuit 150. Connected to terminal / Q.
Therefore, if the terminal Q is at the H level (if the terminal / Q is at the L level), the transmission gates 162 and 164 are turned on and off, respectively, and the signal Von is applied to the pixel electrode 181 while the terminal Q Is at the L level (when the terminal / Q is at the H level), the transmission gates 162 and 164 are turned off and on, respectively, and the signal Voff is applied to the pixel electrode 181.

The liquid crystal element 180 has a configuration in which a TN liquid crystal 183 is sandwiched between an individual pixel electrode 181 for each pixel and a common electrode 185 common to all the pixels.
Although not particularly illustrated, each opposing surface of both substrates is provided with an alignment film that is rubbed so that the major axis direction of the liquid crystal molecules is continuously twisted, for example, by about 90 degrees between the two substrates. A polarizer corresponding to the orientation direction is provided on each back side of both substrates. For this reason, the light passing between the pixel electrode 181 and the common electrode 185 rotates about 90 degrees along the twist of the liquid crystal molecules if the voltage effective value between the two electrodes is zero, while the voltage effective value As is increased, the liquid crystal molecules are tilted in the direction of the electric field, and as a result, their optical rotation disappears. For this reason, for example, in the transmission type, when the polarizer is disposed on the incident side and the back side so that the polarization axes coincide with the alignment direction, the light transmittance increases if the voltage effective value is small, If the effective voltage value is large, the transmittance is low (normally white mode).

  In the present embodiment, the constituent elements in the Y address decoder 20, the X address decoder 30, the sample and hold circuit 40, the delay circuit 50, and the NOT circuit 60 are the constituent elements (memory circuit 150, It is formed by a polysilicon process common to the selection circuit 160).

Next, the operation of the electro-optical device 10 according to this embodiment will be described.
First, since the electro-optical device 10 is based on the premise that the data bits are stored in the memory circuit 150 of each pixel 110, the operation of storing the data bits in the memory circuit 150 will be described.
Here, for example, when data bits are stored in the pixel 110 in the i-th row and j-th column, the upper control circuit outputs the X-address Adx specifying the j-th column together with the Y-address Ady specifying the i-th row, The data bit Da to be stored in the pixel 110 in the i row and j column is output.

  The X address decoder 30 sets the column selection signal Xj to the H level by the X address Adx output in this way. As a result, the sample and hold circuit 40 samples the data bit Da to be stored, as a bit Dj for the bit line 131 corresponding to the j-th column, and for the complementary bit line 132 corresponding to the j-th column. These are supplied as inverted bits / Dj. The bit lines 131 and the complementary bit lines 132 other than the j-th column are in the H level or high impedance state.

On the other hand, the Y address decoder 20 sets only the row selection signal Si to the H level by the Y address Ady designating the i-th row.
In the pixel 110 in the i row and j column, since the row selection signal Si becomes H level, the TFTs 151 and 152 are turned on, and the bit Dj supplied to the bit line 131 is supplied to the terminal Q and the complementary bit line 132. The inverted bits / Dj are written to the terminals / Q, respectively.
In this state, when the row selection signal Si becomes L level, in the pixel 110 in the i row and j column, the TFTs 151 and 152 are turned off, the terminal Q in the memory circuit 150 is from the bit line 131, and the terminal / Q is the complementary bit. Although electrically disconnected from each line 132, the memory circuit 150 will continue to hold the written bits.

Immediately after the power is turned on, such a writing operation is performed on all the pixels 110, and thereby, either the H or L level data bit is held in the memory circuit 150 in all the pixels. The
When the display content is changed, the data bit Da that defines the display content after the change is supplied from the upper control circuit together with the X address Adx and the Y address Ady, and is designated by the X address Adx and the Y address Ady. The data bits held in the memory circuit 150 in the selected pixel are rewritten.

Next, a description will be given from the viewpoint of what happens to the liquid crystal element 180 when data bits are held in the respective pixels 110 as described above.
First, in the memory circuit 150 of the pixel 110, when the L level data bit is held at the terminal Q (when the H level is held at the terminal / Q), the transmission gates 162 and 164 are turned off and on, respectively. A signal Voff having the same logical relationship as the signal Vcom applied to the common electrode 185 is applied to the pixel electrode 181 of the pixel. Therefore, the voltage VLC applied to the liquid crystal element 180, here, the voltage obtained by subtracting the potential of the common electrode 185 from the potential of the pixel electrode 181 becomes zero as shown in FIG. If so, the pixel is in a bright off state.

On the other hand, in the memory circuit 150, when the H level data bit is held at the terminal Q (when the L level is held at the terminal / Q), the transmission gates 162 and 164 are turned on and off, respectively. A signal Von is applied to the pixel electrode 181.
Here, as shown in FIG. 3, the signal Von is a signal that is delayed by a time Td with respect to the signal Vcom applied to the common electrode 185 and has a logic inversion relationship.
For this reason, the voltage VLC applied to the liquid crystal element 180 has the same potential until the time Td elapses from the timing when the logic level of the signal Von changes, and becomes + Vdd or −Vdd after the time Td elapses.
Here, the period of one frame (1F) is about 16.7 milliseconds as described above, whereas in the present embodiment, the delay time Td is about 100 microseconds. Therefore, since the time Td is sufficiently short with respect to the period of one frame, when an H level data bit is held at the terminal Q, the effective voltage value of the liquid crystal element 180 is approximately Vdd, which is normally white mode. If there is, the pixel is in a dark ON state.

By the way, generally, when the electrodes of the charged capacitor are short-circuited, the electric charge is discharged and the voltage between the two terminals becomes zero, but at this time, external energy is unnecessary. When an H level data bit is held at the terminal Q, the voltage VLC in the liquid crystal element 180 becomes the same potential until the time Td elapses from the timing at which the logic level of the signal Von changes, and the pixel electrode 181 and the common electrode 185 Can be regarded as being short-circuited, so that the energy required for the discharge becomes unnecessary. For this reason, in this embodiment, immediately after the time Td elapses in one frame, only the amount of work corresponding to the change to the voltage −Vdd (or voltage + Vdd) is required for the liquid crystal element 180.
On the other hand, considering the configuration in which the signal Von is not delayed by merely inverting the logic level of the signal Vcom (signal Voff), the liquid crystal element charged to the voltage + Vdd is reversed to the voltage -Vdd having the opposite polarity in one frame. Therefore, the amount of work corresponding to the change to the voltage of 2Vdd is required for charging the liquid crystal element charged to the voltage -Vdd to charge the voltage + Vdd.
Therefore, in this embodiment, by delaying the signal Von, it is possible to halve the power consumption due to charging / discharging of the liquid crystal as compared with a configuration in which the signal Von is not delayed.

Here, in the electro-optical device 10, when the delay time Td is changed, what is the current consumption I in the standby state (the state where the writing operation to the memory of the pixel portion is stopped and still images are displayed). Whether or not to change will be described with reference to FIG.
In the electro-optical device 10, current is consumed by capacitances parasitic on the Von and Voff signal lines, and the current consumed by these portions is indicated by the consumption current Ioff when all the pixels are turned off. Therefore, when all the pixels are turned on, the current consumed only by charging / discharging of the liquid crystal element 180 is the current consumption Ion when all the pixels are turned on in FIG. 4 when all the pixels are turned off. The current consumption Ioff is subtracted.
As can be seen from the figure, if the delay time Td is set to 50 microseconds or more, the current consumption due to charging / discharging of the liquid crystal can be halved compared to the case where the delay time is zero.
In practice, the optimum value of the delay time Td varies depending on various conditions, but is determined by the time constant of the capacitance in the liquid crystal element 180 and the resistance parasitic on the wiring.
Further, FIG. 4 shows a result when the period of one frame is set to 1/10 of the normal period (the frame frequency is 600 times 600 Hz) so that the current consumption can be easily measured.

  Next, a configuration example of the delay circuit 50 will be described. The delay circuit 50 has a configuration in which a plurality of NOT circuit stages formed on an element substrate by a low-temperature polysilicon process are connected in cascade (cascade). FIG. 5A and FIG. 5B are diagrams showing the configuration of six basic units of the plurality of NOT circuits. As shown in these drawings, six NOT circuits 51 to 56 are connected in cascade so that an output of a certain stage becomes an input of the next stage. The NOT circuit of each stage includes a P-channel TFT, N-channel TFT. Here, for example, in the NOT circuit 51, the source of the P-channel TFT 51p is connected to the power supply line of the high voltage Vdd of the power supply, while the source of the N-channel TFT 51n is grounded to the reference potential Gnd, and the TFT 51p, A common gate 51n serves as an input terminal, and a common drain serves as an output terminal. The other NOT circuits 52 to 56 have the same structure.

FIG. 5C is a table showing the channel width Wp and channel length Lp of these TFTs 51p to 56p in the upper stage, the channel width Wn and channel length Ln of the TFTs 51n to 56n in the lower stage, and the unit in μm. is there.
A TFT manufactured by a low-temperature polysilicon process has a poor response compared to a monolithic IC transistor. However, a delay generated by the poor response is used as a delay circuit.
As shown in FIG. 5C, the channel length of the TFT 51n in the NOT circuit 51 and the TFT 54n in the NOT circuit 54 is 200 μm, and is extremely longer than 4 μm in the channel length of other TFTs. Designed.

In such a designed configuration, output waveforms at the input In of the NOT circuit 51, the outputs of the NOT circuits 51 to 55 (inputs of the NOT circuits 52 to 56) F1 to F5, and the output Out of the NOT circuit 56 are shown in FIG. As shown in Specifically, the TFTs 51n and 54n having long channel lengths are inferior to other TFTs in the characteristics from off to on, but the TFTs 51p and 54p have the same channel size as the other TFTs. , 54, only the rise time when changing from the L level to the H level becomes longer.
On the other hand, the output waveforms in the NOT circuits 52, 53, 55, and 56 have substantially the same rise time when changing from L level to H level and fall time when changing from H level to L level. Since it is sufficiently short, it functions as a simple waveform shaping circuit.

For this reason, the output Out is obtained by delaying the input In with the delay time Tdr at the rising time and the delay time Tdf at the falling time being substantially equal.
Here, when one of the delay times Tdr and Tdf is generated on one of the P and N channels and the other of the delay times Tdr and Tdf is generated on the other of the P and N channels, the P or N channel TFT When manufacturing variations occur, the delay times Tdr and Tdf cannot be maintained at the same value. Here, if the delay times Tdr and Tdf are not equal, a direct current component is applied to the liquid crystal element 180 and the liquid crystal 183 is deteriorated.
On the other hand, in the configuration shown in FIG. 5B, as shown in FIG. 5C, among the P and N channel type TFTs, the channel size of a part of the N channel type TFTs (in particular, Since only the channel length is changed, even if a manufacturing variation occurs in a P or N channel TFT, the influence acts in the same direction, so that the delay times Tdr and Tdf are shifted from the design values. Although there is, it is possible to keep both values almost the same.

When each part TFT is manufactured by a low-temperature silicon process so that the power supply voltage (Vdd−Gnd) is 3 V and the off-leakage of the entire electro-optical device 10 is suppressed to about 1 μA, the configuration shown in FIG. When the channel size is defined as shown in (c), a delay time of approximately 2 microseconds can be generated. For this reason, in order to generate a delay time of about 100 microseconds, it is only necessary to cascade about 50 configurations (300 stages of NOT circuits) as shown in FIGS. 5 (a) and 5 (b).
Even if a plurality of NOT circuits are not cascaded as described above, a delay of about 100 microseconds can be generated even by a configuration in which a logical inversion signal of the signal Vcom is delayed by a shift register, for example. A separate clock signal is required to control the register, and if this clock signal is supplied to the electro-optical device, power that is wasted due to parasitic capacitance may not be negligible. There is.

Meanwhile, the signal Voff may be the signal Vcom supplied from the outside as it is, whereas the signal Von needs to be generated by the delay circuit 50 and the NOT circuit 60 formed on the element substrate. For this reason, it can be said that a smaller load on the signal line 141 to which the signal Von is supplied is desirable.
Therefore, a second embodiment in which the load on the signal line 141 is reduced will be described. FIG. 7 is a diagram illustrating a configuration of an electro-optical device according to the second embodiment of the invention.
In the first embodiment shown in FIG. 1, the signal lines 141 in one row are shared by the pixels 110 in one row, but in the second embodiment shown in FIG. 7, the pixels 110 in two rows are used. In this configuration, one row of signal lines 141 is shared. For this reason, in the second embodiment, the two pixels 110 arranged across the signal line 141 are arranged symmetrically with respect to the signal line 141.

  The shape of the pixel 110 will be described with reference to the drawings. FIG. 8 is a plan view illustrating the configuration of the pixel 110, and FIG. 9 is a diagram illustrating the electrical equivalent circuit of FIG. In either case, a configuration of a total of four pixels of 2 × 2 corresponding to the intersection of the i row and the (i + 1) row adjacent thereto, the j column and the (j + 1) column adjacent thereto is shown. Here, i and (i + 1) are integers of 1 to 240, and j and (j + 1) are integers of 1 to 320.

In FIG. 8, a range 110a indicated by an alternate long and short dash line corresponds to a pixel 110 of i rows and j columns, and this rectangular range 110a is defined based on the signal line 141 (in the rectangular region indicating the range 110a, in the X direction). (The base portion along the base line) is folded downward and corresponds to the pixel 110 in (i + 1) rows and j columns. A range 110a corresponding to the pixel 110 in the i-th row and j-th column is folded back to the right (based on the right side along the Y direction) and corresponds to the pixel 110 in the i-th row (j + 1) column. Further, what is rotated 180 degrees around the lower right end of the range 110a corresponding to i row and j column corresponds to the pixel 110 in the (i + 1) row (j + 1) column.
Therefore, in the second embodiment, in the display area 100, these four pixels form a basic pattern, and the pixels 110 are arranged in the X direction and the Y direction.

Here, in FIG. 8, the polysilicon layer of the TFT is formed in an island shape on the element substrate, and a word line 121 is formed thereon by patterning the gate electrode layer via a first interlayer insulating film (not shown). In addition, the signal lines 141 and 142, the power supply voltage Vdd, and the power supply line of the ground potential Gnd are formed, and the bit line 131 and the complementary bit line are formed by patterning the aluminum layer through the second interlayer insulating film (not shown). 132, a wiring layer such as an auxiliary wiring is formed. Further, in FIG. 8, “x” marks are contact holes, which are conductive between different layers such as a polysilicon layer, a gate electrode layer, or an aluminum layer.
In practice, the pixel electrode 181 has a shape slightly smaller than the range 110a and is formed on the upper layer of the aluminum layer through an insulating film and conductive at the connection point Pix, but is omitted in FIG. ing. Further, the wiring corresponding to the aluminum layer in FIG. 8 is indicated by a thick line in the equivalent circuit of FIG.

  In the second embodiment, since the signal line 141 for supplying the signal Von is shared by two adjacent rows, the number of the signal lines 141 can be halved compared to the first embodiment. Accordingly, the capacitance parasitic on the signal line 141 is also halved, so that the driving capability of the delay circuit 50 and the NOT circuit 60 that generate the signal Von can be halved. For this reason, the area for forming the delay circuit 50 and the NOT circuit 60 on the element substrate can be reduced to about half, which can contribute to miniaturization.

Although the number of signal lines 142 that supply the signal Voff does not change, the signal Voff is supplied by, for example, a monolithic IC having a high driving capability from the outside, so that the parasitic capacitance of the signal line 142 is somewhat high. However, there is almost no effect.
In the example shown in FIG. 8, the source regions of the TFTs 151 and 152 in the pixel 110 in the i row and j column are the same as the TFTs 151 and 152 in the pixel 110 in the adjacent (i−1) row and j column. Shared with the source area. Similarly, the source regions of the TFTs 151 and 152 in the pixel 110 in the (i + 1) row and j column are shared with the source regions of the TFTs 151 and 152 in the adjacent pixel 110 in the (i + 2) row and j column (only a part is shown). . That is, the source regions of the TFTs 151 and 152 in the pixel 110 are in the same column and are shared with the source regions of the TFTs 151 and 152 in one of the two adjacent rows.
As a result, the parasitic capacitance of the bit line 131 (and the complementary bit line 132) is reduced, so that power consumption can be suppressed and the speed of writing bits (and inverted bits) into the memory circuit 150 can be improved. .

  In the second embodiment, the signal line 141 is shared by two adjacent rows, but may be shared by two adjacent columns. However, in the case of color display as an actual problem, there is often no space in the column direction because primary color pixels such as RGB are arranged in the Y direction, so the signal line 141 is shared by two adjacent rows. It is desirable to have a configuration that

In the first embodiment, the output signal of the delay circuit 50 is logically inverted by one NOT circuit 60 and output as the signal Von. However, since the signal Von is supplied to all the pixels 110, the NOT circuit If the driving capability of 60 is not set to be very high, the waveform and phase of the signal Von will differ from pixel to pixel, which may cause a difference in display.
Therefore, as shown in FIG. 10, outside the display area 100, the left end and the right end of all signal lines 141 are connected in common, and the signal Von is buffered at the four corners outside the display area 100. The buffer circuits 71, 72, 73, and 74 may be provided. Further, instead of one NOT circuit 60, in reality, as shown in FIG. 11, the logic of the output signal from the delay circuit 50 is negated by a circuit 70 in which a plurality of NOT circuits having sequentially increased driving capabilities are connected in cascade. It becomes composition.
Note that since the driving capability is proportional to the channel widths of the P-channel and N-channel transistors, in the circuit 70 shown in FIG. 11, the channel width W of the transistors constituting the NOT circuit at each stage is approximately three times as large. Designed to be wide.

In the configuration shown in FIG. 10, the delay and waveform dullness of the signal Von are made uniform for each pixel, and the driving capability is low up to the input terminals of the buffer circuits 71 to 74. The effect of noise is small.
In FIG. 10, the buffer circuits are arranged at the four corners outside the range of the display area 100. However, since the buffer circuit is substantially an even-numbered cascade connection of NOT circuits, the final-stage NOT circuit in this cascade connection is used. Alternatively, the circuit including the final stage may be arranged at the four corners.

In the first and second embodiments described above, the signal Vcom supplied from the outside is delayed by the delay circuit 50, and then the logic is inverted by the NOT circuit 60 (70) and output as the signal Von. The same result can be obtained even if the order of the delay and logic inversion is reversed. In other words, the signal Vcom may be delayed after being inverted.
In the above description, the pixel 110 can only perform binary display of ON display or OFF display according to the data bit, but one pixel is expressed by a plurality of subpixels having the same configuration as the pixel 110 described above. In addition, one pixel may be displayed in grayscale according to the number (area) of ON display (or OFF display) of the plurality of subpixels. Furthermore, the pixel 110 may be turned on / off for each color so as to correspond to the three primary colors RGBRGB, for example, in the X direction, or may be configured to perform color display in combination with the area gradation. good.
In the embodiment and the like, the signal Vcom whose level is inverted at a cycle of one frame is input. However, the reason for the level inversion of the signal Vcom is only for AC driving of the liquid crystal element 180. Therefore, for example, the level of the signal Vcom may be inverted at a period of 2 frames or more.
Further, although the liquid crystal element 180 is in the normally white mode, it may be in a normally black mode in which the liquid crystal element 180 becomes dark when no voltage is applied.

  In addition, the present invention is not limited to the transmission type, and may be a reflection type or a semi-transmission semi-reflection type intermediate between the two. Furthermore, in addition to the TN type, a dye (guest) having anisotropy in absorption of visible light in the major axis direction and the minor axis direction of the molecule, such as STN type, is dissolved in a liquid crystal (host) having a certain molecular arrangement. Alternatively, a guest-host type liquid crystal in which dye molecules are arranged in parallel with liquid crystal molecules may be used. In addition, the liquid crystal molecules are aligned vertically with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned horizontally with respect to both substrates when voltage is applied. Also, a so-called IPS (including in-plane switching method and FSS) method may be used.

<Electronic equipment>
Next, an electronic apparatus having the electro-optical device 10 according to the above-described embodiment as a display device will be described. FIG. 12 is a perspective view showing a configuration of a mobile phone 1200 using the electro-optical device 10 according to the embodiment.
As shown in this figure, the mobile phone 1200 includes a plurality of operation buttons 1202, the earpiece 1204 and the mouthpiece 1206, and the display area 100 of the electro-optical device 10 described above. Note that components of the electro-optical device 10 other than the display area 100 do not appear as appearance.

  In addition to the mobile phone shown in FIG. 12, the electronic apparatus to which the electro-optical device 10 is applied includes a digital still camera, a notebook computer, a liquid crystal television, and a viewfinder type (or monitor direct view type) video recorder. , Car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, devices equipped with touch panels, and the like. Needless to say, the above-described electro-optical device 1 is applicable as a display device of these various electronic devices. In any electronic device, the electro-optical device 10 can benefit from low power consumption.

1 is a block diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. FIG. 6 is a diagram illustrating a writing operation with respect to a liquid crystal element in the same electro-optical device. It is a figure which shows the relationship between the delay time and current consumption in the same electro-optical device. It is a figure which shows the structure of the delay circuit in the same electro-optical apparatus. It is a figure which shows operation | movement of the delay circuit. FIG. 6 is a block diagram illustrating a configuration of an electro-optical device according to a second embodiment of the invention. FIG. 3 is a plan view illustrating a configuration of a pixel in the electro-optical device. FIG. 3 is an equivalent circuit diagram of a pixel in the same electro-optical device. FIG. 10 is a block diagram illustrating a configuration of an electro-optical device according to a third embodiment of the invention. It is a figure which shows the structure of the NOT circuit of the same electro-optical apparatus. It is a figure which shows the structure of the mobile telephone to which the electro-optical apparatus which concerns on embodiment is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Electro-optical device, 20 ... Y address decoder, 30 ... X address decoder, 40 ... Sample hold circuit, 50 ... Delay circuit, 60 ... NOT circuit, 100 ... Display area, 110 ... Pixel, 150 ... Memory circuit, 160 ... selection circuit, 180 ... liquid crystal element, 181 ... pixel electrode, 183 ... liquid crystal, 185 ... common electrode, 1200 ... mobile phone

Claims (9)

A plurality of pixels;
A common electrode that is common to the plurality of pixels and to which an off signal is applied to turn off the pixels;
An on signal generation circuit that delays the off signal and generates an on signal obtained by inverting the logic level of the off signal;
Have
The pixel is
A memory circuit holding one bit;
A selection circuit that selects the ON signal when the one-bit logic level held in the memory circuit is one, and selects the OFF signal when the logic level is the other;
An on signal or an off signal selected by the selection circuit is applied, and a pixel electrode facing the common electrode;
An electro-optical device comprising: The on signal generation circuit is formed on the same substrate together with the memory circuit and the selection circuit in the pixel,
The electro-optical device according to claim 1, wherein the off signal is supplied from the outside to the substrate. The on signal generation circuit includes:
The electro-optical device according to claim 2, wherein a plurality of NOT circuits are connected in cascade. Each of the NOT circuits includes P-channel and N-channel thin film transistors,
4. The electro-optic according to claim 3, wherein, in some of the plurality of stages, a channel length of any one of the channel-type thin film transistors is larger than a channel length of the other channel-type transistor. apparatus. The plurality of pixels are arranged in a matrix in a horizontal direction and a vertical direction,
The electro-optical device according to claim 2, wherein the signal line that supplies the ON signal is shared in two rows adjacent in the horizontal direction or two columns adjacent in the vertical direction. The matrix arrangement in the plurality of pixels is:
The electro-optical device according to claim 5, wherein the repetition is performed with a basic pattern of four pixels in two rows adjacent in the horizontal direction and two columns adjacent in the vertical direction. The plurality of pixels are arranged in a matrix in a horizontal direction and a vertical direction,
The signal lines for supplying the ON signal are arranged corresponding to the matrix arrangement of the pixels and connected to the output terminals of the buffer circuit or the NOT circuit respectively arranged at the four corners of the pixel matrix arrangement. The electro-optical device according to claim 2. A plurality of pixels;
A common electrode that is common across the plurality of pixels and to which an off signal for displaying the pixels off is applied;
The pixel is
A memory circuit holding one bit;
A selection circuit that selects the ON signal when the one-bit logic level held in the memory circuit is one, and selects the OFF signal when the logic level is the other;
An on signal or an off signal selected by the selection circuit is applied, and a pixel electrode facing the common electrode;
A driving method of an electro-optical device having:
The electro-optical device driving method, wherein the off signal is delayed and the logic level of the off signal is inverted and supplied to the selection circuit as the on signal. An electronic apparatus comprising the electro-optical device according to claim 1.

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