JP4595695B2 - Electro-optical device, driving method, and electronic apparatus - Google Patents

Description

The present invention relates to a technique that enables gradation display in a configuration having a 1-bit memory circuit for each pixel.

Since portable electronic devices are required to be thin and light, electro-optical elements such as liquid crystal elements and organic EL elements suitable for this requirement are used for display devices of electronic devices. A display device using such an electro-optical element originally has low power consumption. However, in recent electronic devices, the display device itself is further reduced due to various reasons such as an extended continuous use time and a reduction in battery size. There is also a strong demand for power consumption.
On the other hand, this type of display device rewrites (refreshes) the state of each pixel every frame regardless of the display content, so that power is consumed by the drive circuit that drives each pixel, its control circuit, etc. There was a factor that hindered low power consumption.
Therefore, a technique has been proposed in which a static memory for storing one bit for each pixel is incorporated, and the pixel is turned on or off according to the bit stored in the memory (
Patent Document 1). In this technique, since refresh of the memory is unnecessary, if a still image is displayed, it is not necessary to operate a drive circuit or the like, and power consumption can be reduced correspondingly.

By the way, in this technique, since a pixel can be displayed only in a binary state of OFF or ON when viewed instantaneously, in the case of gradation display, one field period is divided into a plurality of subfield periods and one field is displayed. Among them, a driving method (subfield driving method) for controlling the ratio of the subfield period to be turned on is employed (see Patent Document 2).
JP 2002-297082 A (see FIG. 1) JP 2001-159883 A (refer to FIG. 7)

In the above subfield driving method, the number of times of writing a bit for instructing the pixel to be turned off or on is increased to the number of subfield divisions compared with the driving method in which the number of times of writing the bit is only once in one frame. The number of times of writing increases, which greatly hinders low power consumption.
In addition, there is no conceivable configuration in which digital data defining the gradation is stored and the pixels are displayed in gradation according to the area gradation according to the data. However, in this configuration, two static memories are provided for each pixel. It is necessary to incorporate more than one, and the configuration becomes extremely complicated.
As a practical matter, it is almost difficult to realize.
The present invention has been made in view of the above-described circumstances, and the object of the present invention is 1 per pixel.
An object of the present invention is to provide an electro-optical device, a driving method thereof, and an electronic apparatus that can perform gradation display in a configuration having a bit memory.

In order to solve the above-described problem, the present invention provides an electro-optical device having a plurality of pixels, wherein each pixel includes a first memory circuit that holds one bit, and a bit that is held in the first memory circuit. Of the gray level control signal supplied to the block to which the pixel belongs, among the gray level control signals supplied to each block in which the plurality of pixels are grouped. And when the bit has the other logic level, an electro-optic element that is turned on or off according to the bit, and the gradation control signal is assigned to the corresponding block. comprising a gray scale control signal output circuit for outputting the gray scale control signal output circuit stores data defining a gray scale including an intermediate gradation of the block, to hold until the change of the gradation When the logic level of the bit held in the first memory circuit is one, the electro-optic element has a gradation defined by the data stored in the second memory circuit. Thus, the gradation control signal is generated and output . According to this configuration, among the pixels included in the block, those having one of the logical levels of the bits held in the first memory circuit display the same gradation by the same gradation control signal.

In the present invention, before Kikaicho control signal, it is desirable in certain period is a logic signal which is a predetermined pulse width.
In the configuration in which the gradation control signal is a logic signal, when the logic level of the bit held in the first memory circuit is one, the gradation control signal is selected, while the logic level of the bit is the other A selection circuit for selecting and supplying to the electro-optic element a signal for turning on or off the electro-optic element according to a logic level of the gate circuit. It is good also as a structure which further has these.
Furthermore, the gate circuit is a NAND circuit having a four-transistor configuration, and the configuration can be simplified if two of the four transistors are shared by adjacent pixels. .

In the present invention, the gradation control signal is a signal in which a signal for turning on or off the electro-optic element is distributed at a predetermined rate in a predetermined period, and the logic of the bit held in the first memory circuit When the level is one, the gradation control signal is selected and supplied to the electro-optic element, while when the logic level of the bit is the other, a signal for turning on or off the electro-optic element A selection circuit that selects any one of them and supplies the selected electro-optical element to the electro-optical element may be used.
In the present invention, when the number of blocks is M and the number of gradations for gradation display is N, the number L of the second memory circuits included in the gradation control signal output circuit is L = M × It is desirable to satisfy the relationship of log ₂ N.

In the present invention, the pixel may be configured such that each block is defined for each primary color corresponding to at least three different primary colors, and each block is defined for each character display unit. It is good also as a composition.
In the present invention, the first or second memory circuit is preferably a static memory.
The present invention can be conceptualized not only as an electro-optical device, but also as a driving method of the electro-optical device, and further as an electronic apparatus having the electro-optical device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
First, the electro-optical device according to the first embodiment of the invention will be described. This electro-optical device is a liquid crystal device having a liquid crystal element as an electro-optical element, in which an element substrate on which various transistors and pixel electrodes are formed and a counter substrate on which a common electrode is formed are opposed to each other on their electrode formation surfaces. As described above, the TN (twisted nematic) type liquid crystal is sandwiched between the gaps while maintaining a certain gap.

FIG. 1 is a block diagram showing an electrical configuration of the electro-optical device 10.
As shown in this figure, in the display area 100 of the electro-optical device 10, 320 rows of word lines 311 each extend in the row (X) direction, while 720 (= 240 × 3) columns of bit lines 211. Are provided so as to extend in the column (Y) direction. The pixels 110 are provided corresponding to the intersections of 320 rows of word lines 311 and 720 columns of bit lines 211. Further, the pixels 110 are arranged in a vertical stripe shape so that the same column has the same color in the order of R (red), G (green), and B (blue) when viewed along the X direction. . Therefore, in the electro-optical device 10, one dot can be displayed in color by the three R, G, and B pixels 110 adjacent to each other in the X direction.

In the present embodiment, when viewed in units of pixels 110, the pixels are arranged in a matrix of 320 vertical rows by 720 horizontal columns, and in terms of display dots, they are arranged in 320 vertical rows by 240 horizontal columns.
The present invention is not intended to be limited to this arrangement. Further, three rows of RGB pixels constituting one dot are referred to as a dot row. Details of the pixel 110 will be described later.
On the other hand, the display area 100 has a signal Von for turning on the liquid crystal element, a signal Voff for turning off the liquid crystal element,
The signal Lcom supplied to the common electrode is supplied to each pixel 110 in common.
Although not shown in FIG. 1, the bit lines 211 provided for each column are provided with complementary bit lines on a one-to-one basis, and bits obtained by inverting the logic levels of the data bits supplied to the bit lines 211. Is configured to be supplied.

The Y address decoder 350 exclusively outputs an H level row selection signal to the word line 311 of the row designated by the Y address Ady. Here, in the present embodiment, the Y address decoder 350 uses a virtual 321st word line for gradation control in addition to the 320th word line 311 in the display area 100.
For the sake of convenience, the row selection signals supplied to the word lines 311 in the first, second, third,..., 320th rows from the top in the display area 100 are denoted as W1, W2, W3,. The row selection signal used for gradation control is denoted as W321.

The X address decoder 240 outputs any one of the sampling signals S1, S2, S3,..., S240 corresponding to the dot row designated by the X address Adx as an H level exclusively.
In principle, the sample and hold circuit 250 (when the row selection signal W321 is at the L level) is a dot column corresponding to the sampling signal that has become the H level, and includes three columns of R, G, and B bits. The data bits Dr, Dg, and Db are sampled and supplied to the line 211, while the other bit lines 211 are set to a high impedance state.
Here, the data bit Dr includes the row designated by the Y address Ady and the X address Adx.
Among the display dots corresponding to the intersection with the dot row specified in (1), 1-bit data to be stored in the R pixel 110. Similarly, the data bits Dg and Db are the same among the same display dots. , B data to be stored in the B pixel 110.

In exceptional cases (when the row selection signal W321 is at the H level), the sample and hold circuit 250 applies the gradation bit Q to the bit lines in the first to sixth columns corresponding to the first and second display dot columns.
r0, Qr1, Qg0, Qg1, Qb0 and Qb1 are supplied.
Here, the two bits of the gradation bits Qr0 and Qr1 define the gradation of the R pixel 110 that stores the H-level data bits. Similarly, the 2 bits of the gradation bits Qg0 and Qg1 define the gradation of the G pixel 110 storing the H level data bit, and the gradation bit Q
The two bits b0 and Qb1 define the gradation of the B pixel 110 that stores H level data bits.

Here, for the sake of convenience, in the display area 100, the bits supplied to the three bit lines 211 of R, G, and B constituting the j-th dot row from the left are respectively represented as Xrj, Xgj, X
Indicated as bj. Note that j is a symbol for generally indicating a row in which display dots are arranged, and is an integer satisfying 1 ≦ j ≦ 240.
Of these, bits Xr1, Xg1, Xb1, X corresponding to the first and second dot rows
For r2, Xg2, and Xb2, if the row selection signal W321 is at the H level, it is not a data bit that defines whether the pixel is on or off, but gradation bits Qr0, Qr1, Qg, respectively.
0, Qg1, Qb0, and Qb1.

The gradation control signal output circuit 450 outputs a gradation control signal Gr that defines the gradation of the R pixel 110 that stores H-level data bits according to the gradation signals P1, P0, etc., to the bit line 21.
1 is supplied to the gradation control line 213 paired with 1, and similarly, the G-level data bit storing the H level data bit is stored.
The gradation control signals Gg and Gb defining the gradation of the B and B pixels 110 are supplied to the gradation control line 213 paired with the bit line 211, respectively. Note that the gradation control signal output circuit 450
Details of this will be described later.
Further, the X address Adx, the Y address Ady, the data bits Dr, Dg, Db, the gradation bits Qr0, Qr1, Qg0, Qg1, Qb0, Qb1, and the gradation signals P1, P0 are respectively supplied from an upper control circuit (not shown). The

Next, details of the pixel 110 will be described. The pixels 110 are structurally identical to each other except that they correspond to the primary colors of R, G, and B, respectively. Therefore, the pixel 110 will be described as a representative of dots located in i rows and j columns and corresponding to one of the primary colors. FIG. 2 is a circuit diagram showing the configuration.
Note that i is a symbol for generally indicating an array row of display dots, and 1 ≦ i ≦ 320.
It is an integer that satisfies

As shown in FIG. 2, the pixel 110 includes a static memory circuit 120, a NAND
A circuit 130, a selection circuit 140, and a liquid crystal element 150 are included.
Among these, the memory circuit (first memory circuit) 120 includes n-channel TFTs (thin film transistors) 122 and 124 and NOT circuits 126 and 128. The TFT 122 has a source connected to the bit line 211, a drain connected to the input terminal of the NOT circuit 126, and a gate connected to the word line 311. The output terminal of the NOT circuit 126 is connected to the input terminal of the NOT circuit 128, and the output terminal of the NOT circuit 128 is connected to the NOT circuit 1.
26 is fed back to the input terminal. Therefore, in the memory circuit 120, when the row selection signal Wi supplied to the word line 311 becomes H level, the TFT 122 is turned on and the bit line 211 is turned on.
The bit Xj supplied to is held at the output terminal Q (i, j).
Since the memory circuit 120 is complementary, the TFT 124 has its source connected to the complementary bit line 212 and its drain connected to the input terminal of the NOT circuit 128.
The gate is connected to the word line 311.
Xj is a general notation for the bits Xrj, Xgj, and Xbj supplied to the bit line 211 of the column that constitutes the j-th dot column, without specifying the color, / Xj
Indicates the inverted logic level of the bit.

One input terminal of the NAND circuit 130 as a gate circuit is connected to the output terminal Q (
i, j), and the other input terminal is a gradation control line 213 to which a gradation control signal G # is supplied.
It is connected to the. Here, the gradation control signal G # is the R, G,
The gradation control signals Gr, Gg, and Gb supplied to the three B pixels are generally expressed without specifying colors. Therefore, # is any one of r, g, and b.
In other words, in the present embodiment, the pixel 110 is blocked for each primary color of R, G, and B, and different gradation control signals Gr, Gg, and Gb are supplied to each block. Yes.

The selection circuit 140 includes transmission gates 142 and 144 and a NAND circuit 13.
A NOT circuit 146 that logically inverts a negative logical product signal of 0 is provided. Here, the signal Von is supplied to the input terminal of the transmission gate 142, while the signal Voff is supplied to the input terminal of the transmission gate 144, so that the transmission gates 142, 14 are supplied.
The output terminals 4 are commonly connected to pixel electrodes 118 formed individually for each pixel.
Among these, the inversion control gate of the transmission gate 142 is the NAND circuit 130.
The forward rotation control gate of the transmission gate 142 is connected to the output terminal of NO.
It is connected to the output terminal of the T circuit 146. The normal control gate of the transmission gate 144 is connected to the output terminal of the NAND circuit 130, while the inversion control gate of the transmission gate 144 is connected to the output terminal of the NOT circuit 146.
Therefore, when the NAND signal by the NAND circuit 130 is at L level, only the transmission gate 142 is turned on and the signal Von is supplied to the pixel electrode 118, while when the NAND signal is at H level, the transmission is performed. Only the gate 144 is turned on, and the signal Voff is applied to the pixel electrode 118.

The liquid crystal element 150 has a configuration in which a TN liquid crystal 105 is sandwiched between an individual pixel electrode 118 for each pixel and a common electrode 108 common to all pixels. In the present embodiment, the common electrode 108 is applied with a signal Lcom whose polarity is inverted every frame (about every 16.7 milliseconds).
Although not particularly illustrated, each opposing surface of both substrates is provided with an alignment film that is rubbed so that the major axis direction of the liquid crystal molecules is continuously twisted, for example, by about 90 degrees between the two substrates. A polarizer corresponding to the orientation direction is provided on each back side of both substrates. For this reason, the light passing between the pixel electrode 118 and the common electrode 108 rotates about 90 degrees along the twist of the liquid crystal molecules if the voltage effective value between the two electrodes is zero, while the voltage effective value As is increased, the liquid crystal molecules are tilted in the direction of the electric field, and as a result, their optical rotation disappears. For this reason, for example, in a transmission type, when a polarizer is arranged on the incident side and the back side so that the polarization axes coincide with the alignment direction, the light transmittance is maximum if the effective voltage value is close to zero. On the other hand, the amount of transmitted light decreases as the effective voltage value increases, and the transmittance is finally minimized (normally white mode).

Here, when the signal Lcom applied to the common electrode 108 is inverted in polarity every frame (1F) as shown in FIG. 5, the signal Von for turning on the liquid crystal element 150 is the signal L
While com has a logic level inverted relationship, the signal Voff for turning off the liquid crystal element 150 has the same logic level as the signal Lcom.

Next, the gradation control signal output circuit 450 will be described. FIG. 3 is a block diagram showing the configuration of the gradation control signal output circuit 450.
In this figure, SRAMs (second memory circuits) 461 to 466 are row selection signals W321.
The data bit when the signal becomes H level is fetched, held and output. Specifically, the SRAM 461 takes in the bit Xr1 when the row selection signal W321 becomes H level, and continuously holds and outputs the fetched bit as Qr0 from its output terminal Q. Similarly, The SRAMs 462 to 466 fetch the bits Xg1, Xb1, Xr2, Xg2, and Xb2 when the row selection signal W321 becomes H level, and also fetch the fetched bits from each output terminal Q to Qr1, Qg0, Qg1, Qb0, and Qb1. Are held and output.

The comparison circuit 471 denoted as CMP in FIG. 3 outputs the gradation control signal Gr to the display area 1.
This is commonly supplied to the R pixel 110 at 00 via the gradation control line 213. Specifically, the comparison circuit 471 compares the logic level of the bit Qr0 output from the SRAM 461 and the logic level of the gradation signal P0, and when both are at the H level, or the bit output from the SRAM 462 When the logical level of Qr1 and the logical level of the gradation signal P1 are compared and both are at the H level, the gradation control signal Gr is set to the H level.
The comparison circuit 472 outputs the gradation control signal Gg to the G pixel 11 in the display area 100.
When the logic level of bit Qg0 and the logic level of gradation signal P0 are compared and both are at the H level, or the logic level of bit Qg1 and the gradation signal When both are at the H level by comparing with the logic level of P1, the gradation control signal Gg is set to the H level. Similarly, the comparison circuit 473 supplies the gradation control signal Gb to the B pixels 110 in the display region 100 in common, and compares the logic level of the bit Qb0 with the logic level of the gradation signal P0. If both are at the H level,
Alternatively, when the logic level of the bit Qb1 and the logic level of the gradation signal P1 are compared and both are at the H level, the gradation control signal Gb is set to the H level.

Note that the configurations of the comparison circuits 471, 472, and 473 are the same as each other, for example, as shown in FIG. That is, taking the comparison circuit 471 as an example, the input terminal D0
AND circuit 475 for obtaining a logical product signal of the logical signal (bit Qr0) supplied to the gray level signal P0, and a logical product signal of the logical signal (bit Qr1) supplied to the input terminal D1 and the gray level signal P1 AND circuit 476 for obtaining the logical sum signal of both logical product signals and the gradation control signal G
and an OR circuit 477 for outputting as r.

In this embodiment, the X address decoder 240 and the sample / hold circuit 2
50, the Y address decoder 350, the gradation control signal output circuit 450, and the constituent elements in the pixel 110 can all be formed simultaneously by a polysilicon process.

Next, the operation of the electro-optical device according to this embodiment will be described.
First, since the electro-optical device 10 is premised on a state in which data bits are stored in the memory circuit 120 of each pixel 110, the operation of storing data bits in the memory circuit 120 will be described.
In the present embodiment, the data bit storage operation for the memory circuit 120 is executed with three pixels of R, G, and B constituting a display dot as one unit. Here, for example, when storing data bits of three pixels of R, G, and B that constitute display rows of i rows and j columns, the upper control circuit
X address A for designating the j-th dot row together with Y address Ady for designating the i-th row
dx is output, and further data bits Dr, Dg, Db to be stored are output.

With this X address Adx, the X address decoder 240 sets the sampling signal Sj to the H level. As a result, the sample and hold circuit 250 samples the data bits Dr, Dg, and Db to be stored and applies the bits to the three bit lines 211 of R, G, and B constituting the j-th dot row, respectively. Supply as Xrj, Xgj, and Xbj. Note that the sample and hold circuit 250 logically inverts the data bits Dr, Dg, and Db to be stored, and applies them to the three complementary bit lines 212 of R, G, and B constituting the j-th dot row.
The operations of supplying data bits / Xrj, / Xgj, and / Xbj, respectively, are also executed.

On the other hand, the Y address decoder 350 sets only the row selection signal Wi to the H level by the Y address Ady specifying the i-th row. When the row selection signal Wi becomes H level, in the 720 pixels 110 located in the i-th row, the TFTs 122 and 124 are turned on, respectively. Among these, for the R pixel 110 corresponding to the j-th dot row, the bit Xrj is supplied to the bit line 211, so the bit Xrj is written by the memory circuit 120. For the G and B pixels 110 corresponding to the j-th dot row, bits Xgj,
Since Xbj is supplied, each bit is written by the memory circuit 120.
Of the pixels 110 located in the i-th row, those other than the j-th dot row are
Since the bit line 211 and the complementary bit line 212 are in a high impedance state, the TFTs 122 and 124 are turned on, but the data bits stored in the memory circuit 120 are not changed.
Even if the row selection signal Wi becomes L level, the written data bits are continuously held by the NOT circuits 126 and 128.

Immediately after the power is turned on, such a writing operation is executed for all of the display dots of 320 rows × 240 columns, and the memory circuits 120 of all the pixels 110
Either H or L level data bits are retained.
In addition, when the display contents are changed, R, G, B 3 constituting the display dot after the change
The pixel data bits Dr, Dg, and Db are supplied from the upper control circuit together with the X address Adx and the Y address Ady, and the data bits held in the memory circuit 120 are rewritten.

In the present embodiment, among the R, G, and B pixels 110, the SR in the gradation control signal output circuit 450 is used for gradation display of the pixels that hold the H-level data bits.
In AM461-466, gradation bits Qr0, Qr1, Qg0, Qg1, Qb0,
Since it is assumed that Qb1 is stored, the operation of storing gradation bits in the SRAMs 461 to 466 will be described.
In the present embodiment, the operation of storing the gradation bits in the SRAMs 461 to 466 is executed with a total of 6 bits, 2 bits each specifying the gradation for each of R, G, and B, as one unit. Gradation bit Qr
When 0, Qr1, Qg0, Qg1, Qb0, and Qb1 are stored, the upper control circuit outputs a Y address Ady specifying the 321st row together with these 6-bit gradation bits.

With this Y address Ady, the Y address decoder 350 sets only the row selection signal W321 to the H level. When the row selection signal W321 becomes H level, the sample and hold circuit 250 becomes an exceptional operation, so that the gradation bits Qr0, Qr1, Qg0, Qg1, Qb0
, Qb1 are supplied as bits Xr1, Xg1, Xb1, Xr2, Xg2, and Xb2 to a total of six bit lines 211 of R, G, and B constituting the first and second dot rows, respectively.

On the other hand, when the row selection signal W321 becomes H level, the SRA of the gradation control signal output circuit 450
M461 to 466 include bits Xr1, Xg1, Xb1, Xr2, Xg2, Xb, respectively.
2 (ie, gradation bits Qr0, Qr1, Qg0, Qg1, Qb0, Qb1) are written.
Immediately after the power is turned on, this write operation is executed and the gradation bits are stored in the SRAMs 461 to 467, respectively.
In addition, when changing the gradation of the R, G, and B pixels 110 storing the H-level data bits, a total of 6-bit levels that define the changed R, G, and B gradations, respectively. Key
Supplied from the host control circuit together with the Y address Ady defining the 321st row, the SRAM
The gradation bits held in 461 to 466 are rewritten.

Incidentally, when the waveforms of the signals Lcom, Von and Voff change as shown in FIG. 5, the gradation signals P0 and P1 have waveforms as shown in FIG. That is, the gradation signal P0 is at the H level from the start timing of one frame until the timing when the period T1 elapses, and thereafter becomes the L level until the end timing of one frame. The gradation signal P1 has a relationship obtained by logically inverting the gradation signal P0.
In the present embodiment, the gradation signals P0 and P1 change in logic level at the timing when the period T1 has elapsed from the start timing of one frame. However, in this embodiment, the gradation signal P0 is at the H level in one frame. The timing at which the logic level changes is set to be a timing before the center of one frame so that the period T2 that becomes the L level becomes longer than the period T1 that becomes.

Next, how the gradation control signal changes with respect to the contents of the gradation bits stored in the SRAMs 461 to 466 will be examined. Here, for the gradation control signals Gr, Gg, and Gb, a gradation control signal G # that is generally expressed without specifying a color will be considered.
This gradation control signal G # includes the logical levels of gradation bits Q # 0 and Q # 1 stored in the SRAM and the logical levels of gradation signals P0 and P1 common to the three blocks R, G and B. Is defined by the result of comparison by the comparison circuit. Specifically, when the gradation control signal G # is at the H level, the gradation level of the gradation bit Q # 0 and the logic level of the gradation signal P0 are both at the H level, or This is a case where the logic level of the bit Q # 1 and the logic level of the gradation signal P1 are both H level.

Therefore, as shown in FIG. 5, the gradation control signal G # has gradation bits (Q # 1, Q #).
If (0) is (0, 0), it is always at the L level, if (0, 1), it is the same as the gradation signal P0, and if (1, 0), it is the same as the gradation signal P1, (1 1) is always H level.
Here, R, G, and B are not specified and generalized using #, but in reality, the gradation control signals Gr, Gg, and Gb correspond to R, G, and B, respectively. Will be generated. For example, the gradation control signal Gr supplied to the R block is stored in the SRAM 462 when the logic level of the gradation bit Qr0 and the logic level of the gradation signal P0 stored in the SRAM 461 are both H level. Logic level of the gradation bit Qr1 and the gradation signal P
When all of the logic levels of 1 are H level, they are generated to be H level.

Subsequently, when such gradation control signals Gr, Gg, and Gb are supplied to the R, G, and B blocks, what happens to the liquid crystal element 150 of the R, G, and B pixels 110, respectively. I will explain it.
First, when the data bit held in the memory circuit 120 of the pixel 110 is at the L level, the NAND signal from the NAND circuit 130 is at the H level regardless of the gradation control signal G #. Turns off, transmission gate 1
As a result, the pixel electrode 118 has a signal V that is the same logic signal as the common electrode 108.
off is applied. For this reason, the voltage VLC applied to the liquid crystal element 150, here, the voltage obtained by subtracting the potential of the pixel electrode 118 from the potential of the common electrode 108 becomes zero. Therefore, in the normally white mode, the pixel corresponds to The brightest color is achieved.

On the other hand, when the data bit held in the memory circuit 120 of the pixel 110 is at the H level, the logic level of the NAND signal by the NAND circuit 130 depends on the gradation control signal G #. Specifically, when the data bit held in the memory circuit 120 is at the H level, the logic level of the negative AND signal becomes the L level when the gradation control signal G # is at the H level,
If the gradation control signal G # is L level, it becomes H level.
If the negative logical product signal is at the L level, the transmission gate 142 is turned on and the transmission gate 144 is turned off, so that the signal Von having a logical inversion relationship with the common electrode 108 is applied to the pixel electrode 118. Therefore, the voltage VLC applied to the liquid crystal element 150 is −Vcc when the signal Lcom is at the L level, and + when the signal Lcom is at the H level.
Vcc. On the other hand, if the NAND signal is at the H level, as described above, the liquid crystal element 15
The voltage VLC applied to 0 is zero.
In this embodiment, the power supply potential is set to Vcc on the higher side and the ground potential Gnd on the lower side. For this reason, when the ground potential is the voltage reference (zero), the logic level H level corresponds to the voltage Vcc, and the L level corresponds to the voltage zero.

If the gradation bits (Q # 1, Q # 0) are (0, 0), the gradation control signal G # is always at the L level, but such gradation control signal G # is supplied to the block. Then, the pixel 110 in which the H-level data bit is held in the block is in the brightest state (off state) in the corresponding color over the entire period of one frame.
When the gradation bits (Q # 1, Q # 0) are (0, 1), the gradation control signal G # changes from H to L level at the timing when the period T1 has elapsed from the start of one frame. However, when such a gradation control signal G # is supplied to the block, the pixel 110 in which the H-level data bit is held in the block has the gradation control signal G # of the one frame period. The darkest state only during the period T1 in the level, the brightest state only in the period T2 in which the gradation control signal G # is at the L level, and the darkest state when one frame is taken as a unit The brightness is in accordance with the ratio between T1 and the period T2 where the brightest state is obtained.

On the other hand, if the gradation bits (Q # 1, Q # 0) are (1, 0), the gradation control signal G # changes from L to H level at the timing when the period T1 has elapsed from the start of one frame. However, when such a gradation control signal G # is supplied to a block, the pixel 110 in which an H-level data bit is held in the block has a gradation control signal G # of L during one frame period. The brightest state only during the period T1 in the level, the darkest state only in the period T2 in which the gradation control signal G # is at the H level, and the brightest state when one frame is taken as a unit The brightness is in accordance with the ratio between T1 and the darkest period T2.
If the gradation bits (Q # 1, Q # 0) are (1, 1), the gradation control signal G # is always at the H level, but such gradation control signal G # is input to the block. When supplied, the pixel 110 in which the H-level data bit is held in the block is in the darkest state (on state) in the corresponding color over the entire period of one frame.

In the present embodiment, when the gradation bits (Q # 1, Q # 0) are (0, 1), the gradation bit (Q # 1) is longer than the period T1 in which the gradation control signal G # is at the H level. , Q # 0) is (1, 0), the gradation signal P0 (P1) is H (L) in one frame so that the period T2 in which the gradation control signal G # is at the H level is longer. ) Since the period T1 to be level is set,
The brightness of the pixel when one frame is taken as a unit is expressed by the gradation bits (Q # 1, Q # 0) (
0, 0), (0, 1), (1, 0), and (1, 1). Thereby, in the present embodiment, four gradation display is possible.
Note that a hatched region in FIG. 5 indicates a period in which the liquid crystal element 150 is turned on, that is, a period in which the darkest period is obtained, in one frame period.

In the present embodiment, since the gradation control signal is individually defined for each of the R, G, and B blocks, the H level data bit is stored in the memory circuit 12 in each block, that is, in each color.
The pixels 110 stored in 0 have the gradation defined by the gradation control signal G # supplied to the block of the color, while the pixels 110 in which the L-level data bits are stored in the memory circuit 120. Is turned off regardless of the gradation control signal G #.
Therefore, according to the present embodiment, although the data bit stored in the memory circuit 120 of the pixel 110 is 1 bit, four gradation display with the same gradation for each block is possible.

Furthermore, in this embodiment, the data bit written in the memory circuit 120 of the pixel 110 is held until it is rewritten next time. For this reason, for example, when displaying a still image, power consumption associated with data rewriting does not occur, so that power consumption can be suppressed to an extremely low level. Further, by adjusting the period T1 of the gradation control signal G # (signals P0 and P1), the gradation of the pixel 110 that holds the H-level data bit can be changed. Furthermore, since the gradation control signal G # is logically inverted twice in one frame, it is possible to suppress an increase in power consumption accompanying this logical inversion.

<Application of First Embodiment>
In the first embodiment, a NAND circuit 130 is provided for each pixel 110. As is generally well known, this NAND circuit 130 includes two p-channel and n-channel transistors in a complementary configuration. Each is composed of a total of four transistors. Of these, by sharing two transistors between adjacent pixels, the total number of transistors required to form the NAND circuit 130 can be reduced.

FIG. 6 shows a NAND circuit composed of pixels 110 adjacent vertically in the same column.
It is a figure which shows the structure which shared two transistors among two transistors, and in detail, (i-1) of the dot located in row j column, i row j column, and (i + 1) row j column It is a figure which shows a structure corresponding to one of the primary colors, that is, the configuration of three pixels 110 adjacent to each other in the column direction. Here, (i-1), i, (i + 1) are symbols for generally indicating the row in which the display dots are arranged, and are integers satisfying 1 ≦ i ≦ 320.

In FIG. 6, p-channel TFTs 132 and 134 and n-channel TFTs
136 and 138 correspond to the NAND circuit 130 in FIG.
Among these, the pixels 110 in which the TFTs 132 are in the same column and are located in the (i-1) row and the i row.
On the other hand, the TFT 138 is shared by the pixels 110 in the same column and located in the i row and the (i + 1) i row.
Therefore, the number of transistors constituting the NAND circuit for one column is (2 × 320 + 320
+1), and the number of transistors required for the NAND circuit can be reduced to about 3/4 as compared with the case where the NAND circuit is simply configured by four transistors per pixel.

In FIG. 6, the signals Von and Voff are not drawn for each row, but are drawn alternately for adjacent rows, so that the wiring is simplified. In FIG. 6, the signal V
On and Voff are drawn alternately between adjacent rows, so that the transmission gate 14
2 and 144 are symmetrical between adjacent rows.

<Second Embodiment>
Next, an electro-optical device according to a second embodiment of the invention will be described.
FIG. 7 is a block diagram illustrating an electrical configuration of the electro-optical device according to the second embodiment. In the second embodiment, the main differences from the first embodiment are that the signal Von is not supplied to the display area 100 and that the signals Von and Voff are supplied to the gradation control signal output circuit 450 instead. It is. For this reason, in the second embodiment, the configuration of the pixel 110 and the configuration of the gradation control signal output circuit 450 are different from the first embodiment in detail. So, for the following,
These differences will be mainly described.

First, the configuration of the pixel 110 in the second embodiment will be described with reference to FIG. As shown in this figure, in the second embodiment, since the NAND circuit 130 does not exist in the pixel 110, the output terminal of the memory circuit 120 is directly connected to the input terminal of the selection circuit 140, that is, NO.
The input terminal of the T circuit 146 is connected.
A signal Voff is supplied to the input terminal of the transmission gate 143, while the input terminal of the transmission gate 145 is connected to the gradation control line 213 to supply the gradation control signal G # and the transmission gate 143. 145 output terminals are commonly connected to the pixel electrode 118.
Further, the normal control gate of the transmission gate 143 is connected to the output terminal of the NOT circuit 146, while the inversion control gate of the transmission gate 143 is connected to the output terminal of the memory circuit 120. The inversion control gate of the transmission gate 145 is connected to the output terminal of the NOT circuit 146 while the transmission gate 14
The normal control gate 5 is connected to the output terminal of the memory circuit 120.
Therefore, in the second embodiment, when the data bit held in the memory circuit 120 is at the H level, only the transmission gate 145 is turned on, and the gradation control signal G # is applied to the pixel electrode 118 while being held. When the data bit is L level, only the transmission gate 143 is turned on, and the signal Voff is applied to the pixel electrode 118.

Next, the configuration of the gradation control signal output circuit 450 in the second embodiment will be described with reference to FIG. As shown in this figure, in the second embodiment, on each output side of the comparison circuits 471, 472, and 473, a NOT circuit 481, transmission gates 482, 48 are provided.
3 selection circuits are provided.
Of these, the selection circuit provided on the output side of the comparison circuit 471 will be described.
The circuit 481 logically inverts the output signal from the comparison circuit 471 and supplies it to the normal rotation control gate of the transmission gate 482 and the inversion control gate of the transmission gate 483, respectively. The inversion control gate of the transmission gate 482 and the normal rotation control gate of the transmission gate 483 are connected to the output terminal Out of the comparison circuit 471, respectively. The signal Voff is supplied to the input terminal of the transmission gate 482, while the signal Von is supplied to the input terminal of the transmission gate 483, and the output terminals of the transmission gates 482 and 483 correspond to the R pixel 110. It is connected to the gradation control line 213.
For this reason, the selection circuit provided on the output side of the comparison circuit 471 selects the signal Von when the signal output from the comparison circuit 471 is at the H level, while selecting the signal Vof when the signal is at the L level.
The f is selected, and the selected signal is output as the gradation control signal Gr.
The same applies to each selection circuit provided on the output side of the comparison circuit 472 (473), and either the signal Von or the signal Voff is selected according to the logic level of the signal output from the comparison circuit 472 (473). Thus, the selected signal is output as the gradation control signal Gg (Gb).

The output signals of the comparison circuits 471, 472, and 473 are the gradation control signal G in the first embodiment.
It corresponds to r, Gg, Gb. Therefore, when R, G, and B are not specified, the output signal of the comparison circuit is always at the L level if the gradation bits (Q # 1, Q # 0) are (0, 0), and (0
1) is the same as the gradation signal P0, (1, 0) is the same as the gradation signal P1, and (1, 1) is always at the H level.
Accordingly, in the second embodiment, the gradation control signal G # is the same as the signal Voff if the gradation bits (Q # 1, Q # 0) are (0, 0), as shown in FIG. Also, if the gradation bits (Q # 1, Q # 0) are (0, 1), the signal Von is the same from the start of one frame until the timing when the period T1 elapses. In the period T2 until the end, it becomes the same as the signal Voff. Further, in the second embodiment, the gradation control signal G # has a gradation bit (Q # 1, Q # 0) of (1, 0) as shown in FIG.
It is the same as the signal Voff from the start of one frame until the timing when the period T1 elapses.
In the period T2 from the timing to the end of one frame, it becomes the same as the signal Von, and if the gradation bits (Q # 1, Q # 0) are (1, 1), it becomes the same as the signal Von.
Here, R, G, B are not specified and generalized using #, but in the second embodiment, gradation control signals Gr, Gg corresponding to R, G, B respectively. , Gb is generated.

In the second embodiment, the pixel 110 has the configuration shown in FIG. 8, and when the data bit held in the memory circuit 120 of the pixel 110 is at the H level, only the transmission gate 145 is turned on. The control signal G # itself is applied to the pixel electrode 118. Therefore, in the second embodiment, when the data bit held in the memory circuit 120 is at the H level, the voltage VLC applied to the liquid crystal element 150 is the gradation bit (Q # 1) as shown in FIG. , Q # 0), the applied waveform is the same as in the first embodiment.
Further, when the data bit held in the memory circuit 120 is at the L level, the pixel electrode 1
18, since only the transmission gate 143 is turned on, the voltage VLC applied to the liquid crystal element 150 becomes zero as a result of the signal Voff being applied to the pixel electrode 118.

Therefore, also in the second embodiment, although the data bit stored in the memory circuit 120 of the pixel 110 is 1 bit, four gradation display with the same gradation for each block is possible.
Furthermore, in the second embodiment, since the NAND circuit 130 in the first embodiment is not necessary, the number of constituent transistors in one pixel 110 can be reduced, so that the configuration can be simplified and the yield can be improved. It becomes.

<Application of Second Embodiment>
By the way, in the second embodiment, the gradation control signal G # when the gradation bits (Q # 1, Q # 0) are (0, 1) is applied to the common electrode 108 as shown in FIG. This corresponds to a signal obtained by delaying the applied signal Lcom by the period T1.
For this reason, the upper control circuit that supplies the signal Lcom supplies a signal delayed by a period T1 with respect to the signal Lcom and a signal obtained by logically inverting the delayed signal to the gradation control signal output circuit 450, The gradation control signal output circuit 450 stores the gradation bits (Q # 1) stored in the SRAM.
, Q # 0) is (0, 1), the former delay signal is selected while the gradation bit (Q # 1) is selected.
, Q # 0) is (1, 0), a logic inversion signal of the latter delay signal may be selected and the selected signal may be output as the gradation control signal G #.
Further, the gradation control signal output circuit 450 receives the signal Lcom and also outputs the signal Lcom.
Similarly, the gradation bits (Q # 1, Q # 0) stored in the SRAM are delayed by the period T1.
It is good also as a structure selected according to.

<Blockization etc.>
In the first and second embodiments described above, gradation display is performed when the data bit held in the memory circuit 120 is at the H level, while off display is performed when the data bit is at the L level. However, a gradation display may be performed when the held data bit is at the L level, or an off display or an on display may be performed when the data bit is at the H level.
In the embodiment, the primary colors R, G, and B are divided into blocks, and the gradation control signals Gr, Gg, and Gb are supplied to these blocks. However, the present invention is not limited to this. Absent. For example, when the electro-optical device 10 is used as a display unit of a mobile phone as will be described later, as shown in FIG.
, Br2 and Br3, and a gradation control signal may be supplied to each of these blocks. Alternatively, as shown in FIG. 12, the standby display area is further divided into blocks Br11 by grouping display character units such as an incoming mail icon, a radio wave intensity icon, a date (day of the week), a time, and a battery remaining amount icon. , Br12, Br13, Br14 and B
It is also possible to use r15 as the other area and use the block Br16 as the other area, and supply a gradation control signal to each of these blocks. In this way, the gradation can be changed for each display character unit such as an icon, a number, or a character.

In the embodiment, a signal having one pulse width and a signal obtained by logically inverting the two intermediate gradations are represented as gradation control signals. However, the period T1 varies depending on the gradation. It is good also as the structure made to do. As described above, when the period T1 is changed according to the intermediate gradation, the number of intermediate gradations can be increased.
Note that the number of SRAMs in the gradation control signal output circuit 450 is determined by the number of blocks and the number of gradations. That is, the number L of SRAMs is expressed by the following equation when the number of blocks is M and the number of gradations is N.
L = M × log ₂ N
For example, in the first and second embodiments described above, the number of blocks M is 3 and the number of gradations is 4 (= 2 ²
), L is “6”.

In the embodiment described above, the liquid crystal element 150 is AC driven by inverting the level of the signal Lcom at a cycle of 1 frame. However, the present invention is not limited to this, and for example, at a cycle of 2 frames or more. A configuration in which the level is inverted may be used.
Furthermore, although the liquid crystal element 150 is in the normally white mode, it may be in a normally black mode that is the darkest state when no voltage is applied.
In addition to color display with the three primary colors of RGB, a configuration in which primary colors such as purple and emerald green are added to display colors in four or more primary colors may be used, or a configuration in which the display area 100 is simply divided and displayed in black and white. good.

In addition, the present invention is not limited to the transmission type, and may be a reflection type or a semi-transmission semi-reflection type intermediate between the two. Furthermore, in addition to the TN type, a dye (guest) having anisotropy in absorption of visible light in the major axis direction and the minor axis direction of the molecule, such as STN type, is dissolved in a liquid crystal (host) having a certain molecular arrangement. Alternatively, a guest-host type liquid crystal in which dye molecules are arranged in parallel with liquid crystal molecules may be used. In addition,
Vertical alignment (homeotropic alignment) in which liquid crystal molecules are aligned vertically to both substrates when no voltage is applied, while liquid crystal molecules are aligned horizontally to both substrates when voltage is applied
Or a so-called IPS (including in-plane switching method and FSS) method.
Furthermore, as an electro-optical element, in addition to a liquid crystal element, an EL (electroluminescence) element, an electrophoretic element, an electron emitting element, a digital mirror element, a plasma display, and the like can be applied. In other words, the present invention is applicable to all electro-optical devices that store binary data bits that indicate on or off.
Here, for example, since the EL element is a current driving element unlike the liquid crystal element, the gradation is defined by the current effective value of the gradation control signal in one frame.

<Electronic equipment>
Next, an electronic apparatus having the electro-optical device 10 according to the above-described embodiment as a display device will be described. FIG. 13 is a perspective view showing a configuration of a mobile phone 1200 using the electro-optical device 10 according to the embodiment.
As shown in this figure, the mobile phone 1200 includes a plurality of operation buttons 1202, the earpiece 1204 and the mouthpiece 1206, and the display area 100 of the electro-optical device 10 described above. Note that components of the electro-optical device 10 other than the display area 100 do not appear as appearance.

As an electronic apparatus to which the electro-optical device 10 is applied, in addition to the mobile phone shown in FIG. 13, a digital still camera, a notebook computer, a liquid crystal television, a viewfinder type (
Or a monitor direct view type video recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a workstation, a videophone, a POS terminal, a device equipped with a touch panel, and the like. And as a display device for these various electronic devices,
Needless to say, the above-described electro-optical device 10 is applicable. In any electronic device, gradation display according to the data bit and gradation control signal stored in the memory circuit is possible.

1 is a block diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. FIG. 3 is a diagram illustrating a configuration of a gradation control signal output circuit in the electro-optical device. It is a figure which shows the structure of the comparison circuit in the gradation control signal output circuit. FIG. 6 is a signal waveform diagram illustrating an operation of the electro-optical device. It is a figure which shows another example of the pixel in the same electro-optical apparatus. FIG. 6 is a block diagram illustrating a configuration of an electro-optical device according to a second embodiment of the invention. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. FIG. 3 is a diagram illustrating a configuration of a gradation control signal output circuit in the electro-optical device. FIG. 6 is a signal waveform diagram illustrating an operation of the electro-optical device. It is a figure which shows the example of blocking of the same electro-optical apparatus. It is a figure which shows the example of blocking of the same electro-optical apparatus. It is a figure which shows the structure of the mobile telephone to which the electro-optical apparatus which concerns on embodiment is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 105 ... Liquid crystal, 108 ... Common electrode, 118 ... Pixel electrode, 120 ...
Memory circuit (first memory circuit), 130... NAND circuit, 132, 134, 136, 13
8 ... TFT, 140 ... selection circuit, 150 ... liquid crystal element, 211 ... bit line, 213 ... gradation control line, 311 ... word line, 450 ... gradation control signal output circuit, 461-466 ... SRAM (
Second memory circuit), 1200 ... mobile phone

Claims (10)

An electro-optical device having a plurality of pixels,
For each pixel,
A first memory circuit holding one bit;
When the logical level of the bit held in the first memory circuit is one of the gradation control signals supplied for each block in which the plurality of pixels are collected, the level supplied to the block to which the pixel belongs. Gradation is displayed according to the effective value of the voltage or current of the control signal,
When the logical level of the bit is the other, an electro-optic element that is turned on or off according to the bit ,
A gradation control signal output circuit for outputting the gradation control signal to a corresponding block ;
The gradation control signal output circuit is
A second memory circuit for storing data defining a gradation including an intermediate gradation of the block and holding the gradation until the gradation is changed;
The gradation control is performed so that the electro-optic element has a gradation defined by data stored in the second memory circuit when the logical level of the bit held in the first memory circuit is one. An electro-optical device that generates and outputs a signal . Before Kikaicho control signal, the electro-optical device according to claim 1, characterized in that the constant period is a logic signal which is a predetermined pulse width. When the logic level of the bits held before Symbol first memory circuit is one, while selecting the tone control signal, when the logic level of the bit is the other, the gate for selecting the bit Circuit,
A selection circuit for selecting one of signals for turning on or off the electro-optic element according to a logic level by the gate circuit and supplying the selected signal to the electro-optic element;
The electro-optical device according to claim 2 , further comprising: Before Symbol gate circuit is a NAND circuit of the four-transistor configuration,
The electro-optical device according to claim 3 , wherein two of the four transistors are shared by adjacent pixels. Before Kikaicho control signal is a signal for signal for turning on or off the electro-optical element is distributed at a predetermined ratio in a fixed period,
When the logic level of the bit held in the first memory circuit is one, the gradation control signal is selected and supplied to the electro-optic element;
A selection circuit that selects one of the signals for turning on or off the electro-optic element and supplies the selected signal to the electro-optic element when the logical level of the bit is the other;
The electro-optical device according to claim 1, further comprising: When the number of blocks is M and the number of gradations for gradation display is N, the number L of the second memory circuits included in the gradation control signal output circuit has a relationship of L = M × log ₂ N. Fulfill
The electro-optical device according to claim 2, wherein Before SL pixels, corresponding to at least three or more different primary colors,
The electro-optical device according to claim 1, wherein each block is defined for each primary color. Before SL each block, the electro-optical device according to claim 1, characterized in that it is defined for each character display unit. A pixel of multiple stores a first memory circuit for holding one bit for each of the pixels, the data defining a gray scale including the intermediate gray blocks that summarizes the plurality of pixels, the gradation And a second memory circuit that holds the change until the change is made ,
The pixel,
The gradation control signal so that the electro-optic element has a gradation defined by the data stored in the second memory circuit when the logical level of the bit held in the first memory circuit is one. by outputting the blocks corresponding to generate, prior of tone control signal supplied to Chivu each lock, the effective value of the voltage or current of the pixels are supplied to the blocks belonging tone control signal The gradation display according to
When the logical level of the bit is the other, the display is turned on or off according to the bit. 請 Motomeko electronic apparatus comprising the electro-optical device according to any one of 1 to 8.

Images