JPH09159993A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lower the power consumption of a driving circuit without spoiling picture quality. SOLUTION: In an active matrix type control circuit 10, 1st and 2nd shift registers 21 and 22 are arranged. Then display data which is one scanning line precedent is transferred to the 2nd shift register 22 and display data corresponding to the latest inputted scanning line is transferred to the 1st shift register 21. A comparator 23 compares the data of the 1st and 2nd shift registers 21 and 22 with each other. When the display data all match each other, a coincidence signal is outputted from the comparator 23, but when some of the display data is discrepant, on the other hand, a discrepancy signal is outputted. When the coincidence signal is outputted, no new display data is transferred and the display data, one scanning line precedent, which is latched by a signal line driving circuit is used as it is.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art Liquid crystal display devices are thin and lightweight, can be driven at a low voltage, and can be easily colorized. In recent years, they have been used as display devices for personal computers, word processors and the like. . Above all, a so-called active matrix type liquid crystal display device, in which a thin film transistor (TFT) is provided as a switching element for each pixel, has no deterioration in contrast, response, etc. even if it has many pixels, and can also perform halftone display. Therefore, it is considered to be the most suitable system as a display device for a full-color television or OA.

An active matrix type liquid crystal display device has two flat glass substrates (an array substrate and a counter substrate).
And a liquid crystal layer sandwiched between these substrates. On one glass substrate, that is, a counter substrate, a color filter array corresponding to each pixel and a transparent electrode (counter electrode) are arranged. The array substrate is provided with pixel electrodes formed of transparent electrodes arranged in a matrix and TFTs whose source electrodes are connected to the respective pixel electrodes. The gate electrode of the TFT is connected to the address line provided in the X direction, and the drain electrode is connected to the signal line provided in the direction orthogonal to the address line.

In the liquid crystal display device constructed as described above,
By applying the address signal and the data signal to the address line and the signal line, respectively, at a predetermined timing, it is possible to selectively apply the voltage corresponding to the display to each pixel electrode.
The orientation of the liquid crystal layer, that is, the light transmittance can be controlled by the potential difference between the counter electrode and the pixel electrode, which enables arbitrary display. For details, see T. P. Brody et al. (IEEE Tra
ns. on Electron. Devices. Vol. ED-20, Nov., 1973,
pp. 995-1001).

There are two types of liquid crystal display devices, a transmissive type and a reflective type, both of which are composed of a liquid crystal panel and a drive circuit for applying a display voltage to each pixel. In the transmissive liquid crystal display device, a desired screen brightness is obtained by installing a backlight on the back surface of the liquid crystal panel. The power consumption of the liquid crystal display device is determined by the power of the drive circuit and the backlight. Especially,
For portable use, long-term operation by battery drive is desired, and a low power consumption type liquid crystal display device is essential. With a liquid crystal display device with a screen size of 10 inches or less,
With the improvement of the backlight efficiency and the aperture ratio of pixels, the ratio of the backlight power is reduced, and the power consumption of the drive circuit is about 1/3 or more of the whole. In the reflective liquid crystal display device, the driving circuit consumes all the power. Further, in recent years, the power consumption of the drive circuit has been increasing due to the multi-gradation of images.

[0006]

Considering the operation of the conventional liquid crystal display device from the viewpoint of the power consumption of the drive circuit, the control circuit (see reference numeral 10 in FIG. 1) always has the control circuit regardless of the displayed image. A video signal is input and each drive circuit in the liquid crystal display device is operating. In this case, since most of the driving circuit is composed of CMOS, the static power consumption is low, but in a large-screen and high-definition display in which the data amount increases, the dynamic power consumption increases and the driving circuit This causes an increase in power consumption.

For example, the total amount of data corresponding to the image displayed per second is the color VGA of stripe arrangement.
In case of, 60 [Hz] * 640 * 3 [pixel] * 480
[Pixel] * 8 [bit] = 400 [Mbit],
60 * 1280 * 3 * 1024 for color SXGA
* 8 = 1600 [M bits], which means that these displays perform enormous data processing. The power consumption consumed for the data processing increases the power consumption of the liquid crystal display device, and becomes a factor that hinders the application of the high-definition liquid crystal display device to a portable device in particular. Therefore, an object of the present invention is to reduce the power consumption of a drive circuit in a liquid crystal display device without impairing the image quality.

[0008]

SUMMARY OF THE INVENTION The essence of the present invention is to reduce the data processing amount in the signal line drive circuit and reduce the power consumption of the drive circuit in consideration of the correlation of the displayed video data. . That is, in order to achieve the above purpose,
The liquid crystal display device of the present invention, by any of the following methods,
The amount of data processing in the signal line driver circuit is reduced.

A first aspect of the present invention is to dispose a plurality of pixel electrodes arranged in a matrix and electrically independent from each other, a counter electrode facing the pixel electrode, and disposed between the pixel electrode and the counter electrode. In a liquid crystal display device, the liquid crystal display device comprises: a liquid crystal layer which is formed into a liquid crystal layer; and a peripheral circuit for synchronously transferring a display voltage to the pixel electrode at a constant cycle by a digitized display signal. Further comprising means for detecting the correlation between the subsequent display signals, means for stopping the transfer of correlated data in the subsequent display signal, and means for demodulating the transfer stopped data based on the data for the previous display signal. It is characterized by doing.

A second aspect of the present invention is to correspond to the intersections of a plurality of signal lines and a plurality of address lines arranged in a grid, and to arrange a plurality of electrically independent lines arranged in a matrix. A pixel electrode, a counter electrode facing the pixel electrode, a liquid crystal layer disposed between the pixel electrode and the counter electrode,
In a liquid crystal display device comprising a peripheral circuit for transferring a display voltage to the signal line by a digitized display signal in synchronization with the address line signal, a signal line driving circuit of the peripheral circuit is a line. A memory and a plurality of n-bit shift registers, wherein the liquid crystal display device has m-th shift register among the n-bit shift registers.
Display data corresponding to the th address line and the (m-1) th
And comparing the mth display data with each other, and when the mth display data is the same as the (m-1) th display data, the transfer of the mth display data is stopped and the line memory Means for outputting display data corresponding to the (m-1) th address line stored in the signal line to the signal line.

According to a third aspect of the present invention, a plurality of electrically independent lines arranged in a matrix are arranged corresponding to the intersections of a plurality of signal lines and a plurality of address lines arranged in a grid. A pixel electrode, a counter electrode facing the pixel electrode, a liquid crystal layer disposed between the pixel electrode and the counter electrode,
In a liquid crystal display device, comprising: a peripheral circuit for transferring a display voltage to the signal line by a digitized display signal in synchronization with the address line signal, a plurality of signal line drive circuits for the peripheral circuit are provided. Of the n-bit shift register, the liquid crystal display device displays the display data corresponding to the m-th address line and the (m-1) -th display data in the n-bit shift register. And the m-th data is converted into logic data composed of digital signals corresponding to the bit whose logic value matches the bit of the (m-1) -th display data and the bit which does not match, and is transferred. And a means for performing a double-tone on the logical data transferred to the n-bit shift register.

According to a fourth aspect of the present invention, in the liquid crystal display device according to any one of the first to third aspects, the peripheral circuit stores a digital signal corresponding to a display voltage of each pixel, Means for transferring a logic signal for discriminating rewriting of data of each pixel to the signal line drive circuit separately from the digital signal, and the digital signal is applied to the pixel electrode only when the logic signal is in the rewriting state. The signal is transferred.

According to a fifth aspect of the present invention, in the liquid crystal display device according to the fourth aspect, an image memory for storing the display signals corresponding to all pixels, and data of the image memory for each field are provided on the signal line. And a means for transferring to a drive circuit, wherein the image memory has, for each pixel, a data determination bit for determining whether the state of display data is rewritten in the latest field separately from the display signal, According to the data determination bit, only the pixel data corresponding to the rewriting is transferred to the signal line drive circuit, and at the same time, the rewriting bit is also transferred at the same time.

According to a sixth aspect of the present invention, in the liquid crystal display device according to the fifth aspect, the image memory is arranged separately from the peripheral circuit. In the liquid crystal display device using the drive circuit of the present invention, it is possible to reduce the power consumption of the drive circuit. In general, displayed images have a strong correlation between adjacent pixels, and most of the images displayed on a computer display are still images.

According to the first and second aspects of the present invention, when the display data between adjacent scanning lines are completely the same or a part of them are the same, the display of the line memory provided in the signal line drive circuit is performed. The data can be used as it is as the data of the pixel corresponding to the next scanning line. Therefore, it is possible to reduce the data transfer from the control circuit, which consumes particularly high power even in the drive circuit, to the signal line circuit and the operation of the shift register in the signal line drive circuit.

According to the third and fourth aspects of the present invention, when only a part of the display data between adjacent scanning lines is different, only this data is processed in the signal line drive circuit. A large amount of data processing can be realized and dynamic C
The power consumption of the MOS circuit can be greatly reduced.

Further, according to the fifth and sixth aspects of the present invention, since only the data of an arbitrary pixel whose display data is newly rewritten needs to be processed, a significant reduction in power consumption can be realized. The drive circuit configuration according to the present invention exhibits a great effect particularly in a display device for OA, which has many graphic displays.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an outline of a liquid crystal display device common to the embodiments of the present invention described below. The liquid crystal panel 1 is of a TFT-LCD type, that is, a thin film transistor (TFT) 4 is attached to each pixel electrode 5 of a plurality of pixels arranged in a matrix. The gate electrode of the TFT 4 is connected to the address line, that is, the gate line 3 provided in the X direction. The source electrode of the TFT 4 is connected to the pixel electrode 5, and the drain electrode is connected to the data line or signal line 2 orthogonal to the gate line 3. The display signal applied to the signal line 2 (S1, ...) Is generated by the scanning line driving circuit (IC) 6 and is applied to the gate line 3 (Y1, ...) By the selection pulse applied to the TFT 4, which is brought into a conductive state. It is added to the pixel electrode 5 through the liquid crystal layer and drives the liquid crystal layer.

In the process of generating the display signal voltage, the digital data Di0 to Dij input to the liquid crystal display device.
Are rearranged by the control circuit (IC) 10 into an array corresponding to the signal line 2 of the liquid crystal panel 1 and converted into signals Da0 to Dak and Db0 to Dbk, respectively. The display signals Da0 to Dak and Db0 to Dbk are transferred to the bus line 13
signal line drive circuit (IC) 15a via a and 13b,
The display signals for one scanning line, which are input to the shift registers 7a and 7b of 15b, are arranged in the shift registers 7a and 7b.

In the signal line drive circuits 15a and 15b,
The display signal is fetched by the latch circuits 8a and 8b, and further,
DA converter 9a for converting these into display signal voltages,
Input to 9b. In the display signal voltage output to the signal line 2, each output Oa1, Oa2, ..., Ob1, Ob
For 2, ..., (k + 1) -bit data of 0 to k is input. The display signal voltage is applied to the pixel electrode via the TFT on the gate line 3 selected by the pulse signal from the scanning line driving circuit 6.

FIG. 2 shows a characteristic part of the liquid crystal display device according to the first embodiment of the present invention. The mechanism shown in FIG. 2 is similar to that shown in FIG.
It is included in the illustrated control circuit (IC) 10. Here, in the data rearrangement circuit 20, the input data Di0 to Dij are input to the respective signal line drive circuits 15a, 1a.
It is rearranged as display data for 5b. The rearranged display data is first transferred to the first shift register 21. Then, the display data corresponding to the next scanning line is input to the second shift register 22. That is, the display data corresponding to each scanning line is alternately transferred to the first and second shift registers 21 and 22 for each scanning line.

Here, for example, the first shift register 21
In the comparator 23, the display data corresponding to the m-th scanning line of the second shift register 22 and the display data corresponding to the (m + 1) -th scanning line of the second shift register 22 are compared. When all display data match, the output CO of the comparator 23 becomes, for example, "L" as a match signal. On the contrary, when at least some display data do not match, the output CO of the comparator 23 becomes, for example, “H” as the mismatch signal.

If they do not match, the display data of the next (m + 2) th scanning line is transferred to the first shift register 21 in synchronization with (m + 2) of the second shift register 22.
The display data corresponding to the 1) th scanning line is transferred to the line buffers 29a and 29b via the gate 26. Next, the display data includes display signals Da0 to Dak and Db0.
As Dbk, from the line buffers 29a and 29b via the bus lines 13a and 13b to the signal line drive circuit 15a,
15b, and a display signal is generated on the signal line 2 by the same operation as the conventional one.

The gate 27 is a bus line 13a, 13b.
When no signals are transferred to the signal line drive circuits 15a and 15b that receive signals from the signal line drive circuits 15a and 15b,
This is also for stopping the transfer of the clock signal for driving 5b.

The gate 28 includes signal line drive circuits 15a, 1
The circuit for controlling the clock Φa to 5b outputs the clock Φa when the outputs of the comparators do not match. The gate 27 is a circuit for controlling the gate 28, and when the outputs of the comparators do not match, a clock is generated from the gate 28. Input to gate 27 27 ₁ 27 ₂
27 _k is shown, which is the case where a plurality of signal line drive circuits 15a and 15b are provided in parallel in the large-screen high-definition LCD, and the shift registers 21 and 2 are provided.
2 and a plurality of comparators 23 are provided, which corresponds to the case where (k + 1) coincident or non-coincident output COs are generated. In this case, one of the inputs 27 _{0 to} 27 _k
The clock is generated from the gate 28 even if there is no match. In consideration of low power driving, (k + 1) gates 28 may be provided and each gate may be driven independently.

When the output CO of the comparator 23 is the same, the gates 26 and 28 are closed and the display data is not transferred. Usually, the signal line drive circuits 15a and 15b are arranged on a printed circuit board. In addition, the output impedance of the line buffers 29a and 29b is set low because the wiring capacity and the signal speed are high. Therefore, the power consumption of the line buffer circuit becomes a considerable ratio. Therefore, the power consumption of the control circuit 10 can be significantly reduced by reducing the transfer amount of the high-speed signal transferred from the line buffer. In the present embodiment, when the new display data and the display data one scanning line before match, the new display data is not transferred and is latched by the latch circuits 8a and 8b of the signal line driving circuit. The display data before the scan line is used as it is.

In this case, the lines L1 and L2 have "H" or "L" corresponding to display data coincidence or non-coincidence.
Signal is prepared, and this signal is transferred to the latch circuits 8a and 8b of the signal line drive circuit. When the display data match and the drive circuit is composed of a CMOS circuit, there is no change in the states of the line buffers 29a and 29b and the shift registers 7a and 7b of the signal line drive circuit.
Little power is consumed. In addition, the control circuit 10
In, the first and second shift registers 21 and 22 are newly required. However, if these are formed in the same chip, the load capacity is very small because only the MOS transistor in the circuit is present, and the power due to this is small in the buffer 2.
It can be much smaller than 9a and 29b.

FIG. 3A shows a characteristic part of the liquid crystal display device according to the second embodiment of the present invention. The mechanism shown in FIG. 3A is arranged on the input side of the control circuit (IC) 10 shown in FIG. The second embodiment is common to the first embodiment in that new data is compared with data one scanning line before.

The input data transferred from the CPU 30a is stored in the frame memory 30b and, at the same time, transferred to the control circuit 10. In this embodiment, in order to reduce the amount of display data transferred to the liquid crystal display device, a data comparison circuit for each scanning line used in the first embodiment is provided between the frame memory and the data transfer buffer 39. And a transfer control circuit. Specifically, the data Dio ', Di output from the frame memory 30b
.. are compared by the shift registers 31, 32 and the comparator 33.

The new data is not transferred to the control circuit 10 in the bit corresponding to the data bit Dij 'in which the new data and the data one scanning line before match. Therefore, the data transfer buffer 39 outputs the data Dio0 to Dij whose transfer amount has been reduced. Further, in order to inform the signal line driving circuits 15a and 15b that the scanning line output is the same as the data of the previous line, the data coincidence signals Cio to Cij are also simultaneously output. As a result, correct signal processing and image processing can be realized on the main body side of the liquid crystal display device.

In the second embodiment, since it is not necessary to provide a special shift register on the body side of the liquid crystal display device,
It is possible to reduce the total power consumption most efficiently. Further, the data coincidence signals Cio to Cij can be transferred to the display device side by being superimposed on the output bus line. FIG. 3B shows this mode, in which the display data is transferred within the display data transfer time Ta and the coincidence signal Cij is transferred within the blanking time Tb. As a result, it is possible to inform the main body of the liquid crystal display device whether the next data is new data or the same as the data one scanning line before.

FIG. 4 shows an outline of the body side of the liquid crystal display device according to the second embodiment shown in FIG. Here, the input display signal data Dio0 to Dij is the signal line drive circuit (IC) 1
The case where it is supplied to 5a and 15b is shown. For example, the input data Di0 is input to the shift register 51 and distributed to the signal line driving circuits 15a and 15b bit by bit, for example (Da0 and Db0 in FIG. 4).

If the new data and the data one scanning line before are the same and the coincidence signal Ci0 becomes "H", the clock 52 to the shift register 51 is stopped and the shift register 51 stops operating. At the same time, the data stored in the line memories (latch circuits 8a and 8b) of the signal line driving circuit are effectively used as they are. On the contrary, when the new data and the data one scanning line before do not match, the above-described data distribution operation is performed.

The circuit 54 is a signal line driving circuit 15a,
It controls the clock Φo to 15b. When all the data Ci0 to Cik match, the shift registers of the signal line drive circuits 15a and 15b do not need to operate, so the circuit 54 stops the transfer of the clocks Φa and Φb.

FIG. 5A shows a characteristic part of the liquid crystal display device according to the third embodiment of the present invention. The mechanism shown in FIG. 5A is included in the control circuit (IC) 10 shown in FIG. Here, the data Dil is
It is transferred to the first shift register 61. Then, the display data corresponding to the next scanning line is transferred to the second shift register 62. Further, the display data corresponding to the next scanning line is transferred to the first shift register 61 again.

The third shift register 63 is based on the comparison of the display data in the first and second shift registers 61 and 62.
At, a new data string Z shown in FIG. 5B is created. The conversion logic used here is defined by the following equation:

Z = Di−1,1 (Yj−1) * Di, 1 (Yj) + Di−1,1 (Yj) * Di, 1 (Yj−1) (1) The data string Z is new. It is a logical data string that indicates, by "1", that the data and the data one scanning line before have different states. That is, this embodiment is characterized in that only the bit whose state has changed is extracted from the data one scanning line before, thereby reducing the amount of subsequent data processing. In this regard, in the second and third embodiments, even if the new data and the data one scanning line before are partially the same, all the new data will be transferred as they are. .

FIG. 6 shows a mode in which the demodulation of the logical data sequence created as shown in FIG. 5B is realized by the signal line drive circuits 15a and 15b. Here, the shift register 71 corresponds to the shift register 7a (or 7b) of FIG. 1, and the line memory 72 and the conversion circuit 73 are the latch circuit 8a of FIG.
(Or 8b). The data string Z is input to the shift register 71 of the signal line drive circuit and further transferred to the conversion circuit 73 together with the data of one scan line before in the line memory 72. In the conversion circuit 73, the data conversion opposite to the equation (1) is performed, and the converted data Wi1 is transferred to the signal voltage generation circuit and at the same time stored in the line memory 72.

The drive circuit according to the third embodiment exhibits a particularly low power effect when the image data for OA is taken into consideration.
Next, referring to FIGS. 7 and 8, the fourth and fifth aspects of the present invention will be described.
An embodiment will be described. The fourth and fifth embodiments can be applied to a liquid crystal panel in which each pixel has some memory function or a function of selectively writing data to an arbitrary pixel.

FIG. 7 is a diagram showing the characterizing portion of the liquid crystal display device according to the fourth embodiment of the present invention. In FIG.
Two TFTs 81 and 82 are arranged in each pixel, and a write enable / disable signal Gij is input to the first TFT 81. Here, a signal that is writable, that is, a signal of Gij = “H”, is transmitted through the TFT 81 to the TFT 82 for signal voltage writing.
When written in the gate electrode of the TFT 82, the TFT 82 is turned on. In this state, the DA converter 83 (see FIG.
The display voltage Voij from the illustrated DA converters 9a and 9b) can be written to the pixel electrode 5ij. The display voltage Voij is effectively written in the pixel electrode as follows.
Only when the gate voltage of the scanning line Yi is in the selected state and the write signal Gij is in the selected state. When Gij is unselected, no matter what the display voltage Voij is, the pixel electrode 5i
It has no effect on j.

The display signal processing circuit of the fourth embodiment requires a frame memory. In addition to the display data of all pixels, the frame memory also stores the rewrite selection signal Gij for determining whether or not the data has been updated from all the frame data. When the CPU or the like updates data in the frame memory, the selection signal Gij is set to, for example, "H". The frame memory data is sequentially collated for each scanning line, and the image data is transferred to the signal line driving circuit in the scanning line where Gij is “H”. At this time, all the pixel data in which Gij is “L” are set to “L”, for example, and the power consumption consumed by the shift register or the like is suppressed.

Further, in the fourth embodiment, if the display data is transferred to the signal line drive circuit according to any one of the above-mentioned first to third embodiments, the power consumption can be further reduced. .

FIG. 8 is a diagram showing the characterizing portion of the liquid crystal display device according to the fifth embodiment of the present invention. The liquid crystal panel 1 has a memory function, and each pixel has two display states of white and black. In the present embodiment,
The display signal input to each pixel is “H” or “L” 2
Value. This display signal is input to the flip-flop (FF) 95 via the TFT 94. When the input data is "H", the output of the FF 95 is inverted (that is, the data is rewritten). FF95 when the input data is "L"
Output does not change and the previous state is retained. TFT9
Reference numerals 6 and 97 denote CMOS buffer circuits, which are liquid crystal layers 98.
Is a circuit for driving.

In the fifth embodiment, the frame memory 91 is used, and the data corresponding to the pixel in which the display signal is newly written is stored in the state of being subjected to the data conversion shown in FIG. 5B. It That is, the frame memory Gij
In, the display data is updated only for the pixel of Gij = “H”. The data in the frame memory is sent via the control circuit 92 to the signal line driving circuits 93a and 9a for each scanning line.
3b and applied to the signal line of the liquid crystal panel. Here, in the data transferred to the signal line drive circuits 93a and 93b, only the rewritten bits are "H", and the rest are "L". Therefore, in the case of OA for which the amount of data rewriting is small, it is possible to minimize the power consumption of the shift register due to the change in data.

[0045]

According to the present invention, in a display device using a digital signal as a display signal, the fact that image data has a correlation between adjacent pixels is utilized to reduce the amount of data processed by the drive circuit. You can do it. Therefore, it is possible to significantly reduce the dynamic power that occupies most of the power consumption of the drive circuit of the liquid crystal display device, particularly the display device for OA.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an outline of a liquid crystal display device.

FIG. 2 is a diagram showing a characteristic part of the liquid crystal display device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a characteristic portion of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing an outline of a main body side of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a characteristic part and a logical data string of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a mode in which demodulation of a logical data string according to a third embodiment of the present invention is realized by a signal line drive circuit.

FIG. 7 is a diagram showing a characterizing portion of a liquid crystal display device according to a fourth embodiment of the present invention.

FIG. 8 is a diagram showing a characterizing portion of a liquid crystal display device according to a fifth embodiment of the present invention.

[Explanation of symbols]

1 ... Liquid crystal panel, 2 ... Signal line, 3 ... Gate line, 4 ... TF
T, 5 ... Pixel electrode, 6 ... Scan line drive circuit, 7a, 7b ...
Shift register, 8a, 8b ... Latch circuit (line memory), 9a, 9b ... DA converter, 10 ... Control circuit, 21, 22 ... Shift register, 23 ... Comparator, 29a, 29b ... Line buffer, 30a ... CP
U, 30b ... Video memory (frame memory) 31,
32 ... Shift register, 61, 62, 63 ... Shift register, 71 ... Shift register, 72 ... Line memory, 7
3 ... Data demodulation circuit.

Claims (6)

[Claims] 1. A plurality of electrically isolated pixel electrodes arranged in a matrix, a counter electrode facing the pixel electrode, a liquid crystal layer disposed between the pixel electrode and the counter electrode, and a digital circuit. A liquid crystal display device comprising: a peripheral circuit for synchronously transferring a display voltage to the pixel electrode at a constant cycle by the converted display signal; and means for detecting a correlation between the display signals during the transfer cycle. When,
A liquid crystal display device further comprising means for stopping the transfer of correlated data in the subsequent display signal, and means for demodulating the data whose transfer has been stopped based on the data of the previous display signal. . 2. A plurality of pixel electrodes arranged in a matrix and electrically independent of each other, corresponding to intersections of a plurality of signal lines and a plurality of address lines arranged in a grid, and the pixel electrode. And a liquid crystal layer disposed between the pixel electrode and the counter electrode, for transferring a display voltage to the signal line by a digitized display signal in synchronization with the address line signal. A liquid crystal display device including a peripheral circuit, wherein the signal line driving circuit of the peripheral circuit includes a line memory and a plurality of n-bit shift registers.
The liquid crystal display device compares the display data corresponding to the mth address line in the n-bit shift register with the (m-1) th display data, and the mth display data is When it is the same as the (m-1) th display data, the transfer of the mth display data is stopped, and it corresponds to the (m-1) th address line stored in the line memory. A liquid crystal display device comprising means for outputting display data to the signal line. 3. A plurality of electrically independent pixel electrodes arranged in a matrix corresponding to the intersections of a plurality of signal lines and a plurality of address lines arranged in a grid, and the pixel electrodes. And a liquid crystal layer disposed between the pixel electrode and the counter electrode, for transferring a display voltage to the signal line by a digitized display signal in synchronization with the address line signal. A liquid crystal display device including a peripheral circuit, wherein the signal line driving circuit of the peripheral circuit includes a plurality of n-bit shift registers, and the liquid crystal display device includes:
In the n-bit shift register, the display data corresponding to the m-th address line is compared with the (m-1) -th display data, and the m-th data is changed to the (m-
1) Means for converting into logical data consisting of digital signals corresponding to the bit whose logical value matches that of the display data and the bit not corresponding to the logical value, and transferring the logical data, and the logical data transferred to the n-bit shift register. A liquid crystal display device characterized by comprising: 4. The means for the peripheral circuit to store a digital signal corresponding to the display voltage of each pixel, and a logic signal for discriminating the rewriting of the data of each pixel to the signal line drive circuit, separately from the digital signal. 4. The liquid crystal display according to claim 1, further comprising: a transfer unit, wherein the digital signal is transferred to the pixel electrode only when the logic signal is in a rewritten state. apparatus. 5. The image memory further comprises: an image memory for storing the display signals corresponding to all pixels; and means for transferring the data of the image memory to the signal line drive circuit for each field. In addition to the display signal, each pixel has a data determination bit for determining whether the state of the display data has been rewritten in the latest field, and only the pixel data corresponding to the rewriting by the data determination bit is the signal line drive circuit. 5. The liquid crystal display device according to claim 4, wherein the rewriting bit is also transferred at the same time when the rewriting bit is transferred to. 6. The liquid crystal display device according to claim 5, wherein the image memory is provided separately from the peripheral circuit.