JP2002297082A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the error in writing of a video signal to a holding circuit, even if this display device is operated under a low-power source voltage and to perform correct display according to the video signal held in the holding circuit. SOLUTION: In this display device, a digital video signal is written from a drain signal line 61 in a holding circuit 110 through a pixel selecting TFT(thin-film transistor) and display is performed according to the digital video signal held in the holding circuit 110. Moreover, a threshold VT1 of a first inverter circuit INV1 constituting the holding circuit 110 is set lower than a threshold VT2 of a second inverter circuit INV2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a display device suitable for a portable display device.

[0002]

2. Description of the Related Art In recent years, portable display devices such as portable televisions and portable telephones have been demanded as market needs. In response to such demands, research and development have been actively conducted to reduce the size, weight, and power consumption of the display device.

FIG. 6 shows a circuit configuration diagram of one display pixel of a liquid crystal display device according to a conventional example. On an insulating substrate (not shown),
The gate signal line 51 and the drain signal line 61 are formed to intersect with each other, and a pixel selection thin film transistor 72 connected to the signal lines 51 and 61 is provided near the intersection. Hereinafter, the thin film transistor is abbreviated as TFT. The source 11 s of the pixel selection TFT 72 is connected to the display electrode 80 of the liquid crystal 21.
It is connected to the.

An auxiliary capacitor 85 for holding the voltage of the display electrode 80 for one field period is provided.
One terminal 86 of the auxiliary capacitor 85 is connected to the pixel selection TFT 7.
2 is connected to the source 11s, and a common potential is applied to the other electrode 87 to each display pixel.

Here, a scanning signal (H
When the (level) is applied, the pixel selection TFT 72 is turned on, an analog video signal is transmitted from the drain signal line 61 to the display electrode 80, and is held in the auxiliary capacitance 85. A video signal voltage applied to the display electrode 80 is applied to the liquid crystal 21 and the liquid crystal 21 is oriented according to the voltage, whereby a liquid crystal display can be obtained.

Therefore, liquid crystal display can be performed regardless of a moving image and a still image. When a still image is displayed on such a liquid crystal display device, for example, an image of a dry battery is displayed on a part of the liquid crystal display section of the mobile phone as a remaining battery level display for driving the mobile phone.

However, in the liquid crystal display device having the above-described configuration, even when a still image is displayed, the pixel selection TF is selected by the scanning signal in the same manner as when displaying a moving image.
It has been necessary to turn on T72 and rewrite the video signal to each display pixel.

Therefore, a driver circuit for generating drive signals such as a scanning signal and a video signal, and an external LSI for generating various signals for controlling the operation timing of the driver circuit always operate, so that a large power is always used. Had consumed. For this reason, a mobile phone or the like having only a limited power supply has a drawback that its usable time is shortened.

On the other hand, a liquid crystal display device having a static memory for each display pixel is disclosed in Japanese Patent Laid-Open No. 8-19420.
No. 5. Explaining with reference to a part of the publication, as shown in FIG. 7, this liquid crystal display device uses a memory in which two-stage inverters INV1 and INV2 are positively fed back, that is, a static memory for holding a digital video signal. By using it as a circuit, power consumption is reduced.

Here, the switch element 24 controls a resistance value between the reference line Vref and the display electrode 80 in accordance with the binary digital video signal held in the static memory,
The bias state of the liquid crystal 21 is adjusted. On the other hand, an AC signal Vcom is input to the common electrode. Ideally, the present device does not require refreshing to the memory if there is no change in the displayed image like a still image.

[0011]

As described above, a liquid crystal display device provided with a holding circuit (static type memory) for holding a digital video signal displays a low-gradation still image and consumes less power. It is suitable for reducing

However, the liquid crystal display device having the above configuration has the following problems. This problem will be described with reference to FIG. Now, the pixel selection TFT 72
Is at the “L (low)” level, and the “H (high)” level is held at the output node of the inverter INV1.

When "H" is output from the external circuit to the drain signal line 61 and "H" is written in the static memory from the held state, the N of the inverter INV2 is set to "N".
Since the channel type TFT is turned on, as shown by the broken line in FIG. 8A, the drain signal line 61 → the pixel selection TFT
Current flows through the path of 72 → N-channel TFT. In other words, the “H” level and the “L” level are in tension, and there is a possibility that erroneous writing may occur due to a decrease in “H”. In order to write “H” data normally, the potential of the source 11 s of the pixel selection TFT 72 must be
Although the condition that the threshold voltage is higher than 1 must be satisfied, this condition may not be satisfied because the source 11s of the pixel selection TFT 72 is reduced due to the presence of the current path.

A similar problem occurs when the "L" level is held at the output node of INV1 (FIG. 8).
(B)). When “L” is output from the external circuit to the drain signal line 61 and “L” is written to the static memory from this holding state, the inverter INV2
Since the P-channel type TFT is turned on, the P-channel type TFT → pixel selection TFT 72
→ Current flows through the path of the drain signal line 61. In order to normally write “L” data, the pixel selection TFT 72
Must satisfy the condition that the potential of the source 11s is lower than the threshold voltage of the inverter INV1.
This condition may not be satisfied due to the rise of the source 11s of the pixel selection TFT 72 due to the existence of the above current path.

However, conventionally, the sizes L and W (L is the channel length and W is the channel length) of the P-channel TFT and the N-channel TFT constituting the first and second inverter circuits of the holding circuit are designed to be the same. (For example, L /
W = 12/2), the threshold values of the first and second inverter circuits were the same.

For this reason, when writing video signal data to the holding circuit 110 under a low power supply voltage VDD, if a device such as a P-channel TFT whose characteristics such as the threshold value Vth and the on-current Ion vary, the above-described writing is performed. Are not satisfied, writing cannot be performed, and writing time becomes long.

Therefore, the present invention has been made in view of the above-mentioned problems of the prior art, and is provided in a display pixel.
An object of the present invention is to enable smooth writing to a holding circuit for holding video signal data.

[0018]

Means for Solving the Problems Among the inventions disclosed in the present application, the main ones are as follows.

According to the display device of the present invention, there are provided a plurality of gate signal lines arranged in one direction on a substrate, a plurality of drain signal lines arranged in a direction crossing the gate lines, and a scanning signal from the gate signal line. A pixel selection transistor for selecting a display pixel according to the above, and a holding circuit arranged in the display pixel and holding a video signal input from the drain signal line through the pixel selection transistor, according to the video signal held in the holding circuit. A display device that performs display by using a first inverter circuit to which a video signal from a drain signal line is input, and a second inverter circuit that positively feeds back an output of the first inverter circuit to an input. The threshold value VT1 of the first inverter circuit is set smaller than the threshold value VT2 of the second inverter circuit.

Assuming that "H" level is held at the output node of the first inverter circuit and "H" is written from the drain signal line to the holding circuit, as described above, And "L" level, the input potential of the first inverter circuit decreases, but according to the present invention, the threshold value VT1 of the first inverter circuit is equal to that of the second inverter circuit 2. Threshold value VT2
Therefore, the holding loop of the holding circuit is quickly formed, and the writing of the video signal data can be performed quickly and reliably.

The preferred embodiments of the present invention are as follows.

(A) The first and second inverter circuits are C
In the MOS inverter circuit, the L / W (L is the channel length and W is the channel width) of the P-channel transistor of the first inverter circuit is set to L / W (L) of the P-channel transistor of the second inverter circuit. Is greater than the channel length, and W is greater than the channel width.

(B) The first and second inverter circuits are C
In the MOS inverter circuit, the L / W (L is the channel length and W is the channel width) of the N-channel transistor of the first inverter circuit is set to L / W (L) of the N-channel transistor of the second inverter circuit. Is the channel length and W is the channel width.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A display device according to a first embodiment of the present invention will be described with reference to the circuit diagram of FIG. This embodiment corresponds to a case where the present invention is applied to a liquid crystal display device.

A gate signal line 51 and a drain signal line 61 are formed on an insulating substrate (not shown) so as to intersect, and a pixel selection thin film connected to both signal lines 51 and 61 near the intersection. A TFT 72 is provided.

The holding circuit 110 includes first and second inverter circuits INV1 and INV2 forming a positive feedback loop. The input of the first inverter circuit INV1 is connected to the source 11s of the pixel selection TFT 72, and the output is input to the second inverter circuit INV2. The output of the second inverter circuit INV2 is connected to the input of the first inverter circuit INV1.

The first inverter circuit INV1 has a CMO
An S-type inverter circuit comprising a P-channel TFT QP connected in cascade between a power supply voltage VDD and a ground voltage VSS.
1 and an N-channel TFT QN1. The second inverter circuit INV2 is also a CMOS inverter circuit, and includes a P-channel TFT QP2 and an N-channel TFT QN2 connected in cascade between the power supply voltage VDD and the ground voltage VSS.

According to the present embodiment, the following configuration is employed in order to smoothly perform writing to the holding circuit 110 that holds digital video signals.

The first configuration is composed of a first inverter circuit IN
The threshold value VT1 of V1 is equal to the second inverter circuit IN.
It is set smaller than the threshold value VT2 of V2. In order to set such a threshold value, the L / W (for example, L / W = 12 μm / 2 μm) of the P-channel TFT QP1 of the first inverter circuit INV1 is changed to the P-channel TFT QP2 of the second inverter circuit INV2. (For example, L / W = 10 μm / 2 μm). Also, the N-channel type TF of the first inverter circuit INV1
L / W of TQN1 (for example, L / W = 10 μm / 5 μ
m) is the N-channel type T of the second inverter circuit INV2.
L / W of FTQN2 (for example, L / W = 12 μm / 2 μ
m).

Assuming that the "H" level is held at the output node of the first inverter circuit INV1 and "H" is written from the drain signal line 61 to the holding circuit 110, as described above. , The "H" level and the "L" level are attracted to each other, and the input potential of the first inverter circuit INV1 decreases. However, since the threshold value VT1 of the first inverter circuit INV1 is set low, Even when the power supply voltage VDD supplied to the circuit 110 is low, the writing condition that the input potential is higher than VT1 is easily satisfied.

As a result, the first inverter circuit INV1
Is quickly inverted from "H" to "L". Further, since the threshold value VT2 of the second inverter circuit INV2 is set relatively high, the second inverter circuit INV1 receives the inversion of the output of the first inverter circuit INV1 from "H" to "L", Of the inverter circuit INV2 is easily inverted from “L” to “H”. Thus, the holding circuit 11
Since a new holding loop of 0 is formed promptly, writing of video signal data can be performed quickly and reliably.

When the pixel selection TFT 72 is of an N-channel type, the threshold Vtn of the pixel selection TFT 72 is set when writing an “H” digital video signal from the drain signal line 61.
Since a voltage loss occurs, the writing condition becomes severe, and the above-described configuration is particularly effective. On the other hand, when the “L” level is held at the output node of the first inverter circuit INV 1 and “L” is written from the drain signal line 61 to the holding circuit 110, such a voltage loss occurs. Does not occur. Therefore, no adverse effect occurs when the threshold value VT1 of the first inverter circuit INV1 is set low.

The second configuration is composed of a second inverter circuit IN
The output resistance of V2 is set to be higher than the ON resistance of the pixel selection TFT 72, and as will be described later, the drain signal line 6
The first inverter circuit INV1 is configured to be capable of inverting operation in accordance with the video signal data from the first inverter circuit INV1.

Specifically, the second inverter circuit INV
2 ON-resistance of N-channel TFT QN2
It is set larger than the on-resistance of the FT 72. In order to set such an on-resistance, for example, L / W (L is a channel length and W is a channel width) of the N-channel TFT QN2 may be larger than L / W of the pixel selection TFT 72.

When the "H" level is held at the output node of the first inverter circuit and an "H" level digital video signal is input from the drain signal line, the drain signal line 61 transfers to the N-channel TFT QN2. According to such a configuration, the pixel selection TFT 7 which is the input potential of the first inverter circuit INV1 is provided.
2 is connected to the first inverter circuit IN
Since the ON resistance is set so as to be equal to or higher than the threshold voltage of V1, the digital video signal is accurately written and held.

Similarly, the second inverter circuit INV
The ON resistance of the second P-channel TFT QP2 is set to be larger than the ON resistance of the pixel selection TFT 72. In order to set such an on-resistance, for example, the L / W (L is the channel length and W is the channel width) of the P-channel TFT QP2 may be larger than the L / W of the pixel selection TFT 72.

The "L" level is held at the output node of the first inverter circuit INV1, and the drain signal line 6
When a digital video signal of “L” level is input from P1 to P-channel type TF of the second inverter circuit INV2
There is a current path from TQP2 to the drain signal line,
According to this configuration, the on-resistance is set such that the potential of the source 11s of the pixel selection TFT 72, which is the input potential of the first inverter circuit INV1, is equal to or lower than the threshold voltage of the first inverter circuit INV1. Therefore, such a video signal is accurately written and held.

The binary digital video signal held in the holding circuit 110 is applied to the gates of the signal selection TFTs 121 and 122 of the signal selection circuit 120 as complementary output signals D and * D. The signal selection circuit 120 selects one of the signals A and B according to the output signals D and * D and applies the selected signal to the display electrode of the liquid crystal 21. Signal selection TFT12
Reference numerals 1 and 122 denote N-channel TFTs.

Next, the operation of the apparatus having the above configuration will be described. The scanning signal G from the gate signal line 51 rises to “H”, and the pixel selection TFT 72 turns on. Then, the digital video signal from the drain signal line 61 is supplied to the pixel selection TF.
The data is written to the holding circuit 110 via T72. Here, erroneous writing is prevented by the above-described configuration even when the level is pulled when switching the digital video signal from the drain signal line 61.

Next, a display device according to a second embodiment of the present invention will be described with reference to FIGS. This embodiment corresponds to a case where the present invention is applied to a liquid crystal display device. FIG.
FIG. 3 is a circuit diagram showing a configuration of one display pixel 200, and FIG.
Is an overall circuit diagram of a display device including the display pixel 200. The display device selects between an analog display mode for performing display (full-color moving image) according to an analog video signal and a digital display mode for performing display (still image) according to a digital video signal held by the holding circuit 110. A possible liquid crystal display device.

A plurality of gate signal lines 51 connected to a gate driver 50 for supplying a scanning signal are arranged in one direction on an insulating substrate 10 (not shown). A plurality of drain signal lines 61
Is arranged.

The drain signal line 61 has sampling transistors SP1, SP2, SP2 in accordance with the timing of the sampling pulse output from the drain driver 60.
, SPn are turned on, and the data signal (analog video signal or digital video signal) of the data signal line 62 is supplied.

The liquid crystal display panel 100 has a gate signal line 5
A plurality of display pixels 200 which are selected by the scanning signal from 1 and to which the data signal from the drain signal line 61 is supplied are arranged in a matrix.

Hereinafter, a detailed configuration of the display pixel 200 will be described. In the vicinity of the intersection between the gate signal line 51 and the drain signal line 61, a circuit selection circuit 40 including a P-channel TFT 41 and an N-channel TFT 42 is provided.
Both drains of the TFTs 41 and 42 are connected to a drain signal line 61, and both gates thereof are connected to a circuit selection signal line 88. One of the TFTs 41 and 42 is turned on in response to a selection signal from a circuit selection signal line 88. Further, a circuit selection circuit 43 is provided in a pair with the circuit selection circuit 40 as described later.

This makes it possible to select and switch between an analog display mode (corresponding to a full-color moving image) and a digital display mode (low power consumption, corresponding to a still image), which will be described later. Further, a pixel selection circuit 70 including an N-channel TFT 71 and an N-channel TFT 72 is arranged adjacent to the circuit selection circuit 40. Pixel selection TFT7
Reference numerals 1 and 72 denote circuit selection TFTs of the circuit selection circuit 40, respectively.
Gates 41 and 42 are connected in cascade, and a gate signal line 51 is connected to both gates. TFT7
Reference numerals 1 and 72 are configured so that both of them are simultaneously turned on in response to the scanning signal from the gate signal line 51.

Further, an auxiliary capacitor 85 for holding an analog video signal is provided. One electrode 86 of the auxiliary capacitor 85 is connected to the source 71 s of the TFT 71. The other electrode 87 is connected to a common auxiliary capacitance line SCL, and is supplied with a bias voltage Vsc. When the gate of the TFT 70 is opened and an analog video signal is applied to the liquid crystal 21, the signal must be held for one field period. However, the voltage of the signal of the liquid crystal 21 alone gradually decreases with time. Then, it appears as display unevenness, and good display cannot be obtained. Therefore, an auxiliary capacitor 85 is provided to hold the voltage for one field period.

Between the auxiliary capacitor 85 and the liquid crystal 21,
A P-channel TFT 44 of the circuit selection circuit 43 is provided, and is turned on and off simultaneously with the TFT 41 of the circuit selection circuit 43. In addition, T of the pixel selection circuit 70
A holding circuit 110 and a signal selection circuit 120 are provided between the FT 72 and the display electrode 80 of the liquid crystal 21.

The holding circuit 110, as shown in FIG.
It comprises first and second inverter circuits INV1 and INV2 forming a positive feedback loop. First inverter circuit I
The input of NV1 is the source 11s of the pixel selection TFT 72.
And its output is connected to a second inverter circuit INV2.
Has been entered. And the second inverter circuit INV
The output of the second inverter circuit INV1 is connected to the input of the first inverter circuit INV1.

In the digital display mode, the potential of the circuit selection signal line 88 becomes "H" and the gate signal line 5
When the scanning signal of “1” becomes “H”, the holding circuit 110 becomes writable.

A holding circuit 11 for holding a digital video signal
The following configuration similar to that of the first embodiment was adopted in order to enable writing to 0 smoothly. In the first configuration, the threshold value VT1 of the first inverter circuit INV1 is set smaller than the threshold value VT2 of the second inverter circuit INV2. The detailed configuration is the same as in the first embodiment, and a description thereof will be omitted.

In the second configuration, the output resistance of the second inverter circuit INV2 is set to be larger than the ON resistance of the pixel selection TFT 72, and the second resistance is set in accordance with the digital video signal from the drain signal line 61 as described later. One inverter circuit INV1 is configured to be capable of inverting operation.

More specifically, the second inverter circuit INV
2 ON-resistance of N-channel TFT QN2
It is set larger than the combined ON resistance of the FT 72 and the circuit selection TFT 42. In order to set such an on-resistance, for example, the L / W (L
Is the channel length, W is the channel width) is the pixel selection TFT7
2 may be larger than the sum of L / W of the circuit selection TFT 42 and L / W of the circuit selection TFT 42.

When the "H" level is held at the output node of the first inverter circuit and an "H" level digital video signal is input from the drain signal line, the pixel selection TFT 72 and the A current path to the N-channel TFT QN2 is generated via the circuit selection TFT 42. According to such a configuration, the input potential of the first inverter circuit INV1 becomes higher than the threshold voltage of the first inverter circuit INV1. Since the ON resistance is set so that the digital video signal is written, the digital video signal is accurately written and held.

Similarly, the second inverter circuit INV
The ON resistance of the second P-channel TFT QP2 is set to be larger than the combined ON resistance of the pixel selection TFT 72 and the circuit selection TFT. In order to set such on-resistance, for example, the L / W (L
Is the channel length, W is the channel width) is the pixel selection TFT7
2 and L / W of the circuit selection TFT 42.

The "L" level is held at the output node of the first inverter circuit INV1, and the drain signal line 6
When a digital video signal of “L” level is input from P1 to P-channel type TF of the second inverter circuit INV2
From T, a current path to the drain signal line is generated via the pixel selection TFT 72 and the circuit selection TFT 42. According to such a configuration, the input potential of the first inverter circuit INV1 is reduced by the input potential of the first inverter circuit INV1. Since the ON resistance is set so as to be equal to or lower than the threshold voltage, such a video signal is accurately written and held.

The signal selection circuit 120 is a circuit for selecting a signal in accordance with the digital video signal held in the holding circuit 110, and includes two N-channel TFTs 121 and 122.
It is composed of Since complementary output signals from the holding circuit 110 are applied to the gates of the TFTs 121 and 122, the TFTs 121 and 122 are turned on and off complementarily.

When the TFT 122 is turned on, the AC drive signal (signal B) is selected. When the TFT 121 is turned on, the counter electrode signal VCOM (signal A) is selected. Is supplied to the display electrode 80 which applies a voltage to the display electrode 80.

Next, a peripheral circuit of the display pixel 200 will be described. An external circuit board 90 separate from the insulating substrate 10 of the display pixel 200 is provided with a driver scan LS.
I91 is provided. The vertical start signal ST is output from the driver scan LSI 91 of the external circuit board 90.
V is input to the gate driver 50, and the horizontal start signal STH is input to the drain driver 60. Further, a video signal is input to the data line 62.

Next, a method of driving the display device having the above-described configuration will be described with reference to FIGS. FIG.
FIG. 6 is a timing chart when the liquid crystal display device is selected to be in the digital display mode. (1) In the case of the analog display mode When the analog display mode is selected according to the mode switching signal MD, a state is set in which an analog video signal is output to the data signal line 62 and the circuit selection signal line 88 is set.
Becomes “L”, and the TFT 4 of the circuit selection circuits 40 and 43
1, 44 are turned on.

Further, the sampling transistor SP according to the sampling signal based on the horizontal start signal STH
Is turned on, and the analog video signal of the data signal line 62 is supplied to the drain signal line 61.

A scanning signal is supplied to the gate signal line 51 based on the vertical start signal STV. When the TFT 71 is turned on in response to the scanning signal, the analog video signal Sig is transmitted from the drain signal line 61 to the display electrode 80 and is held in the storage capacitor 85. Display electrode 8
A video signal voltage applied to 0 is applied to the liquid crystal 21 and the liquid crystal 21 is oriented according to the voltage, whereby a liquid crystal display can be obtained.

This analog display mode is suitable for displaying a full-color moving image. However, power is constantly consumed by the LSI 91 of the external circuit board 90 and the drivers 50 and 60 to drive them. (2) Digital display mode When the digital display mode is selected according to the mode switching signal MD, the digital video signal is set to be output to the data signal line 62 and the circuit selection signal line 88 is set.
Becomes “H”, and the holding circuit 110 becomes operable. Further, the TFT 4 of the circuit selection circuits 40 and 43
1 and 44 are turned off, and the TFTs 42 and 45 are turned on.

The start signals STV and STH are input to the gate driver 50 and the drain driver 60 from the driver scan LSI 91 of the external circuit board 90, respectively. Sampling signals are sequentially generated in response thereto, and the sampling transistors SP1, SP2,..., SPn are sequentially turned on in accordance with the respective sampling signals to sample the digital video signal Sig and supply it to each drain signal line 61.

Here, the first row, that is, the gate signal line 51 to which the scanning signal G1 is applied will be described. First, the TFTs of the display pixels P11, P12,... P1n connected to the gate signal line 51 are turned on by the scanning signal G1 for one horizontal scanning period.

Focusing on the display pixel P11 in the first row and first column, the digital video signal S11 sampled by the sampling signal SP1 is input to the drain signal line 61. Then, the scanning signal G1 becomes “H” and the TFT 70
Is in the ON state, the drain signal D1 is written to the holding circuit 110.

At the time of writing, when data is rewritten, level competition occurs. However, according to the above-described configuration, erroneous writing is prevented.

The signal held by the holding circuit 110 is
The signal is input to the signal selection circuit 120 and the signal selection circuit 1
At 20, the signal A or the signal B is selected, the selected signal is applied to the display electrode 80, and the voltage is applied to the liquid crystal 21. By scanning from the gate signal line 51 to the gate signal line 51 of the last row in this manner, writing for one screen (one field period) is completed.

Thereafter, a display (display of a still image) based on the data held in the holding circuit 110 is performed. In the digital display mode, the supply of the voltage to the gate driver 50, the drain driver 60, and the external driver scan LSI 91 is stopped, and the driving thereof is stopped. The holding circuit 110 is always driven by supplying the voltages VDD and VSS, and the common electrode voltage is applied to the common electrode 32 by each signal A.
And B are supplied to the signal selection circuit 120.

That is, VDD and VSS for driving the holding circuit 110 are supplied to the holding circuit 110, the common electrode voltage VCOM (signal A) is applied to the common electrode, and the liquid crystal display panel 10
When 0 is a normally white (NW) signal, a voltage having the same potential as that of the counter electrode 32 is applied to the signal A, and an AC voltage (for example, 60 Hz) for driving the liquid crystal is applied to the signal B. is there. By doing so, one screen can be held and displayed as a still image. In addition, no voltage is applied to the other gate driver 50, drain driver 60, and external LSI 91.

At this time, when “H (high)” is input to the holding circuit 110 as a digital video signal to the drain signal line 61, the first TFT is selected in the signal selection circuit 120.
Since “L” is to be input to 121, the first T
The FT 121 is turned off and “H” is input to the other second TFT 122, so that the second TFT 12
2 turns on.

Then, the signal B is selected, and the voltage of the signal B is applied to the liquid crystal. That is, since the AC voltage of the signal B is applied and the liquid crystal rises by the electric field, the display can be observed as a black display on the NW display panel.

When “L” is input to the holding circuit 110 as a digital video signal to the drain signal line 61, “H” is input to the first TFT 121 in the signal selection circuit 120, The first TFT 121 is turned on, and “L” is input to the other second TFT 122, so that the second TFT 122 is turned off. Then, the signal A is selected, and the voltage of the signal A is applied to the liquid crystal. That is, since the same voltage as that of the counter electrode 32 is applied, no electric field is generated and the liquid crystal does not rise, so that N
On the W display panel, white display can be observed.

As described above, a still image can be displayed by writing and holding one screen, but in that case, the driving of each of the drivers 50 and 60 and the LSI 91 is stopped. Can be

As described above, according to the embodiment of the present invention, one liquid crystal display panel 100 can display a full-color moving image (in an analog display mode) and a digital gradation display (in a digital display mode). Two types of display can be supported. Further, malfunction of the holding circuit 110 at the time of writing can be prevented.

Further, in the above embodiment, the display device capable of selecting the analog display mode and the digital display mode has been described. However, the present invention writes a digital video signal,
It can be widely applied to a display device that includes a holding circuit 110 and displays an image in accordance with the holding signal.

The display device of the present invention is preferably applied to a reflection type liquid crystal display device among liquid crystal display devices. Therefore, the device structure of the reflection type liquid crystal display device will be described with reference to FIG.

As shown in FIG. 5, one of the insulating substrates 10
On the semiconductor layer 11 made of polycrystalline silicon,
A gate insulating film 12 is formed thereon, and a gate electrode 13 is formed on the gate insulating film 12 above the semiconductor layer 11.

A source 11 s and a drain 11 d are formed in the lower semiconductor layer 11 located on both sides of the gate electrode 13. An interlayer insulating film 14 is deposited on the gate electrode 13 and the gate insulating film 12, and a contact hole 15 is formed at a position corresponding to the drain 11d and a position corresponding to the source 11s. The drain 11d is connected to a drain electrode 16, and the source 11s is connected to a display electrode 19 via a contact hole 18 provided in a planarization insulating film 17 provided on the interlayer insulating film 14.

Each display electrode 19 formed on the flattening insulating film 17 is made of a reflective material such as aluminum (Al). An alignment film 20 made of polyimide or the like for aligning the liquid crystal 21 is formed on each of the display electrodes 19 and the flattening insulating film 17.

On the other insulating substrate 30, red (R),
A color filter 3 that exhibits green (G) and blue (B) colors
1. Counter electrode 32 made of a transparent conductive film such as ITO (Indium Tin Oxide), and alignment film 33 for aligning liquid crystal 21
Are formed in order. When color display is not performed, the color filter 31 is unnecessary.

The pair of insulating substrates 1 thus formed
The periphery of 0, 30 is adhered with an adhesive sealing material, and the gap formed thereby is filled with the liquid crystal 21 to complete the reflection type liquid crystal display device.

As shown by the dotted arrows in the drawing, external light incident from the observer 1 side sequentially enters from the counter electrode substrate 30,
The light is reflected by the display electrode 19 and emitted to the observer 1 side, so that the display can be observed by the observer 1.

As described above, the reflection type liquid crystal display device is a method of observing a display by reflecting external light, and it is necessary to use a so-called backlight on the side opposite to the observer side like a transmission type liquid crystal display device. Therefore, power for lighting the backlight is not required. Therefore, it is preferable that the display device of the present invention is a reflective liquid crystal display device which does not require a backlight and is suitable for low power consumption.

In the above-described embodiment, the case where the common electrode voltage and the voltages of the signals A and B are applied during the entire dot scan period of one screen has been described. However, the present invention is not limited to this. Rather, it is not necessary to apply these voltages even during this period. However, in order to reduce power consumption, it is preferable not to apply the voltage.

In the above-described embodiment, the case where a 1-bit digital data signal is input in the digital display mode has been described. However, the present invention is not limited to this. It is possible to apply even in the case of.

By doing so, multi-gradation display can be performed. At that time, it is necessary to set the number of holding circuits and signal selection circuits according to the number of input bits.

In the above-described embodiment, the case where a still image is displayed on a part of the liquid crystal display panel has been described. However, the present invention is not limited to this, and a still image is displayed on all display pixels. It is also possible to achieve the specific effects of the present invention.

In the above embodiment, the case of the reflection type liquid crystal display device has been described.
By arranging a transparent electrode in a region excluding T, the holding circuit, the signal selection circuit, and the signal wiring, it can be used for a transmission type liquid crystal display device. In addition, when used in a transmissive liquid crystal display device, after one screen is displayed, the supply of voltage to the gate driver 50, the drain driver 60, and the external driver scan LSI 91 is stopped to reduce the consumption. The power can be reduced.

[0089]

According to the display device of the present invention, the threshold value of the first inverter circuit constituting the holding circuit is set smaller than the threshold value of the second inverter circuit. A video signal can be smoothly written through the transistor.

Thus, even when the power supply voltage supplied to the display device is low, it is possible to prevent erroneous writing of the video signal and decrease in the writing speed. As a result, the voltage of the display device can be reduced, so that a display device with low power consumption can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing one display pixel of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram showing one display pixel of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of the entire device when a display device according to a second embodiment of the present invention is applied to a liquid crystal display device.

FIG. 4 is a timing chart when the liquid crystal display device is selected in a digital display mode.

FIG. 5 is a sectional view of a reflection type liquid crystal display device.

FIG. 6 is a circuit configuration diagram of a liquid crystal display device according to a conventional example.

FIG. 7 is another circuit configuration diagram of a liquid crystal display device according to a conventional example.

FIG. 8 is a circuit configuration diagram showing a problem of the liquid crystal display device according to the conventional example.

[Explanation of symbols]

 Reference Signs List 21 liquid crystal 40 circuit selection circuit 41, 42 circuit selection TFT 43 circuit selection circuit 50 gate driver 51 gate signal line 60 drain driver 61 drain signal line 62 data signal line 70 pixel selection circuit 71, 72 pixel selection TFT 80 display electrode 85 auxiliary capacitance 88 circuit selection signal line 100 liquid crystal display panel 110 holding circuit 120 signal selection circuit 200 display pixel

────────────────────────────────────────────────── ─── of the front page continued (51) Int.Cl. ⁷ identification mark FI theme Court Bu (reference) G09G 3/36 G09G 3/36 F-term (reference) 2H092 JA21 JB42 JB43 NA01 PA06 PA08 2H093 NA16 NC32 NC40 ND33 ND39 5C006 BB16 BC06 BC20 BF06 BF27 BF32 BF34 BF37 EB05 FA46 FA47 5C080 AA10 BB05 DD09 DD26 FF11 JJ03 JJ04 JJ06

Claims (7)

[Claims] A plurality of gate signal lines arranged in one direction on a substrate, a plurality of drain signal lines arranged in a direction intersecting the gate lines, and a display pixel based on a scanning signal from the gate signal lines. And a holding circuit that is arranged in the display pixel and holds a video signal input from the drain signal line through the pixel selection transistor. The video signal held by the holding circuit A display device that performs display in response to the signal, wherein the holding circuit has a first inverter circuit to which a video signal from the drain signal line is input, and a second inverter that positively feeds back an output of the first inverter circuit to an input. Wherein the threshold value of the first inverter circuit is set smaller than the threshold value of the second inverter circuit. Location. 2. The method according to claim 1, wherein the first and second inverter circuits are C
A MOS inverter circuit, wherein L / W (L is a channel length and W is a channel width) of a P-channel transistor of the first inverter circuit is set to L / W (L) of a P-channel transistor of the second inverter circuit. Is the channel length, W
2. The display device according to claim 1, wherein the width is larger than a channel width. 3. The method according to claim 1, wherein the first and second inverter circuits are C
A MOS inverter circuit, wherein L / W (L is a channel length and W is a channel width) of an N-channel transistor of the first inverter circuit is set to L / W (L) of an N-channel transistor of the second inverter circuit. Is the channel length, W
3. The display device according to claim 2, wherein the width is smaller than a channel width. 4. The display device according to claim 3, wherein the pixel selection transistor is an N-channel transistor. 5. A plurality of gate signal lines arranged in one direction on a substrate, a plurality of drain signal lines arranged in a direction intersecting with the gate lines, and a display pixel based on a scanning signal from the gate signal lines. A pixel selection transistor for selecting a pixel, a display electrode disposed in the display pixel, and a first display circuit disposed for each display pixel and sequentially supplying a video signal input from the drain signal line to the display electrode. And a holding circuit that is arranged corresponding to the display pixel and holds a video signal input from a drain signal line through the pixel selection transistor, and displays a voltage signal corresponding to the signal held by the holding circuit in the display. A second display circuit for supplying an electrode; and a cascade connection with the pixel selection transistor, for selecting one of the first and second display circuits in accordance with a circuit selection signal. And a path selection transistor, wherein the holding circuit further includes a first inverter circuit to which a video signal from the drain signal line is input, and a second inverter that positively feeds back an output of the first inverter circuit to an input. And a threshold value of the first inverter circuit is set smaller than a threshold value of the second inverter circuit. 6. The first and second inverter circuits are C
A MOS inverter circuit, wherein L / W (L is a channel length and W is a channel width) of a P-channel transistor of the first inverter circuit is set to L / W (L) of a P-channel transistor of the second inverter circuit. Is the channel length, W
6. The display device according to claim 5, wherein the width is larger than the channel width. 7. The method according to claim 1, wherein the first and second inverter circuits are C
A MOS inverter circuit, wherein L / W (L is a channel length and W is a channel width) of an N-channel transistor of the first inverter circuit is set to L / W (L) of an N-channel transistor of the second inverter circuit. Is the channel length, W
7. The display device according to claim 6, wherein the width is smaller than a channel width.