JP2011257593A - Driving method for electrophoretic display device, electrophoretic display device, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driving method for an electrophoretic display device that prevents deterioration of a latch circuit in a pixel and is capable of obtaining outstanding reliability.SOLUTION: A driving method for an electrophoretic display device includes a first step S101 of inputting an electric potential of a first control wire or a second control wire to a pixel electrode and driving an electrophoretic element of a pixel in a state in which a positive image signal corresponding to a single image is held in a plurality of latch circuits; and a second step S102 of causing the plurality of latch circuits to hold an inverted image signal corresponding to a reverse image of the single image for a specified period.

Description

  The present invention relates to an electrophoretic display device driving method, an electrophoretic display device, and an electronic apparatus.

  As an active matrix type electrophoretic display device, one having a switching transistor and a latch circuit (SRAM; Static Random Access Memory) in a pixel is known (see Patent Document 1). The display device described in Patent Document 1 has a configuration in which a first substrate on which pixel electrodes are formed is bonded to a second substrate having an electrophoretic element in which microcapsules are arranged so as to sandwich the electrophoretic element. Adopted.

JP 2003-84314 A

  By the way, TFTs (thin film transistors) have a problem of causing degradation such as threshold shift, decrease of on-current, increase of off-current, etc. by applying a DC bias, and it is also known that these threshold shifts are accelerated by temperature. (BT (Bias-Temperature) stress degradation). In the latch circuit provided in the pixel of the electrophoretic display device, when the threshold shift of the TFT constituting the circuit proceeds excessively, writing of the image signal to the latch circuit may fail, resulting in a display defect. There is sex.

  The present invention has been made in view of the above-described problems of the prior art, and can prevent deterioration of a latch circuit in a pixel and obtain excellent reliability. An object is to provide an electrophoretic display device.

  According to the driving method of the electrophoretic display device of the invention, an electrophoretic element including electrophoretic particles is sandwiched between a pair of substrates, a plurality of pixels, a first control line connected to the pixels, and a second control line are connected. A display unit having a control line, and each pixel includes a pixel electrode, a pixel switching element, a latch circuit connected between the pixel electrode and the pixel switching element, and an output of the latch circuit And a switch circuit that switches connection between the pixel electrode and the first and second control lines based on the first and second control lines. In a state where a positive image signal corresponding to the image of the first pixel is held, a potential of the first control line or the second control line is input to the pixel electrode to drive the electrophoretic element of the pixel. And the steps A second step of a predetermined period of time holds the inverted image signal corresponding to the reverse image of the keys of the image into a plurality of said latch circuit, and having a.

  According to this driving method, the BT stress deterioration caused by the DC bias applied to the transistors constituting the latch circuit in the first step is applied, and the DC bias having the opposite polarity to the DC bias is applied in the second step. Can be recovered. Thereby, deterioration of the latch circuit can be prevented, and excellent reliability can be obtained.

The period in which the latch circuit holds the normal image signal in the first step and the period in which the latch circuit holds the inverted image signal in the second step may be equal in length. .
According to this driving method, the DC bias application period in the first step and the DC bias period in the second step can be set to the same length, so that BT stress deterioration can be more reliably and efficiently performed in a short time. Can be recovered.

In the second step, the electrophoretic element may not be driven.
According to this driving method, it is possible to recover the BT stress deterioration by executing the second step while maintaining the state of the display unit.

In the second step, the potential input to the first control line is the potential input to the second control line in the first step, while being input to the second control line. A method may be used in which the potential is the potential input to the first control line in the first step.
According to this driving method, the images displayed on the display unit can be matched in the first step and the second step, and therefore the second step can be executed during the image display operation.

The electrophoretic display device includes a temperature measurement unit that measures the temperature of the display unit, and the execution or skip of the second step is selected based on the temperature measured by the temperature measurement unit. Also good.
According to this driving method, execution or non-execution of the second step is selected based on the temperature of the display unit, so that the second step is not executed in a relatively low temperature environment where BT stress deterioration does not occur. be able to. As a result, it is possible to avoid a decrease in operability associated with the execution of the second step, and it is possible to reliably recover the BT stress deterioration in a high temperature environment where the BT stress deterioration is likely to occur.

When the power supply of the latch circuit is cut off, a method may be used in which the power supply terminal is electrically disconnected after a reference potential is input to the power supply terminal of the latch circuit.
According to this driving method, before the power source of the latch circuit is cut off, the charge can be removed from the transistor of the latch circuit so that no DC bias is applied. Thereby, it is possible to prevent the BT stress deterioration due to the DC bias due to the residual charge.

  An electrophoretic display device of the present invention includes an electrophoretic element including electrophoretic particles sandwiched between a pair of substrates, a plurality of pixels, and a first control line and a second control line connected to the pixels. For each pixel, based on a pixel electrode, a pixel switching element, a latch circuit connected between the pixel electrode and the pixel switching element, and an output of the latch circuit An electrophoretic display device comprising: a switch circuit that switches connection between the pixel electrode and the first and second control lines; and a control unit that controls the display unit. The potential of the first control line or the second control line is input to the pixel electrode in a state where a positive image signal corresponding to one image is held in the plurality of latch circuits of the display unit, Drive the electrophoretic element of the pixel Characterized in that it operates in a first operation for, and a second operation to hold predetermined period into a plurality of the latch circuits inverted image signal corresponding to the reverse image of the first image run.

  According to this configuration, the BT stress deterioration caused by the DC bias applied to the transistors constituting the latch circuit in the first operation is applied to the DC bias having the opposite polarity to the DC bias in the second operation. Can be recovered. Thereby, deterioration of the latch circuit can be prevented, and excellent reliability can be obtained.

The period during which the latch circuit holds the normal image signal in the first operation and the period during which the latch circuit holds the inverted image signal in the second operation may have the same length. .
According to this configuration, since the DC bias application period in the first operation and the DC bias period in the second operation can be made equal in length, BT stress degradation can be recovered more reliably and efficiently in a short time. Thus, an electrophoretic display device can be obtained.

The control unit may not drive the electrophoretic element in the second operation.
According to this configuration, the electrophoretic display layer can perform the second operation while maintaining the state of the display unit, and can recover the BT stress deterioration.

The control unit inputs a first potential to the first control line and a second potential to the second control line in the first operation, and the first control line in the second operation. The second potential may be input to the second control line, and the first potential may be input to the second control line.
According to this configuration, since the images displayed on the display unit can be matched between the first operation and the second operation, the second operation can be executed during the image display operation.

A temperature measurement unit that measures the temperature of the display unit may be provided, and the control unit may select execution or skipping of the second operation based on the temperature measured by the temperature measurement unit. .
According to this configuration, since execution or non-execution of the second operation is selected based on the temperature of the display unit, the second operation is not performed in a relatively low temperature environment where BT stress deterioration does not occur. Can do. Accordingly, it is possible to avoid a decrease in operability associated with the execution of the second operation, and it is possible to reliably recover the BT stress deterioration in a high temperature environment where the BT stress deterioration is likely to occur.

The control unit may electrically disconnect the power supply terminal after inputting a reference potential to the power supply terminal of the latch circuit when shutting off the power supply of the latch circuit.
According to this configuration, before the power supply of the latch circuit is shut off, the charge can be removed from the transistor of the latch circuit so that no DC bias is applied. Thereby, it is possible to prevent the BT stress deterioration due to the DC bias due to the residual charge.

An electronic apparatus according to the present invention includes the electrophoretic display device described above.
According to this configuration, it is possible to provide an electronic device including a display unit having excellent reliability.

1 is a schematic configuration diagram of an electrophoretic display device according to a first embodiment. The circuit block diagram of a pixel. Sectional drawing of an electrophoretic display device and a microcapsule. Operation | movement explanatory drawing of an electrophoretic element. The block diagram which shows the detail of a controller (control part). The flowchart which shows the drive method of 1st Embodiment. 7 is a timing chart corresponding to FIG. Explanatory drawing which shows the state transition of image data and a display part. Explanatory drawing of BT stress deterioration in a latch circuit. The flowchart which shows the drive method of 2nd Embodiment. 11 is a timing chart corresponding to FIG. The perspective view which shows the specific example of an electronic device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The scope of the present invention is not limited to the following embodiment, and can be arbitrarily changed within the scope of the technical idea of the present invention. Moreover, in the following drawings, in order to make each structure easy to understand, the actual structure may be different from the scale, number, or the like in each structure.

(First embodiment)
FIG. 1 is a schematic configuration diagram of an electrophoretic display device according to the first embodiment.
The electrophoretic display device 100 includes a display unit 5 in which a plurality of pixels 40 are arranged in a matrix. Around the display unit 5, a scanning line driving circuit 61, a data line driving circuit 62, a controller (control unit) 63, and a common power supply modulation circuit 64 are arranged. The scanning line driving circuit 61, the data line driving circuit 62, and the common power supply modulation circuit 64 are each connected to the controller 63. The controller 63 comprehensively controls these based on image data and synchronization signals supplied from the host device.

  A plurality of scanning lines 66 extending from the scanning line driving circuit 61 and a plurality of data lines 68 extending from the data line driving circuit 62 are formed in the display unit 5, and the pixels 40 are provided corresponding to the intersection positions thereof. It has been.

  The scanning line driving circuit 61 is connected to each pixel 40 via m scanning lines 66 (Y1, Y2,..., Ym). Under the control of the controller 63, the first to mth rows are connected. The scanning lines 66 are sequentially selected, and a selection signal defining the ON timing of the selection transistor 41 (see FIG. 2) provided in the pixel 40 is supplied via the selected scanning line 66.

The data line driving circuit 62 is connected to each pixel 40 via n data lines 68 (X1, X2,..., Xn), and corresponds to each pixel 40 under the control of the controller 63. An image signal defining 1-bit pixel data is supplied to the pixel 40.
In the present embodiment, a low level (L) image signal is supplied to the pixel 40 when the pixel data “0” is defined, and a high level (H) image is defined when the pixel data “1” is defined. It is assumed that a signal is supplied to the pixel 40.

  The display unit 5 is also provided with a low potential power line 49, a high potential power line 50, and a common electrode wiring 55 extending from the common power modulation circuit 64, and each wiring is connected to the pixel 40. The common power supply modulation circuit 64 generates various signals to be supplied to each of the wires under the control of the controller 63, and electrically connects and disconnects these wires (high impedance (Hi-Z)). )I do.

FIG. 2 is a circuit configuration diagram of the pixel 40.
The pixel 40 includes a selection transistor 41 (pixel switching element) made of a TFT (Thin Film Transistor), a latch circuit (memory circuit) 70, a switch circuit 80, an electrophoretic element 32, a pixel electrode 35, and a common electrode. 37 is provided. A scanning line 66, a data line 68, a low-potential power line 49, a high-potential power line 50, a first control line 91, and a second control line 92 are connected to the pixel 40. . The pixel 40 has an SRAM (Static Random Access Memory) type configuration in which the latch circuit 70 holds an image signal as a potential.

  The selection transistor 41 is a pixel switching element composed of an N-MOS transistor (Negative Metal Oxide Semiconductor Transistor). The selection transistor 41 has a gate connected to the scanning line 66, a source connected to the data line 68, and a drain connected to the data input terminal N 1 of the latch circuit 70.

  The latch circuit 70 includes a transfer inverter 70t and a feedback inverter 70f. Both the transfer inverter 70t and the feedback inverter 70f are C-MOS inverters. The transfer inverter 70t and the feedback inverter 70f have a loop structure in which the other output terminal is connected to each other's input terminal, and each inverter has a high potential connected via a high potential power supply terminal PH. A power supply voltage is supplied from the power supply line 50 and the low potential power supply line 49 connected via the low potential power supply terminal PL.

  The transfer inverter 70t has a P-MOS transistor 71 (Positive Metal Oxide Semiconductor Transistor) and an N-MOS transistor 72, each drain of which is connected to the data output terminal N2. The source of the P-MOS transistor 71 is connected to the high potential power supply terminal PH, and the source of the N-MOS transistor 72 is connected to the low potential power supply terminal PL. The gates of the P-MOS transistor 71 and the N-MOS transistor 72 (input terminal of the transfer inverter 70t) are connected to the data input terminal N1 (output terminal of the feedback inverter 70f).

  The feedback inverter 70f includes a P-MOS transistor 73 and an N-MOS transistor 74 whose drains are connected to the data input terminal N1. The gates of the P-MOS transistor 73 and the N-MOS transistor 74 (input terminal of the feedback inverter 70f) are connected to the data output terminal N2 (output terminal of the transfer inverter 70t).

The switch circuit 80 includes a first transmission gate TG1 and a second transmission gate TG2.
The first transmission gate TG1 includes a P-MOS transistor 81 and an N-MOS transistor 82. The sources of the P-MOS transistor 81 and the N-MOS transistor 82 are connected to the first control line 91, and the drains of the P-MOS transistor 81 and the N-MOS transistor 82 are connected to the pixel electrode 35. The gate of the P-MOS transistor 81 is connected to the data input terminal N1 of the latch circuit 70, and the gate of the N-MOS transistor 82 is connected to the data output terminal N2 of the latch circuit 70.

  The second transmission gate TG 2 includes a P-MOS transistor 83 and an N-MOS transistor 84. The sources of the P-MOS transistor 83 and the N-MOS transistor 84 are connected to the second control line 92, and the drains of the P-MOS transistor 83 and the N-MOS transistor 84 are connected to the pixel electrode 35. The gate of the P-MOS transistor 83 is connected to the data output terminal N2 of the latch circuit 70, and the gate of the N-MOS transistor 84 is connected to the data input terminal N1 of the latch circuit 70. Further, the electrophoretic element 32 is sandwiched between the pixel electrode 35 and the common electrode 37.

In the pixel 40 having the above configuration, a low level (L) image signal (pixel data “0”) is stored in the latch circuit 70, and a high level (H) signal is output from the data output terminal N2. The first transmission gate TG1 is turned on, and the potential S1 supplied via the first control line 91 is input to the pixel electrode 35.
On the other hand, when a high level (H) image signal (pixel data “1”) is stored in the latch circuit 70 and a low level (L) signal is output from the data output terminal N2, the second transmission gate TG2 The potential S <b> 2 supplied through the second control line 92 is input to the pixel electrode 35.
The electrophoretic element 32 is driven based on the potential difference between the potentials S1 and S2 input to the pixel electrode 35 and the potential Vcom input to the common electrode 37 via the common electrode wiring 55 (FIG. 1). Thus, the pixel 40 is displayed with a gradation corresponding to the input image signal.

Next, FIG. 3A is a partial cross-sectional view of the electrophoretic display device 100 in the display unit 5.
The electrophoretic display device 100 includes a configuration in which an electrophoretic element 32 formed by arranging a plurality of microcapsules 20 is sandwiched between an element substrate (first substrate) 30 and a counter substrate (second substrate) 31. Yes.

In the display unit 5, the circuit layer 34 on which the scanning line 66, the data line 68, the selection transistor 41, the latch circuit 70, and the like illustrated in FIG. 1 and FIG. A plurality of pixel electrodes 35 are arranged on the circuit layer 34.
The element substrate 30 is a substrate made of glass, plastic, or the like and is not required to be transparent because it is disposed on the side opposite to the image display surface. The pixel electrode 35 has a voltage applied to an electrophoretic element 32 formed by laminating nickel plating and gold plating on a Cu (copper) foil in this order, Al (aluminum), ITO (indium tin oxide), or the like. Is an electrode to which is applied.

On the other hand, a planar common electrode 37 facing the plurality of pixel electrodes 35 is formed on the electrophoretic element 32 side of the counter substrate 31, and the electrophoretic element 32 is provided on the common electrode 37.
The counter substrate 31 is a substrate made of glass, plastic, or the like, and is a transparent substrate because it is disposed on the image display side. The common electrode 37 is an electrode for applying a voltage to the electrophoretic element 32 together with the pixel electrode 35, and is formed of MgAg (magnesium silver), ITO (indium tin oxide), IZO (indium zinc oxide) or the like. It is a transparent electrode.
The electrophoretic element 32 and the pixel electrode 35 are bonded via the adhesive layer 33, so that the element substrate 30 and the counter substrate 31 are bonded.

  In general, the electrophoretic element 32 is formed in advance on the counter substrate 31 side, and is handled as an electrophoretic sheet including the adhesive layer 33. In the manufacturing process, the electrophoretic sheet is handled in a state where a protective release sheet is attached to the surface of the adhesive layer 33. And the display part 5 is formed by sticking the said electrophoretic sheet which peeled the release sheet with respect to the element board | substrate 30 (The pixel electrode 35, various circuits, etc.) which were manufactured separately. For this reason, the adhesive layer 33 exists only on the pixel electrode 35 side.

  FIG. 3B is a schematic cross-sectional view of the microcapsule 20. The microcapsule 20 has a particle size of, for example, about 50 μm and encloses therein a dispersion medium 21, a plurality of white particles (electrophoretic particles) 27, and a plurality of black particles (electrophoretic particles) 26. It is a spherical body. As shown in FIG. 3A, the microcapsule 20 is sandwiched between the common electrode 37 and the pixel electrode 35, and one or more microcapsules 20 are disposed in one pixel 40.

The outer shell (wall film) of the microcapsule 20 is formed using a transparent polymer resin such as acrylic resin such as polymethyl methacrylate and polyethyl methacrylate, urea resin, and gum arabic.
The dispersion medium 21 is a liquid that disperses the white particles 27 and the black particles 26 in the microcapsules 20. Examples of the dispersion medium 21 include water, alcohol solvents (methanol, ethanol, isopropanol, butanol, octanol, methyl cellosolve, etc.), esters (ethyl acetate, butyl acetate, etc.), ketones (acetone, methyl ethyl ketone, methyl isobutyl ketone, etc.). ), Aliphatic hydrocarbons (pentane, hexane, octane, etc.), alicyclic hydrocarbons (cyclohexane, methylcyclohexane, etc.), aromatic hydrocarbons (benzene, toluene, benzenes having a long-chain alkyl group ( Xylene, hexylbenzene, hebutylbenzene, octylbenzene, nonylbenzene, decylbenzene, undecylbenzene, dodecylbenzene, tridecylbenzene, tetradecylbenzene)), halogenated hydrocarbons (methylene chloride, chloroform, tetrachloride) Element, and 1,2-dichloroethane), can be exemplified a carboxylate, it may be other oils. These substances can be used alone or as a mixture, and a surfactant or the like may be further blended.

The white particles 27 are particles (polymer or colloid) made of a white pigment such as titanium dioxide, zinc white, and antimony trioxide, and are used, for example, by being negatively charged. The black particles 26 are particles (polymer or colloid) made of a black pigment such as aniline black or carbon black, and are used by being charged positively, for example.
These pigments include electrolytes, surfactants, metal soaps, resins, rubbers, oils, varnishes, compound charge control agents, titanium-based coupling agents, aluminum-based coupling agents, silanes as necessary. A dispersant such as a system coupling agent, a lubricant, a stabilizer, and the like can be added.
Further, instead of the black particles 26 and the white particles 27, for example, pigments such as red, green, and blue may be used. According to such a configuration, red, green, blue, or the like can be displayed on the display unit 5.

FIG. 4 is an operation explanatory diagram of the electrophoretic element. 4A shows a case where the pixel 40 displays white, and FIG. 4B shows a case where the pixel 40 displays black.
In the case of white display shown in FIG. 4A, the common electrode 37 is held at a relatively high potential and the pixel electrode 35 is held at a relatively low potential. As a result, the negatively charged white particles 27 are attracted to the common electrode 37, while the positively charged black particles 26 are attracted to the pixel electrode 35. As a result, when this pixel is viewed from the common electrode 37 side which is the display surface side, white (W) is recognized.
In the case of black display shown in FIG. 4B, the common electrode 37 is held at a relatively low potential, and the pixel electrode 35 is held at a relatively high potential. As a result, the positively charged black particles 26 are attracted to the common electrode 37, while the negatively charged white particles 27 are attracted to the pixel electrode 35. As a result, when this pixel is viewed from the common electrode 37 side, black (B) is recognized.

FIG. 5 is a block diagram showing details of the controller 63 provided in the electrophoretic display device 100.
The controller 63 includes a control circuit 161 as a CPU (Central Processing Unit), a memory 162 (storage unit), a data buffer 164, a frame memory 165, and an image signal generation circuit 166. The controller 63 is connected to the temperature sensor 6 (temperature measurement unit) connected to the display unit 5 and the drive circuit 69 (scanning line drive circuit 61, data line drive circuit 62, common power supply modulation circuit 64). .

  The control circuit 161 generates control signals (timing pulses) such as a clock signal CLK, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync, and supplies these control signals to each circuit arranged around the control circuit 161. The control circuit 161 is connected to the memory 162, the data buffer 164, the image signal generation circuit 166, and the temperature sensor 6.

  The memory 162 is a storage unit configured to be readable and writable from the control circuit 161 and at least writable from the image signal generation circuit 166. The memory 162 stores programs executed in the control circuit 161, setting values (mode setting values and volume values) necessary for operation control of each circuit, and the like, for example, setting values of driving sequences for each operation mode Is stored as a LUT (Look Up Table). In the present embodiment, the memory 162 includes a plurality of areas for storing copies of the frame memory supplied from the image signal generation circuit 166, and is configured to be able to save the display history of the electrophoretic display device.

  The data buffer 164 is an interface unit with the host device in the controller 63, holds the image data D input from the host device, and transmits the image data D to the control circuit 161.

The frame memory 165 is a readable / writable memory having a memory space corresponding to the arrangement of the pixels 40 of the display unit 5. The image signal generation circuit 166 converts the image data D supplied from the control circuit 161 into an image signal by developing it corresponding to the pixel arrangement of the display unit 5 according to the control signal, and writes the image signal in the frame memory 165. The image signal written in the frame memory 165 is transmitted to the drive circuit 69 (data line drive circuit 62) via the image signal generation circuit 166.
The data line driving circuit 62 latches the image signal transmitted from the frame memory 165 one line at a time based on the control signal supplied via the image signal generation circuit 166. Then, the latched image signal is supplied to the data line 68 in synchronization with the sequential selection operation of the scanning line 66 by the scanning line driving circuit 61.

  The temperature sensor 6 is a sensor in which the amount of electricity such as a resistance value or a capacitance value changes according to the temperature, and transmits the detected temperature to the control circuit 161. As the temperature sensor 6, for example, a thermistor or a thermocouple can be used. Since the signal input from the temperature sensor 6 to the control circuit 161 is an analog detection signal, the controller 63 or the control circuit 161 includes an AD converter that AD converts the analog detection signal into encoded temperature data. It is preferable.

One or a plurality of temperature sensors 6 are provided in the electrophoretic display device 100, and are provided at positions where the temperature of the display unit 5 shown in FIGS. 1 and 3 can be measured.
For example, the temperature sensor 6 can be attached to the back surface of the element substrate 30 shown in FIG. Moreover, when the flat area of the display part 5 is large, etc., you may attach the temperature sensor 6 to two or more places near the center of the display part 5, and a peripheral part. The temperature information acquired by the control circuit 161 when a plurality of temperature sensors 6 are attached may be a simple average value or a weighted average value of a plurality of temperatures measured by the plurality of temperature sensors 6, or a plurality of temperatures. May be the highest value.

[Driving method]
Next, a driving method of the electrophoretic display device of this embodiment will be described with reference to FIGS.
FIG. 6 is a flowchart showing a method for driving the electrophoretic display device 100. FIG. 7 is a timing chart corresponding to the flowchart of FIG. FIG. 8 is an explanatory diagram showing image data and state transition of the display unit in the driving method of the present embodiment.

  FIG. 6 shows a flow in the case where the character “A” is displayed on the display unit 5 as shown in FIG. 8. FIG. 7 shows the potential Vcom of the common electrode 37, the potential S1 of the first control line 91, the potential S2 of the second control line 92, and the potential Vdd of the high potential power supply line 50.

As shown in FIG. 6, the driving method according to the present embodiment includes a first step S101, a temperature determination step ST15, and a second step S102.
FIG. 8 (s) shows the image data D1 transferred to the display unit 5 in the first step S101 and the image data D2 transferred in the second step S102. FIG. 8B shows the display state of the display unit 5 corresponding to the execution results of the first step S101 and the second step S102.

The first step S101 includes a normal image signal transfer step ST11 and an image display step ST12. In the display unit 5 before the normal image signal transfer step ST11, each circuit is in a power-off state.
First, when the process proceeds to the normal image signal transfer step ST11, power is supplied to the scanning line driving circuit 61, the data line driving circuit 62, and the common power supply modulation circuit 64, and the wiring connected to each circuit is in a state where potential can be supplied. . In addition, power is supplied to the latch circuit 70 of the pixel 40 via the high potential power supply line 50 and the low potential power supply line 49, and the image signal can be stored.

  In the present embodiment, the low level (L) potential in the data line 68 and the low level potential VL in the low potential power supply line 49 are both assumed to be the ground potential GND (0 V). Further, the potential VH shown in FIG. 7 is a high-level potential VH (for example, 15V) for image display, and the potential VM is a high-level potential VM (for example, 5V) for image signal input.

  When each circuit of the electrophoretic display device 100 is turned on, an image signal is input to the latch circuit 70 of each pixel 40. That is, a high-level (H; for example, 7 V) pulse that is a selection signal is input to the scanning line 66, the selection transistor 41 connected to the scanning line 66 is turned on, and the data line 68 and the latch circuit 70 are connected. Connected. As a result, the image signal supplied via the data line 68 is input to the data input terminal N 1 of the latch circuit 70.

  The image signal transferred to the pixel 40 in the first step S101 is an image signal corresponding to the image data D1 shown in FIG. 8A (an image in which a black character “A” is written on a white background). Image signal). In FIG. 8, a white area is an area where pixel data “0” (corresponding to a low level image signal) is arranged, and a black area is where pixel data “1” (corresponding to a high level image signal) is arranged. This is the area that has been

  In the pixel 40 shown in FIG. 2, when a high level (for example, 5V) image signal is input from the data line 68 to the latch circuit 70 via the selection transistor 41, the potential of the data input terminal N1 is set to a high level for image signal input. The level potential and the potential of the data output terminal N2 become a low level potential (ground potential). As a result, in the pixel 40, the second transmission gate TG2 is turned on, and the second control line 92 and the pixel electrode 35 are electrically connected.

  On the other hand, when a low level (ground potential) image signal is input from the data line 68 to the latch circuit 70 via the selection transistor 41, the data input terminal N1 has a low level potential (ground potential) and the data output terminal N2 has a potential. Becomes a high-level potential VM (for example, 5 V) for image signal input. As a result, in the pixel 40, the first transmission gate TG1 is turned on, and the first control line 91 and the pixel electrode 35 are electrically connected.

If the positive image signal based on the image data D1 is input to the pixel 40 of the display unit 5 in this way, the normal image signal transfer step ST11 is terminated and the process proceeds to the image display step ST12.
In the image display step ST12 of the present embodiment, as shown in FIG. 7, a first image display step ST12A and a second image display step ST12B are executed in order.

  First, when proceeding to the first image display step ST12A, the potential Vdd of the high potential power supply line 50 is raised from the high level potential for image signal input to the high level potential VH for image display (for example, 15V). The potential Vss of the low potential power line 49 is a low level potential (ground potential).

  In the first image display step ST12A, a rectangular wave (for example, a pulse width of 20 ms) that repeats the high level potential VH and the ground potential GND at a predetermined cycle is input to the common electrode 37. Further, the high level potential VH is input to the first control line 91, and the ground potential GND is input to the second control line 92.

  In the pixel 40 holding the low-level image signal (pixel data “0”) in the latch circuit 70 by the potential input described above, the first control line 91 is connected to the pixel electrode 35 via the first transmission gate TG1. Potential S1 (high level potential VH). Accordingly, in this pixel 40, a voltage is applied to the electrophoretic element 32 during a period in which the common electrode 37 is at the ground potential GND, and the pixel 40 performs a black display operation (FIG. 4B). In the pixel 40, the electrophoretic element 32 is not driven during a period in which the common electrode 37 is at the high level potential VH.

  On the other hand, in the pixel 40 that holds the high-level image signal (pixel data “1”) in the latch circuit 70, the potential S2 (the second control line 92) is applied to the pixel electrode 35 via the second transmission gate TG2. The ground potential GND) is input. Thereby, in this pixel 40, a voltage is applied to the electrophoretic element 32 during a period in which the common electrode 37 is at the high level potential VH, and the pixel 40 performs a white display operation (FIG. 4A). In the pixel 40, the electrophoretic element 32 is not driven during a period in which the common electrode 37 is at the ground potential GND.

  Next, in the second image display step ST12B, as shown in FIG. 7, a rectangular pulse having a pulse width different from that of the first image display step ST12A is input to the common electrode 37. The pulse width of the pulse input to the common electrode 37 in the second image display step ST12B is, for example, 200 ms, and the period of the rectangular wave (for example, pulse width 20 ms) input to the common electrode 37 in the first image display step ST12A. The pulse has a width about 10 times as large as the above.

  On the other hand, in the second image display step ST12B, the number of pulses input to the common electrode 37 is set to be smaller than the number of pulses input in the first image display step ST12A. Specifically, the number of pulses in the first image display step ST12A is 30 pulses (the period of the high level potential VH and the period of the ground potential are counted as one pulse), whereas the second image display. In step ST12B, there are four pulses.

  The operation of the pixel 40 in the second image display step ST12B is the same as that of the first image display step ST12A. The pixel 40 holding the low-level image signal in the latch circuit 70 performs the black display operation and has the high level. The pixel 40 holding the image signal performs a white display operation.

  By sequentially executing the first image display step ST12A and the second image display step ST12B described above, the image (normal image) shown in FIG. 8B can be displayed on the display unit 5.

  In the driving method of this embodiment, as described above, the image display step ST12 is input to the first image display step ST12A in which a narrow pulse is input to the common electrode 37, and the wide pulse is input to the common electrode 37. By sequentially executing the second image display step ST12B, high-quality image display is possible. That is, in the first image display step ST12A, the period in which the black display progresses and the period in which the white display progresses are switched in a short time (20 ms), so the image shown in FIG. Can appear smoothly. On the other hand, in the second image display step ST12B, since the period during which black display or white display proceeds is long, the electrophoretic particles (black particles 26, white particles 27) in the electrophoretic element 32 are sufficiently moved to the vicinity of the electrodes. Accordingly, the contrast can be increased and a clear display can be obtained.

  The ratio between the pulse width of the pulse input to the common electrode 37 in the first image display step ST12A and the pulse width of the pulse input to the common electrode 37 in the second image display step ST12B is exemplified above. However, the setting can be changed within a range of several times to several tens of times. Further, the number of pulses input to the common electrode 37 can be arbitrarily set in each of the first image display step ST12A and the second image display step ST12B.

  If an image is displayed on the display part 5, it will transfer to temperature determination step ST15. In the temperature determination step ST15, the control circuit 161 acquires temperature information from the output of the temperature sensor 6, holds it as the current environmental temperature (temperature of the display unit 5), and uses this temperature information for the environmental temperature of the memory 162. Are stored in a storage area (not shown).

Next, the control circuit 161 reads the set value of the environmental temperature stored in the memory 162. The set value of the environmental temperature held in the memory 162 is a temperature classified into a high temperature environment of about 50 ° C. to 65 ° C., for example.
Thereafter, the control circuit 161 compares the measured environmental temperature with the set value. And when the measured environmental temperature is more than a preset value, it transfers to 2nd step S102. On the other hand, if the measured environmental temperature is less than the set value, the process is terminated (END).

Hereinafter, the case where it transfers to 2nd step S102 is demonstrated.
In the second step S102 of the present embodiment, as shown in FIG. 6, an inverted image signal transfer step ST21 and a wait step ST22 are sequentially executed.

  First, in the inverted image signal transfer step ST21, as shown in FIG. 7, the common electrode 37, the first control line 91, and the second control line 92 are all in a high impedance state. Thereby, the pixel electrode 35 and the common electrode 37 of all the pixels 40 are in a high impedance state, and a voltage is not applied to the electrophoretic element 32. On the other hand, since the potential Vdd of the high potential power supply line 50 is set to a high level potential VM (for example, 5 V) for inputting an image signal, the latch circuit 70 is held in a power-on state.

  Then, after the potential of each electrode is set as described above, an inverted image signal based on the image data D2 (inverted image of the image data D1) shown on the right side of FIG. 8A is transferred to the pixel 40 of the display unit 5. The The image signal transfer operation is the same as the normal image signal transfer step ST11 in the first step S101. Through this inverted image signal transfer step ST21, the image signal held in the latch circuit 70 of the pixel 40 is inverted.

  When the input of the inverted image signal is completed, the process proceeds to wait step ST22. In the present embodiment, the weight step ST22 includes a first weight step ST22A and a second weight step ST22B as shown in FIG. The first weight step ST22A is set to the same length of time as the first image display step ST12A in the first step S101, and the second weight step ST22B is the second image display in the first step S101. The time is set to the same length as step ST12B.

  In the first wait step ST22A and the second wait step ST22B, the common electrode 37, the first control line 91, and the second control line 92 are all in a high impedance state, and the potential Vdd of the high potential power supply line 50 is set. Is set to the high-level potential VH for image display. Since the common electrode 37, the first control line 91, and the second control line 92 are all in a high impedance state, the electrophoretic element 32 is not driven over the entire period of the wait step ST22, and the display is performed. The state of the part 5 does not change.

  By executing the first wait step ST22A and the second wait step ST22B set to the above-described potential state and period length, BT (Bias-Temperature) stress of the MOS transistor constituting the latch circuit 70 is performed. Progress of deterioration can be suppressed. Hereinafter, further details will be described with reference to FIG.

  FIG. 9 is an explanatory diagram of BT stress degradation in the latch circuit. FIG. 9A is a diagram showing a latch circuit in a state where a high level image signal is held, and FIG. 9B is a diagram showing a latch circuit in a state where a low level image signal is held.

  As shown in FIG. 9A, in a state where a high level image signal is held in the latch circuit 70, in the P-MOS transistor 73, the source is high level (high level potential VH) and the gate is low level ( Ground potential GND), and a DC bias is applied between the source and the gate (indicated as “−BT”). On the other hand, in the P-MOS transistor 71, the drain is at a low level and the gate is at a high level, and a DC bias is applied between the gate and the drain (shown as “+ BT”). Similarly, DC biases of “+ BT” and “−BT” are applied to the N-MOS transistors 72 and 74, respectively.

  On the other hand, in a state where the low level image signal is held in the latch circuit 70 shown in FIG. 9B, “+ BT” is applied to the P-MOS transistor 73 and the N-MOS transistor 74, and the P-MOS transistor 71. Then, a DC bias of “+ BT” is applied to the N-MOS transistor 72, and the state is completely opposite to that in FIG.

Here, it is known that the BT stress deterioration of the TFT is reversible, and the BT stress deterioration caused by applying the DC bias in one direction is recovered by applying the DC bias in the reverse direction.
Therefore, in the driving method of the present embodiment, a DC bias opposite to the DC bias applied to the TFT of the latch circuit 70 in the first step S101 is applied to the TFT of the latch circuit 70 in the second step S102. The BT bias deterioration caused in the first step S101 is recovered in the second step S102.

In particular, in the case of the present embodiment, since the potential Vdd of the high potential power supply line 50 is matched in the image display step ST12 and the wait step ST22, the DC bias applied to the TFT of any latch circuit 70 in the image display step ST12. And the magnitude of the DC bias in the weight step ST22 are substantially equal.
Further, the length of the period of the first image display step ST12A is matched with the length of the period of the first weight step ST22A, and the length of the period of the second image display step ST12B and the period of the second weight step ST22B. Since the lengths are the same, the DC bias application period is the same in the image display step ST12 and the wait step ST22.
As described above, according to the driving method of the present embodiment, the BT stress degradation that has occurred in the first step S101 can be almost certainly recovered in the second step S102, and excellent reliability can be obtained over a long period of time. It is possible.

In the present embodiment, the energization of the latch circuit 70 is stopped by electrically disconnecting the potential Vdd of the high potential power line 50 after the end time t of the second wait step ST22B shown in FIG. When the power is shut off at time t, the potential Vdd is changed from the high level potential VH to the ground potential GND, and then is changed to the high impedance state.
By adopting such a power supply shut-off method, the high potential power supply line 50 is held in a state in which the electric charge is removed, so that a DC bias is not applied to the TFT of the latch circuit 70 due to the residual electric charge. And the occurrence of BT stress degradation can be effectively suppressed.

  In the present embodiment, the temperature determination step ST15 is provided between the first step S101 and the second step S102, and the second step S102 is executed only in a high temperature environment. The BT stress degradation of TFT tends to be manifested in a high temperature environment, but generally hardly becomes a problem at room temperature. Therefore, power consumption can be suppressed by making the execution of the second step S102 unnecessary in a relatively low temperature environment.

Further, while the second step S102 is being executed, there is a restriction that display update to different image data is not possible. However, if the second step S102 is not executed in a relatively low temperature environment as described above. The influence on operability can be reduced.
However, even during the execution of the second step S102, the display image can be refreshed, inverted, or entirely erased by controlling the potentials of the first control line 91 and the second control line 92. In the image erasing operation performed prior to the display image update, the second step S102 may be executed.

  It should be noted that at least if the DC bias in the direction opposite to that in the first step S101 is applied to the TFT of the latch circuit 70, except for an excessively low applied voltage or an excessively short application time, It is possible to obtain the effect of restoring the BT stress deterioration. Therefore, the DC bias voltage and period conditions applied to the TFT in the wait step ST22 do not necessarily correspond to the DC bias conditions applied to the TFT in the image display step ST12.

  For example, in the above embodiment, the potential Vdd of the high potential power supply line 50 is set to the high level potential VH in the wait step ST22. However, the high level potential VM for inputting an image signal lower than the high level potential VH may be used. The potential may be higher than VH (for example, 30 V). Further, the length of the period of the wait step ST22 may be made longer or shorter than the length of the period of the image display step ST12.

  On the other hand, in order to recover the BT stress deterioration to the maximum, the product V1 · T1 of the DC bias application voltage V1 and the application time T1 in the first step S101, and the DC bias application voltage V2 in the second step S102. And the product V2 · T2 of the application time T2 are preferably matched. In this case, the applied voltage V2 and the applied time T2 may be appropriately changed as long as the range satisfies the expression V1 · T1 = V2 · T2.

  In the present embodiment, the second step S102 is executed immediately after the first step S101. However, the execution timings of the first step S101 and the second step S102 are not limited to this. For example, the second step S102 may be executed immediately before the first step S101.

  Moreover, it is good also as a structure which does not perform 1st step S101 and 2nd step S102 continuously. That is, after executing the first step S101 a plurality of times, the second step S102 corresponding to each first step S101 can also be executed collectively. In the present embodiment, as shown in FIG. 5, since a copy of the frame memory can be written from the image signal generation circuit 166 to the memory 162, for example, the frame when the first step S101 is executed over 100 frames. The history of the memory 165 can be stored in the memory 162.

Then, for example, the BT stress generated by the first step S101 of the 100 frame at the timing when the electrophoretic display device 100 is in an idle state such as when the image is not rewritten for a predetermined time or when the power-off sequence is executed. A plurality of second steps S102 for recovering the deterioration can be continuously executed. Specifically, the image data of the history of the frame memory held in the memory 162 is read out to produce inverted image data, which is transferred to the pixel 40 of the display unit 5 and the operation of maintaining the wait state for a predetermined period is performed. The image data is sequentially executed.
When executing the plurality of second steps S102 corresponding to the plurality of first steps S101 as described above, some of the plurality of second steps S102 may be intermittently executed. Good.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the drawings referred to in the following description, the same reference numerals are given to the same components as those in the electrophoretic display device according to the first embodiment, and detailed descriptions thereof are also omitted.

FIG. 10 is a flowchart illustrating a driving method of the electrophoretic display device according to the second embodiment. FIG. 11 is a timing chart corresponding to FIG.
As shown in FIG. 10, the driving method of the present embodiment includes a first step S101 and a second step S102. The first step S201 is a step of sequentially executing the normal image signal transfer step ST11 and the normal image driving step ST13. The second step S202 is a step of sequentially executing the reverse image signal transfer step ST21 and the reverse image driving step ST23.

  First, in the normal image signal transfer step ST11 of the first step S201, as in the first embodiment, for example, an image signal corresponding to the image data D1 shown in FIG. 8A is transferred to the pixel 40 of the display unit 5. Then, an image signal is held in the latch circuit 70 of each pixel 40. Thereafter, the process proceeds to the normal image driving step ST13.

  Next, when proceeding to the normal image driving step ST13, as shown in FIG. 11, the potential Vdd of the high potential power supply line 50 is used for image signal input as in the first image display step ST12A in the first embodiment. The high level potential VM (for example, 5V) is raised to a high level potential VH (for example, 15V) for image display. A rectangular wave (for example, a pulse width of 20 ms) that repeats the high level potential VH and the ground potential GND at a predetermined cycle is input to the common electrode 37. Further, the high level potential VH is input to the first control line 91, and the ground potential GND is input to the second control line 92.

With the above potential input, the pixel 40 holding the low level image signal (pixel data “0”) in the latch circuit 70 performs a black display operation, and the high level image signal (pixel data “1”) is input to the latch circuit 70. ) Holds a white display operation. Thereby, the image shown in FIG. 8B is displayed on the display unit 5.
In the present embodiment, the image display step corresponding to the second image display step ST12B according to the first embodiment is not executed.

If the above-described potential input is executed for a predetermined period (a period in which 18 pulses are input to the common electrode 37 in FIG. 11), the process proceeds to the inverted image signal transfer step ST21 in the second step S202.
In the inverted image signal transfer step ST21, as in the first embodiment, the image signal corresponding to the image data D2 shown on the right side of FIG. 8A is transferred to the pixel 40 of the display unit 5, and the latch circuit of each pixel 40 is transferred. The image signal is held in 70. Thereafter, the process proceeds to a reverse image driving step ST23.

When the process proceeds to the reverse image driving step ST23, unlike the normal image driving step ST13, the ground potential GND is input to the first control line 91, and the high level potential VH is input to the second control line 92.
The potential Vdd of the high potential power supply line 50 is raised from the high level potential VM (for example, 5V) for image signal input to the high level potential VH (for example, 15V) for image display, Similar to the positive image drive step ST13, a rectangular wave (for example, a pulse width of 20 ms) that repeats the ground potential GND at a predetermined cycle is input.

  As described above, in the second step S202, the inverted image signal is input to the pixel 40, and the potentials input to the first control line 91 and the second control line 92 are switched. Therefore, in the second step S202, the pixel 40 holding the low-level image signal (pixel data “0”; the black region in the image data D2) in the latch circuit 70 performs a white display operation, and the latch circuit 70 The pixel 40 holding the high level image signal (pixel data “1”; white area in the image data D2) performs a black display operation. Thereby, also in 2nd step S202, the image by which the black character was displayed on the white background shown in FIG.8 (b) is displayed on the display part 5. FIG.

  In the driving method according to the second embodiment described above, in the second step S202, an inverted image signal is input to the pixel 40 of the display unit 5, and the potentials of the first control line 91 and the second control line 92 are set. By performing replacement and inputting, the same image display operation as in the first step S201 is performed on the display unit 5. Accordingly, since the DC bias acting on the TFT of the latch circuit 70 can be reversed during the operation of displaying an image based on the image data, the BT stress degradation that has occurred in the TFT in the first step S201 is reduced to the second. It is possible to recover by executing step S202.

  In the present embodiment, the length of the period of the reverse image driving step ST23 is preferably equal to the length of the period of the normal image driving step ST13. Thereby, recovery of BT stress degradation can be performed efficiently. However, this is not the case when the potential Vdd of the high potential power supply line 50 is set to a potential other than the high level potential VH in the inverted image driving step ST23, and it depends on the voltage of the DC bias applied to the TFT of the latch circuit 70. Thus, the length of the period of the reverse image driving step ST23 may be adjusted.

  Also in the present embodiment, a temperature determination step ST15 may be provided between the first step S201 and the second step S202, and the driving method may switch the execution of the second step S202 based on the environmental temperature. Of course.

(Electronics)
FIG. 12 is a perspective view showing a specific example of an electronic apparatus to which the electrophoretic display device 100 of the present invention is applied.
FIG. 12A is a perspective view illustrating an electronic book which is an example of an electronic apparatus. The electronic book 1000 includes a book-shaped frame 1001, a cover 1002 that can be rotated (openable and closable) with respect to the frame 1001, an operation unit 1003, and the electrophoretic display device of the above embodiment. The display unit 1004 is provided.
FIG. 12B is a perspective view illustrating a wrist watch that is an example of an electronic apparatus. The wristwatch 1100 includes a display unit 1101 configured by the electrophoretic display device of the above embodiment.
FIG. 12C is a perspective view illustrating an electronic paper which is an example of the electronic apparatus. The electronic paper 1200 includes a main body 1201 formed of a rewritable sheet having the same texture and flexibility as paper, and a display unit 1202 configured by the electrophoretic display device of the above embodiment.

The electronic book 1000, the wristwatch 1100, and the electronic paper 1200 described above are electronic devices including display means with excellent reliability by employing the electrophoretic display device according to the previous embodiment.
In addition, the said electronic device illustrates the electronic device which concerns on this invention, Comprising: The technical scope of this invention is not limited. For example, the electrophoretic display device according to the present invention can be suitably used for a display portion of an electronic device such as a mobile phone or a portable audio device. The range of electronic devices to which the electrophoretic display device of the present invention can be applied is not limited to this, and includes a wide range of devices that use changes in visual color tone accompanying the movement of charged particles.

  100 electrophoretic display device, 5 display unit, 6 temperature sensor (temperature measurement unit), 32 electrophoretic element, 35 pixel electrode, 37 common electrode, 40 pixel, 41 selection transistor (pixel switching element), 50 high potential power line, 61 scanning line drive circuit, 62 data line drive circuit, 63 controller (control unit), 64 common power supply modulation circuit, 70 latch circuit, 80 switch circuit, 91 first control line, 92 second control line, S101, S201 First step, S102, S202 Second step, ST11 Positive image signal transfer step, ST12 Image display step, ST12A First image display step, ST12B Second image display step, ST13 Positive image drive step, ST15 Temperature determination Step, ST21 Inverted image signal transfer step, S T22 wait step, ST22A first wait step, ST22B second wait step, ST23 reverse image drive step

Claims (13)

An electrophoretic element including electrophoretic particles is sandwiched between a pair of substrates, and includes a display unit having a plurality of pixels and a first control line and a second control line connected to the pixels, For each pixel, a pixel electrode, a pixel switching element, a latch circuit connected between the pixel electrode and the pixel switching element, and the pixel electrode and the first and first elements based on an output of the latch circuit And a switch circuit for switching connection with the control line of the electrophoretic display device,
In a state where a plurality of latch circuits of the display unit hold a positive image signal corresponding to one image, the potential of the first control line or the second control line is input to the pixel electrode, A first step of driving the electrophoretic element of a pixel;
A second step in which a plurality of latch circuits hold a reverse image signal corresponding to a reverse image of the one image for a predetermined period;
A method for driving an electrophoretic display device, comprising:   The period during which the latch circuit holds the normal image signal in the first step and the period during which the latch circuit holds the inverted image signal in the second step have the same length. The method for driving an electrophoretic display device according to claim 1.   The driving method of the electrophoretic display device according to claim 1, wherein the electrophoretic element is not driven in the second step.   In the second step, the potential input to the first control line is the potential input to the second control line in the first step, while being input to the second control line. 3. The method for driving an electrophoretic display device according to claim 1, wherein the potential is a potential input to the first control line in the first step. The electrophoretic display device includes a temperature measurement unit that measures the temperature of the display unit,
5. The driving method of the electrophoretic display device according to claim 1, wherein execution or skip of the second step is selected based on the temperature measured by the temperature measurement unit. 6. .   The power supply terminal is electrically disconnected after the reference potential is input to the power supply terminal of the latch circuit when shutting off the power supply of the latch circuit. A driving method of the electrophoretic display device described. An electrophoretic element including electrophoretic particles is sandwiched between a pair of substrates, and includes a display unit having a plurality of pixels and a first control line and a second control line connected to the pixels, For each pixel, a pixel electrode, a pixel switching element, a latch circuit connected between the pixel electrode and the pixel switching element, and the pixel electrode and the first and first elements based on an output of the latch circuit An electrophoretic display device comprising a control unit that controls the display unit, and a switch circuit that switches connection with the two control lines.
The controller is
A potential of the first control line or the second control line is input to the pixel electrode in a state where a plurality of the latch circuits of the display unit hold a positive image signal corresponding to one image, and the pixel A first operation of driving the electrophoretic element of
A second operation in which a plurality of latch circuits hold a reverse image signal corresponding to a reverse image of the one image for a predetermined period;
An electrophoretic display device comprising:   The period during which the latch circuit holds the normal image signal in the first operation and the period during which the latch circuit holds the inverted image signal in the second operation have the same length. The electrophoretic display device according to claim 7.   The electrophoretic display device according to claim 7, wherein the controller does not drive the electrophoretic element in the second operation. The controller is
In the first operation, a first potential is input to the first control line, and a second potential is input to the second control line,
9. The electrophoretic display according to claim 7, wherein the second potential is input to the first control line and the first potential is input to the second control line in the second operation. apparatus. A temperature measuring unit for measuring the temperature of the display unit;
11. The electrophoresis according to claim 7, wherein the control unit selects execution or skipping of the second operation based on the temperature measured by the temperature measurement unit. Display device.   12. The control unit according to claim 7, wherein when the power supply of the latch circuit is cut off, the control unit electrically disconnects the power supply terminal after inputting a reference potential to the power supply terminal of the latch circuit. The electrophoretic display device according to any one of the above.   An electronic apparatus comprising the electrophoretic display device according to claim 7.

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