JP2008263222A - Multilayer printed wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer printed wiring board capable of reducing the number of buildup layers by forming a high-density through-hole on a core substrate. <P>SOLUTION: The front side of a buildup layer 90A and the rear side of the buildup layer 90B are connected via a through-hole 16 formed on a core substrate 30. The through-hole 16 is filled up with filler 22, and a conductor layer 26a is formed so that the exposed surface of the filler 22 from the through-hole 16 may be covered. Then, a via hole 60 on the side of an upper layer is connected to the conductor layer 26a. Finally, the number of the buildup layers can be reduced by forming a high-density through-hole on the core substrate, and it can be achieved by making the land pattern of the through-hole 16 circular, which can be made possible by forming the conductor layer 26a in a circular fashion. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a multilayer printed wiring board, and more particularly to a multilayer printed wiring board in which build-up wiring layers in which interlayer resin insulating layers and conductor layers are alternately laminated are formed on both surfaces of a core substrate.

In recent years, a package substrate on which an IC chip is mounted is required to have a high density and high reliability by a fine pattern in response to downsizing or speeding up of electronic equipment accompanying the advancement of the electronics industry. As such a package substrate, 1997. In the January issue of “Surface Mount Technology” and PCT / JP96 / 02608, a multilayer core substrate having a build-up multilayer wiring layer formed on both sides is disclosed.

In the package substrate according to the prior art described above, the conductor layer in the multilayer core substrate and the build-up wiring layer are connected by providing an inner layer pad wired from a through hole on the surface of the multilayer core substrate, and a via hole in the inner layer pad. Was connected. That is, an inner layer pad 226b for connecting a via hole to the upper layer is added to the land 226a of the through hole 216 as shown in FIG. 8A, or the land of the through hole 216 is shown in FIG. 8B. An inner layer pad 226b for via hole connection was connected to 226a via a wiring 226c.
PCT / JP96 / 02608 JP-A-7-283538 JP-A-9-8459

However, in the conventional land shape shown in FIG. 8 (A) or FIG. 8 (B), the interval between the through holes exceeds 750 μm in order to maintain the insulation between the inner layer pads. The number of formations was limited.

On the other hand, in the package substrate, an IC chip is placed on a bump disposed in the center on the front surface side, and the bump formed on the entire back surface is connected to the motherboard. That is, in the build-up wiring layer of the package substrate, the conductor circuit formed in each interlayer resin insulating layer is routed in the outer peripheral direction of the substrate and spreads from the bump disposed in the center on the surface side in the outer peripheral direction. Connected to the back bump.

In the package substrate, more bumps on the back surface are formed than the number of bumps on the front surface side. This is because wiring from the plurality of bumps on the back surface is connected to the bumps on the front surface side while being integrated. Here, the build-up wiring layer formed on the front side of the core substrate and the build-up wiring layer formed on the back side can be integrated at the same pace, so that the upper build-up wiring layer and the lower build-up wiring layer can be integrated. It is desirable to make the number of layers equal to each other, that is, to minimize the number of layers. However, as described above, the number of through holes that can be formed in the multilayer core substrate is limited. For this reason, in the conventional package substrate, wiring is integrated to some extent in the backside buildup wiring layer, and then connected to the front side buildup wiring layer through the through-hole of the multilayer core substrate. That is, in the front-side build-up wiring layer, since the wiring density is lowered, the number of layers that is essentially the same as that of the back-side build-up wiring layer is not required. However, if the number of build-up wiring layers on the front and back sides is different, warpage occurs due to asymmetry, so the number of layers on the front and back sides is the same. That is, since the number of through-holes formed in the multilayer core substrate is limited, the number of back-up build-up wiring layers must be increased, and in addition, the number of layers is equal to the back side with the increased number of layers. The front side build-up wiring layer had to be formed.

That is, in the multilayer printed wiring board (package substrate) of the prior art, since the number of buildup layers is increased, the connection reliability of the upper and lower layers is reduced, and the cost of the package substrate is increased. There has been a problem that the thickness and weight of the package substrate become larger than necessary.

The present invention has been made to solve the above-described problems, and the object of the present invention is to reduce the number of build-up layers by increasing the density of through holes formed in the core substrate. It is to provide a multilayer printed wiring board.

As a result of intensive research aimed at the realization of the above object, the inventors did not connect the via hole and the through hole via the inner layer pad, but formed the via hole directly on the conductor layer formed so as to cover the through hole. Knowing to connect. Thereby, the shape of the through hole can be made circular, and the number of through holes formed can be increased.

The multilayer printed wiring board of the present invention has a build-up wiring layer in which an interlayer resin insulating layer and a conductor layer are alternately laminated on both surfaces of a multilayer core substrate having a conductor layer, and each conductor layer is connected by a via hole. A plurality of through holes having a pitch interval of 700 μm or less are formed in the multilayer core substrate, and the through holes are filled with a filler and cover the exposed surface of the filler from the through holes. A technical feature is that a via hole is connected to the conductor layer. In the multilayer printed wiring board according to the present invention, the filler filled in the through hole is preferably made of metal particles and a thermosetting or thermoplastic resin.

In the multilayer printed wiring board of the present invention, a filler is filled in a through hole provided in the core substrate, and a conductor layer covering the exposed surface of the filler from the through hole is formed, and a via hole is formed in the conductor layer. It is characterized in that it is structured to connect the build-up wiring layer and the through hole by connecting them. According to such a configuration of the present invention, the dead space is eliminated by causing the region immediately above the through hole to function as the inner layer pad, and it is not necessary to wire the inner layer pad for connecting the through hole to the via hole. The land shape of the through hole can be a perfect circle. As a result, the density of through-holes provided in the multilayer core substrate is improved, and the number of through-holes can be increased. The signal lines of the back-side build-up wiring layer are connected to the surface build-up layer through these through-holes. You can connect.

Therefore, the conductor circuit can be routed to the outer periphery of the substrate in both the front and back build-up layers. In addition, as described above, in the multilayer printed wiring board, wiring from a plurality of bumps on the back surface is connected to the bumps on the front surface side while being integrated, but by forming through holes with a necessary density, on the front side and the back side Since the wiring can be integrated at the same pace in the formed buildup wiring layer, the number of buildup wiring layers formed on the front side and the back side can be reduced. The pitch of the through holes needs to be 700 μm or less. By setting the thickness to 700 μm or less, the number of through holes can be increased to a predetermined number (pieces / substrate) or more, and the signal line can be reliably connected from the front surface to the back-up build-up layer.

In such a multilayer printed wiring board of the present invention, the core substrate may be multilayered. This multilayer core substrate is formed by alternately laminating conductor layers and prepregs. For example, a prepreg made by impregnating a glass fiber or aramid fiber cloth or nonwoven fabric with a resin to form a B stage is alternately laminated with a copper foil or a circuit board, and then heated and integrated to form.

The filler filled in the through hole in the multilayer printed wiring board of the present invention is preferably composed of metal particles, a thermosetting resin and a curing agent, or composed of metal particles and a thermoplastic resin, if necessary. A solvent may be added. When such a filler contains metal particles, the metal particles are exposed by polishing the surface, and integrated with the plating film of the conductor layer formed thereon via the exposed metal particles. For this reason, peeling is unlikely to occur at the interface with the conductor layer even under severe hot and humid conditions such as PCT (pressure cooker test). In addition, since the filler is filled in the through hole in which the metal film is formed on the wall surface, migration of metal ions does not occur.

As the metal particles, copper, gold, silver, aluminum, nickel, titanium, chromium, tin / lead, palladium, platinum or the like can be used. In addition, as for the particle diameter of this metal particle, 0.1-50 micrometers is good. The reason for this is that if the thickness is less than 0.1 μm, the copper surface is oxidized and the wettability with respect to the resin is deteriorated, whereas if it exceeds 50 μm, the printability is deteriorated. The blending amount of the metal particles is preferably 30 to 90 wt% with respect to the total amount. The reason for this is that if the amount is less than 30 wt%, the adhesion of the lid plating is deteriorated, while if it exceeds 90 wt%, the printability is deteriorated.

Examples of resins used include epoxy resins such as bisphenol A type and bisphenol F type, phenol resins, polyimide resins, fluorine resins such as polytetrafluoroethylene (PTFE), bismaleimide triazine (BT) resins, FEP, PFA, and PPS. , PEN, PES, nylon, aramid, PEEK, PEKK, PET and the like can be used. As the curing agent, an imidazole-based, phenol-based, or amine-based curing agent can be used.

Solvents include NMP (normal methyl pyrrolidone), DMDG (diethylene glycol dimethyl ether), glycerin, water, 11 or 2- or 3-cyclohexanol, cyclohexanone, methyl cellosolve, methyl cellosolve acetate, methanol, ethanol, butanol, Propanol or the like can be used.

This filler is preferably non-conductive. This is because the non-conductive material has a smaller curing shrinkage and is less likely to be peeled off from the conductor layer or via hole.

In the multilayer printed wiring board of the present invention, it is desirable that a roughened layer is formed on the inner wall conductor surface of the through hole filled with the filler. The reason why the roughened layer is formed on the conductor surface of the inner wall of the through hole is that the filler and the through hole are in close contact with each other through the roughened layer and no gap is generated. If there is a gap between the filler and the through hole, the conductor layer formed by electroplating just above it will not be flat, or the air in the gap will thermally expand and crack or peel off. On the other hand, water accumulates in the voids and causes migration and cracks. In this respect, the occurrence of such a defect can be prevented if the roughened layer is formed.

Further, in the present invention, it is advantageous that a roughening layer similar to the roughening layer formed on the conductor surface of the inner wall of the through hole is formed on the surface of the conductor layer covering the exposed surface of the filler from the through hole. It is. This is because the roughened layer can improve the adhesion with the interlayer resin insulation layer and via hole. In particular, when a roughened layer is formed on the side surface of the conductor layer, cracks generated toward the interlayer resin insulating layer starting from these interfaces due to insufficient adhesion between the side surface of the conductor layer and the interlayer resin insulating layer are suppressed. Can do.

The thickness of the roughened layer formed on the inner wall of such a through hole or the surface of the conductor layer is preferably 0.1 to 10 μm. This is because if it is too thick, it will cause a short circuit between layers, and if it is too thin, the adhesion to the adherend will be low. The roughened layer is formed by subjecting the conductor of the inner wall of the through hole or the surface of the conductor layer to oxidation (blackening) -reduction treatment, or treatment with a mixed aqueous solution of an organic acid and a cupric complex. Alternatively, those formed by plating a copper-nickel-phosphorus needle-like alloy are preferable.

Among these treatments, in the method based on oxidation (blackening) -reduction treatment, NaOH (10 g / l), NaClO ₂ (40 g / l), Na ₃ PO ₄ (6 g / l) is oxidized in the oxidation bath (blackening bath). NaOH (10 g / l) and NaBH ₄ (6 g / l) are used as a reducing bath.

Moreover, in the process using the mixed aqueous solution of an organic acid-cupric complex, it acts as follows under oxygen coexistence conditions such as spraying and bubbling to dissolve a metal foil such as copper which is a conductor circuit.
Cu + Cu (II) An → 2Cu (I) An / 2
2Cu (I) An / 2 / 20n / 4O2 + nAH (aeration)
→ 2Cu (II) An + n / 2H ₂ O
A is a complexing agent (acting as a chelating agent), and n is a coordination number.

The cupric complex used in this treatment is preferably an azole cupric complex. This cupric complex of azoles acts as an oxidizing agent for oxidizing metallic copper and the like. As azoles, diazole, triazole, and tetrazole are preferable. Of these, imidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-undecylimidazole and the like are preferable. The content of the cupric complex of the azole is preferably 1 to 15% by weight. It is because it is excellent in solubility and stability if it is within this range.

The organic acid is added to dissolve the copper oxide. Specific examples include formic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, maleic acid, benzoic acid, glycolic acid, lactic acid, apple Any one selected from acids and sulfamic acids is preferable. The content of the organic acid is preferably 0.1 to 30% by weight. This is to maintain the solubility of oxidized copper and to ensure dissolution stability. In addition, the generated cuprous complex is dissolved by the action of an acid and combined with oxygen to form a cupric complex, which again contributes to the oxidation of copper. In addition to organic acids, inorganic acids such as borofluoric acid, hydrochloric acid, and sulfuric acid may be added.

In order to assist the dissolution of copper and the oxidizing action of azoles, halogen ions such as fluorine ions, chlorine ions and bromine ions may be added to the etching solution comprising the organic acid-cupric complex. This halogen ion can be supplied by adding hydrochloric acid, sodium chloride or the like. The amount of halogen ions is preferably 0.01 to 20% by weight. This is because, if it is within this range, the formed roughened layer has excellent adhesion to the interlayer resin insulating layer.

The etching solution comprising this organic acid-cupric complex is prepared by dissolving a cupric complex of an azole and an organic acid (halogen ions as required) in water.

Moreover, in the plating treatment of the acicular alloy composed of copper-nickel-phosphorus, copper sulfate 1-40 g / l, nickel sulfate 0.1-6.0 g / l, citric acid 10-20 g / l, hypophosphite It is desirable to use a plating bath having a liquid composition comprising 10 to 100 g / l, boric acid 10 to 40 g / l, and surfactant 0.01 to 10 g / l.

In the present invention, as the interlayer resin insulation layer used in the build-up wiring layer, a thermosetting resin, a thermoplastic resin, or a composite of a thermosetting resin and a thermoplastic resin can be used. As the thermosetting resin, epoxy resin, polyimide resin, phenol resin, thermosetting polyphenylene ether (PPE), or the like can be used. Examples of the mature plastic resin include fluorine resins such as polytetrafluoroethylene (PTFE), polyethylene terephthalate (PET), polysulfone (PSF), polyphenylene sulfide (PPS), thermoplastic polyphenylene ether (PPE), and polyether sulfone (PES). ), Polyetherimide (PEI), polyphenylene sulfone (PPES), tetrafluoroethylene hexafluoropropylene copolymer (FEP), tetrafluoroethylene perfluoroalkoxy copolymer (PFA), polyethylene naphthalate (PEN) , Polyether ether ketone (PEEK), polyolefin resin and the like can be used. As the composite of the thermosetting resin and the thermoplastic resin, epoxy resin-PES, epoxy resin-PSF, epoxy resin-PPS, epoxy resin-PPES, or the like can be used.

In the present invention, a glass cloth impregnated resin composite can be used as the interlayer resin insulation layer. Examples of the glass cloth-impregnated resin composite include glass cloth-impregnated epoxy, glass cloth-impregnated bismaleimide triazine, glass cloth-impregnated PTFE, glass cloth-impregnated PPE, and glass cloth-impregnated polyimide.

In the present invention, an adhesive for electroless plating can be used as the interlayer resin insulating layer. As the electroless plating adhesive, heat-resistant resin particles that are soluble in a cured acid or oxidizing agent are dispersed in an uncured heat-resistant resin that becomes insoluble in an acid or oxidizing agent by the curing treatment. What is best. This is because the heat-resistant resin particles are dissolved and removed by treatment with an acid or an oxidizing agent, and a roughened surface made of crucible-like anchors can be formed on the surface.

In the above electroless plating adhesive, the heat-resistant resin particles particularly cured are (1) heat-resistant resin powder having an average particle size of 10 μm or less, and (2) heat-resistant resin having an average particle size of 2 μm or less. Aggregated particles obtained by agglomerating powder, (3) a mixture of heat-resistant resin powder having an average particle diameter of 2 to 10 μm and heat-resistant resin powder having an average particle diameter of 2 μm or less, and (4) having an average particle diameter of 2 to 10 μm Pseudo particles formed by adhering at least one of a heat-resistant resin powder or an inorganic powder having an average particle size of 2 μm or less to the surface of the heat-resistant resin powder, and (5) an average particle size of 0.1 to 0.8 μm Any one selected from a mixture of a heat-resistant resin powder and a heat-resistant resin powder having an average particle size of more than 0.8 μm and less than 2 μm, and (6) a heat-resistant resin powder having an average particle size of 0.1 to 1.0 μm It is desirable to use at least one kind. This is because more complex anchors can be formed. As the heat-resistant resin used in the electroless plating adhesive, the above-mentioned thermosetting resin, thermoplastic resin, and composite of thermosetting resin and thermoplastic resin can be used.

In the present invention, the conductor layers (including those covering the filler filled in the through holes) formed on the multilayer core substrate and the conductor circuits formed on the interlayer resin insulation layer can be connected by via holes. it can. In this case, the via hole may be filled with a plating film or a filler.

The multilayer printed wiring board of the present invention will be described below with reference to the drawings. FIG. 6 shows a cross section of the multilayer printed wiring board according to the embodiment of the present invention. Build-up wiring layers 90 </ b> A and 90 </ b> B are formed on the front and back surfaces of the multilayer core substrate 30. The built-up layers 90A and 90B are composed of an interlayer resin insulation layer 50 in which via holes 60 and conductor circuits 58 are formed, and an interlayer resin insulation layer 150 in which via holes 160 and conductor circuits 158 are formed.

Solder bumps 76U for connecting to bumps (not shown) of the IC chip are formed on the front side, and solder bumps 76U for connecting to bumps (not shown) of the mother board are formed on the back side. ing. In the multilayer printed wiring board, the conductor circuit from the solder bump 76U connected to the IC chip is wired toward the outer periphery of the board and connected to the solder bump 76D connected to the mother board. The front-side built-up layer 90 </ b> A and the back-side built-up layer 90 </ b> B are connected through the through-hole 16 formed in the core substrate 30.

That is, the through hole 16 is filled with the filler 22, and the conductor layer 26a is formed so as to cover the exposed surface of the filler 22 from the through hole 16. The upper via hole 60 is connected to the conductor layer 26 a, and the upper via hole 160 is connected to the conductor circuit 58 connected to the via hole, to the via hole 160 or the via hole 160. Solder bumps 76U and 76D are formed on the connected conductor circuit 158.

FIG. 7 shows a plan view of the core substrate 30 of the multilayer printed wiring board shown in FIG. 6, that is, a BB cross section in FIG. Here, the conductor layer 26a formed above the filler in the through hole 16 is formed in a circular shape, and the via hole 60 is directly connected to the conductor layer 26a as described above with reference to FIG. . By connecting in this way, the area immediately above the through hole 16 is made to function as the inner layer pad 226b described above with reference to FIGS. 8A and 8B, thereby eliminating the dead space. Since the inner layer pad 226b for connecting to the via hole 60 is not added, the land shape of the through hole 16 can be made circular. As a result, the number of through holes can be increased by improving the arrangement density of the through holes 16 provided in the multilayer core substrate 30.

Therefore, the conductor circuit can be routed to the outer periphery of the substrate by the build-up layers 90A and 90B on both the front surface and the back surface. In addition, as described above, in the multilayer printed wiring board, wiring from a plurality of bumps on the back surface is connected to the bumps on the front surface side while being integrated, but by forming through holes with a necessary density, on the front side and the back side With the build-up wiring layers 90A and 90B formed, wiring can be integrated at the same pace. As a result, the number of build-up wiring layers 90A and 90B formed on the front side and the back side can be reduced.

In the core substrate 30 shown in FIG. 6, the pitch of the through holes is 600 μm, but the pitch is desirably 700 μm or less. By setting the thickness to 700 μm or less, the number of through holes can be increased to (number / substrate) or more, and the signal line can be reliably connected from the front surface to the build-up layer on the back surface.

Next, a method for manufacturing the multilayer printed wiring board shown in FIG. 6 will be specifically described with an example. The method described below relates to a method for manufacturing a multilayer printed wiring board by a semi-additive method, but the method for manufacturing a multilayer printed wiring board in the present invention employs a full additive method, a multi-lamination method, and a pin lamination method. can do.

(1) Production of core substrate 30 The core substrate is formed by laminating prepregs. For example, a glass fiber or aramid fiber cloth or non-woven fabric is laminated with a prepreg that is impregnated with epoxy resin, polyimide resin, bismaleimide triazine resin, fluorine resin (polytetrafluoroethylene, etc.) and the like as a B stage, It is formed by heating and integrating. In addition, as a circuit board on a core board | substrate, what provided the copper pattern by providing an etching resist on both surfaces of a double-sided copper clad laminated board, for example, can be used.

(2) Formation of through hole 16
(1). A through-hole is formed in the multilayer core substrate with a drill or the like, and electroless plating is applied to the wall surface of the through-hole and the substrate surface to form the through-hole 16. Copper plating is preferable as the electroless plating. If the substrate surface is a resin with poor plating, such as fluororesin, surface modification such as pretreatment agent (trade name: Junkosha: Tetra Etch) made of organometallic sodium, plasma treatment, etc. Do.

(2). Next, electrolytic plating is performed for thickening. As this electrolytic plating, copper plating is preferable.
(3). Further, the roughening layer 20 is provided by roughening the inner wall of the through hole and the surface of the electrolytic plating film. This roughened layer may be blackened (oxidized) -reduced, formed by spraying a mixed aqueous solution of an organic acid and a cupric complex, or copper-nickel-phosphorous alloy plated. is there.

(3) Filler filling
(1). The through hole 16 formed in the above (2) is filled with the filler 22 having the structure described above. Specifically, the filler is filled in the through-hole by applying it by a printing method onto a substrate on which a mask having an opening in the through-hole portion is placed, and is dried and cured after filling.

A metal surface modifier such as a silane coupling agent may be added to the filler in order to increase the adhesion between the metal particles and the resin. Further, as other additives, an antifoaming agent such as an acrylic antifoaming agent or a silicon antifoaming agent, or an inorganic filler such as silica, alumina or talc may be added. Moreover, you may make a silane coupling agent adhere to the surface of a metal particle.

Such a filler is printed under the following conditions, for example. That is, printing is performed under the conditions of a Cu paste viscosity: 120 Pa · s, a squeegee speed: 13 mm / sec, and a squeegee push-in amount: 1 mm using a Tetron mesh mask printing mask plate and a 45 ° C. square squeegee.

(2). The filler protruding from the through holes and the roughened layer on the surface of the electrolytic plating film of the substrate are removed by polishing to flatten the substrate surface. Polishing is preferably a belt sander or buffing.

(4) Formation of conductor layer 26a (conductor layer covering conductor circuit and filler on multilayer core substrate) (1). After applying catalyst nuclei to the surface of the substrate flattened in (3) above, electroless plating is performed to form an electroless plating film having a thickness of about 0.1 to 5 μm, and further, if necessary, electrolytic plating is performed. And an electrolytic plating film having a thickness of 5 to 25 μm is provided. Next, a photosensitive dry film is laminated on the surface of the plating film by a hot press, and a photomask film (made of glass) on which a pattern is drawn is placed, exposed, and developed with a developer. An etching resist is provided. Then, the conductor layer 26a portion covering the conductor circuit portion and the filler 22 is formed by dissolving and removing the conductor in the etching resist non-forming portion with an etching solution. As the etching solution, an aqueous solution of sulfuric acid-hydrogen peroxide, an aqueous solution of persulfate such as ammonium persulfate, sodium persulfate, or potassium persulfate, or an aqueous solution of ferric chloride or cupric chloride is preferable.

(2). Then, after removing the etching resist to form independent conductor circuits 14 and conductor layers 26a, a roughened layer 27 is formed on the surfaces of the conductor circuits 14 and conductor layers 26a. When the roughened layer 27 is formed on the surface of the conductor layer 26a covering the conductor circuit 14 and the filler, the conductor has excellent adhesion to the interlayer resin insulating layer, and therefore, the side surface of the conductor layer covering the conductor circuit and the filler Cracks starting from the interface with the resin insulation layer do not occur. On the other hand, the conductor layer covering the filler improves the adhesion with the electrically connected via hole. The method for forming the roughened layer is as described above, and includes a method of forming by blackening (oxidation) -reduction treatment, acicular alloy plating, or etching.

Further, after roughening, in order to eliminate unevenness due to the conductor layer 26a on the substrate surface, the resin 28 is applied and filled between the conductor circuits, this is cured, and the surface is polished and smoothed until the conductor is exposed. May be. As the resin, it is desirable to use a bisphenol type epoxy resin such as a bisphenol A type epoxy resin or a bisphenol F type epoxy resin, a resin comprising an imidazole curing agent and inorganic particles. This is because the bisphenol type epoxy resin has a low viscosity and is easy to apply. Further, since the bisphenol F type epoxy resin does not require the use of a solvent, it is advantageous in that it can prevent cracks and peeling due to volatilization of the solvent during heat curing. Furthermore, it is desirable to provide a roughened layer on the surface of the conductor layer after polishing.

In addition, the following processes are employable as a formation method of a conductor layer. That is, a plating resist is formed on the substrate after completing the steps (1) to (3), and then electroplating is performed on the resist non-formation portion to form a conductor circuit and a conductor layer portion. On these conductors, After forming a solder plating film using an electrolytic solder plating solution consisting of tin borofluoride, lead borofluoride, borohydrofluoric acid, and peptone, the plating resist is removed, and the electroless plating film and copper foil under the plating resist are removed. Etching is performed to form an independent pattern, and the solder plating film is dissolved and removed with a borofluoric acid aqueous solution to form a conductor layer.

(5) Formation of interlayer resin insulation layer 50, conductor circuit 58, and via hole 60
(1). An interlayer resin insulation layer is formed on the wiring board thus produced. As the interlayer resin insulating layer 50, a thermosetting resin, a thermoplastic resin, or a composite of a thermosetting resin and a thermoplastic resin can be used. In the present invention, the above-described adhesive for electroless plating can be used as the interlayer resin insulating material. The interlayer resin insulation layer is formed by applying an uncured liquid of these resins or laminating a film-like resin by thermocompression bonding.

(2). Next, an opening is provided in the interlayer resin insulation layer 50 in order to ensure electrical connection with the underlying conductor circuit (through hole) covered with the interlayer resin insulation layer. The perforation of the opening is performed by exposure and development processing when the interlayer resin insulating layer is made of a photosensitive resin, and laser light is used when the interlayer resin insulating layer is made of a thermosetting resin or a thermoplastic resin. At this time, the laser beam used includes a carbon dioxide laser, an ultraviolet laser, an excimer laser, and the like. In the case where holes are formed by laser light, desmear treatment may be performed. This desmear treatment can be performed using an oxidant composed of an aqueous solution such as chromic acid or permanganate, or may be treated with oxygen plasma or the like.

(3). After the formation of the interlayer resin insulation layer 50 having openings, the surface is roughened as necessary. When the above-described electroless plating adhesive is used as an interlayer resin insulation layer, the surface is treated with an oxidizing agent to selectively remove only the heat-resistant resin particles and roughen. Even when a thermosetting resin or a thermoplastic resin is used, a surface roughening treatment with an oxidizing agent selected from aqueous solutions such as chromic acid and permanganate is effective. In the case of a resin such as a fluororesin (polytetrafluoroethylene or the like) that is not roughened by an oxidizing agent, the surface is roughened by plasma treatment or tetraetching.

(Five). Next, a catalyst nucleus for electroless plating is applied. In general, the catalyst nucleus is a palladium-tin colloid, and the substrate is immersed in this solution, dried, and heat-treated to fix the catalyst nucleus on the resin surface. Moreover, a metal nucleus can be driven into the resin surface by CVD, sputtering, or plasma to form a catalyst nucleus. In this case, metal nuclei are embedded in the resin surface, and plating is deposited around the metal nuclei to form a conductor circuit, so that it is difficult to roughen such as resin or fluororesin (polytetrafluoroethylene, etc.) Even with a resin having poor adhesion between the resin and the conductor circuit, adhesion can be secured. The metal nucleus is preferably at least one selected from palladium, silver, gold, platinum, titanium, copper and nickel. The amount of metal nuclei is preferably 20 μg / cm 2 or less. This is because if this amount is exceeded, the metal nuclei must be removed.

(6). Next, electroless plating is performed on the surface of the interlayer resin insulation layer, and an electroless plating film 52 is formed on the entire surface. The thickness of the electroless plating film 52 is 0.1 to 5 μm, more preferably 0.5 to 3 μm.
(6). Then, a plating resist is formed on the electroless plating film. The plating resist is formed by laminating a photosensitive dry film and exposing and developing as described above.
(7). Furthermore, electrolytic plating is performed. The electrolytic plating film 56 is preferably 5 to 30 μm. In the figure, the thickness is simply increased by electrolytic plating. However, it is desirable to fill the recesses for forming the via holes with an electrolytic plating film.
(8). Further, after the plating resist is peeled off, the electroless plating film under the plating resist is dissolved and removed by etching to form independent conductor circuits 58 and via holes 60. Conductor circuits (including via holes) are formed. As an etching solution, an aqueous solution of sulfuric acid-hydrogen peroxide, an aqueous solution of persulfate such as ammonium persulfate, sodium persulfate, or potassium persulfate, or an aqueous solution of ferric chloride or cupric chloride is preferable. Further, another layer of the interlayer resin insulation layer 150 and the via hole 160 is formed in the same manner.

[Example]
Hereinafter, the Example of the manufacturing process of a multilayer printed wiring board is described concretely with reference to FIGS.
(1) A copper-clad laminate 30A in which 18 μm of copper foil 12 is laminated on both surfaces of a core substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.5 mm is used as a starting material (see FIG. 1 (A)). Etching resist was provided on both surfaces, and etching treatment was performed with a sulfuric acid-hydrogen peroxide aqueous solution to obtain the core substrate 30 having the conductor circuit 14 (FIG. 1B).

(2) Next, through-holes 16 having a pitch interval of 600 μm and a diameter of 300 μm are drilled in the core substrate 30 with a drill (see FIG. 1C), and then a palladium-tin colloid is adhered, and electroless plating is performed with the following composition. Then, an electroless plating film 18 having a thickness of 2 μm was formed on the entire surface of the substrate 30 (see FIG. 1D).
[Electroless plating aqueous solution]
EDTA 150 g / l
Copper sulfate 20 g / l
HCHO 30 ml / l
NaOH 40 g / l
α, α'-bipyridyl 80 mg / l
PEG 0.1 g / l
[Electroless plating conditions]
30 minutes at a liquid temperature of 70 ° C

(3) The substrate 30 on which the conductor (including the through hole 16) made of the electroless copper plating film 18 in (2) is formed is washed with water and dried, and then NaOH (10 g / l), NaClO ₂ (40 g / l), Na ₃ PO ₄ (6 g / l) in an oxidation bath (blackening bath), NaOH (10 g / l), and NaBH ₄ (6 g / l) in a reduction bath are subjected to an oxidation-reduction treatment. A roughening layer 20 was provided on the entire surface of the conductor 18 including the metal (see FIG. 1E).

(4) Next, a filler 22 containing copper particles having an average particle diameter of 10 μm (non-conductive hole-filled copper paste made by Tatsuta Electric Wire, trade name: DD paste) is filled into the through-holes 16 by screen printing, and dried. Cured (FIG. 2 (F)). Then, the roughened layer 20 on the upper surface of the conductor 18 and the filler 22 protruding from the through-hole 16 are removed by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku), and scratches due to this belt sander polishing are further removed. The surface of the substrate 30 was flattened (see FIG. 2G). In this way, the substrate 30 is obtained in which the inner wall surface of the through hole 16 and the resin filler 22 are firmly adhered via the roughened layer 20.

(5) A palladium catalyst (manufactured by Atotech) is applied to the surface of the substrate 30 flattened in (4), and electroless copper plating is performed in accordance with the conditions of (2) above, thereby electrolessly having a thickness of 0.6 μm. A copper plating film 23 was formed (see FIG. 1H).

(6) Next, electrolytic copper plating is performed under the following conditions to form an electrolytic copper plating film 24 having a thickness of 15 μm, thickening a portion to be the conductor circuit 14, and a filler 22 filled in the through hole 16. A portion to be a conductor layer (a circular through-hole land) 26a was formed (FIG. 2 (I)).
(Electrolytic plating aqueous solution)
Sulfuric acid 180 g / l
Copper sulfate 80 g / l
Additive (product name: Kaparaside GL, manufactured by Atotech Japan)
1 ml / l
[Electrolytic plating conditions]
Current density 1A / dm ²
30 minutes
Temperature room temperature

(7) A commercially available photosensitive dry film is pasted on both surfaces of the substrate 30 on which the conductor circuit 14 and the conductor layer 26a are formed, and a mask is placed, exposed at 100 mJ / cm ² , and 0.8% carbonic acid. Development processing was performed with sodium to form an etching resist 25 having a thickness of 15 μm (see FIG. 2J).

(8) Then, the plating films 23 and 24 where the etching resist 25 is not formed are dissolved and removed by etching using a mixed solution of sulfuric acid and hydrogen peroxide, and the etching resist 8 is peeled off with 5% KOH. The conductor layer 26a covering the independent conductor circuit 14a and the filler 22 was formed by removing (see FIG. 3K).

(9) Next, a 2.5 μm thick roughened layer (uneven layer) 27 made of a Cu—Ni—P alloy is formed on the surface of the conductor layer 26 a covering the conductor circuit 14 a and the filler 22, and this roughening is further performed. An Sn layer having a thickness of 0.3 μm was formed on the surface of the chemical layer 27 (see FIG. 3L, but the Sn layer is not shown). The formation method is as follows. That is, the substrate 30 is subjected to acid degreasing and soft etching, and then treated with a catalyst solution composed of palladium chloride and an organic acid to give a Pd catalyst. After activating this catalyst, copper sulfate 8 g / l, sulfuric acid Plating in an electroless plating bath consisting of nickel 0.6 g / l, citric acid 15 g / l, sodium hypophosphite 29 g / l, boric acid 31 g / l, surfactant 0.1 g / l, pH = 9 Then, a roughened layer 27 of Cu—Ni—P alloy was provided on the surface of the conductor layer 26 a covering the conductor circuit 14 a and the filler 22.
Next, a Cu—Sn substitution reaction was performed under the conditions of tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l, temperature 50 ° C., pH = 1.2, and a thickness of 0.3 μm was formed on the surface of the roughened layer 10. The Sn layer was provided (the Sn layer is not shown).

Instead of the step (9), a so-called blackening-reducing layer is formed on the surface of the conductor layer 26a covering the conductor circuit 14a and the filler 22, and a resin such as bisphenol F type epoxy resin is filled between the conductor circuits. A roughened layer of Cu—Ni—P alloy may be formed by surface polishing and further plating of (9). (The package cross section shown in FIG. 6 is manufactured using this process)

(10) A resin filler for smoothing the substrate surface is adjusted. Here, 100 parts by weight of a bisphenol F type epoxy monomer (manufactured by Yuka Shell, molecular weight 310, YL983U) and 6 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei, 2E4MZ-CN) are mixed. 170 parts by weight of SiO2 spherical particles having an average particle diameter of 1.6 μm coated with a silane coupling agent (manufactured by Admatech, CRS1101-CE, where the maximum particle size is equal to or less than the thickness of the conductor circuit 14a described later) By mixing 0.5 parts by weight of an antifoam (manufactured by San Nopco, Perenol S4) and kneading with three rolls, the viscosity of the mixture is adjusted to 45,000 to 49,000 cps at 23 ± 1 ° C. To obtain a resin filler. This resin filler is solvent-free. If a resin filler containing a solvent is used, when the interlayer agent is applied and heated and dried in the subsequent step, the solvent evaporates from the resin filler layer, resulting in a gap between the resin filler layer and the interlayer material. This is because peeling occurs.

(11) By applying the resin filler 28 obtained in the above (10) to both surfaces of the substrate 30 using a roll coater, it is filled between the conductor layers 26a on the upper surface and dried at 70 ° C. for 20 minutes. Similarly, the lower surface is filled with the resin filler 30 between the conductor layers 26a or between the conductor circuits 14a and dried at 70 ° C. for 20 minutes (see FIG. 3M).

(12) Resin is applied to the surface of the conductor layer 26a or the surface of the conductor circuit 14a by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku Co., Ltd.) Polishing is performed so that the filler 28 does not remain, and then buffing is performed to remove scratches due to the belt sander polishing (see FIG. 3N). Next, the resin filler 28 is cured by heat treatment at 100 ° C. for 1 hour, 120 ° C. for 3 hours, 150 ° C. for 1 hour, and 180 ° C. for 7 hours.

Thus, by removing the roughening layer 27 on the surface of the conductor layer 26a and the conductor circuit 14a and smoothing both sides of the substrate, the resin filler 28, the conductor layer 26a, and the side surface of the conductor circuit 14a are roughened. The layer 27 is firmly attached.

(13) A roughened layer (concave / convex layer) 29 made of a Cu—Ni—P alloy having a thickness of 2.5 μm is formed on the upper surface of the conductor layer 26a and the conductor circuit 14a exposed by the processing of (12) above; An Sn layer having a thickness of 0.3 μm is provided on the surface of the roughened layer 29 (see FIG. 3 (O), but the Sn layer is not shown). The formation method is as follows. That is, the substrate 30 is subjected to acid degreasing and soft etching, and then treated with a catalyst solution composed of palladium chloride and an organic acid to give a Pd catalyst. After activating this catalyst, copper sulfate 8 g / l, sulfuric acid Plating in an electroless plating bath consisting of nickel 0.6 g / l, citric acid 15 g / l, sodium hypophosphite 29 g / l, boric acid 31 g / l, surfactant 0.1 g / l, pH = 9 Then, a roughened layer 29 of Cu—Ni—P alloy is formed on the land surfaces of the copper conductor circuit 4 and the through hole 9. Next, a Cu—Sn substitution reaction was carried out under the conditions of tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l, temperature 50 ° C., pH = 1.2, and the thickness of the roughened layer 29 was 0.3 μm thick. The Sn layer is provided (the Sn layer is not shown).

(14) Adhesives A and B for electroless plating for forming an interlayer resin insulation layer were prepared by the following method.
A. Preparation of upper layer electroless plating adhesive
(1). 35% by weight (solid content 80%) of 25% acrylate of cresol novolac type epoxy resin (manufactured by Nippon Kayaku, molecular weight 2500), 3.15 parts by weight of photosensitive monomer (Aronix M315, manufactured by Toa Gosei), antifoaming agent (San Nopco, S-65) 0.5 parts by weight and 3.6 parts by weight of NMP were mixed with stirring.
(2). 12 parts by weight of polyethersulfone (PES), 7.2 parts by weight of epoxy resin particles (manufactured by Sanyo Chemical Co., Ltd., polymer pole) with an average particle diameter of 1.0 μm, and 3.09 weights with an average particle diameter of 0.5 μm After mixing 30 parts by weight of NMP, 30 parts by weight of NMP was further added and stirred and mixed in a bead mill.
(3). Imidazole curing agent (manufactured by Shikoku Chemicals, 2E4MZ-CN) 2 parts by weight, photoinitiator (manufactured by Ciba Geigy, Irgacure I-907), 2 parts by weight, photosensitizer (manufactured by Nippon Kayaku, DETX-S) 0.2 weight And 1.5 parts by weight of NMP were mixed with stirring. These were mixed to prepare an electroless plating adhesive composition A.

B. Preparation of lower layer electroless plating adhesive
(1). 35 parts by weight (solid content 80%) of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500), 4 parts by weight of photosensitive monomer (Aronix M315, manufactured by Toagosei Co., Ltd.), defoamer (Sannopco Made by S-65) and 3.6 parts by weight of NMP were mixed with stirring.
(2). After mixing 12 parts by weight of polyethersulfone (PES) and 14.49 parts by weight of epoxy resin particles (manufactured by Sanyo Kasei, polymer pole) having an average particle size of 0.5 μm, 20 parts by weight of NMP was further added, The mixture was stirred and mixed with a bead mill.

(3). Imidazole curing agent (manufactured by Shikoku Chemicals, 2E4MZ-CN) 2 parts by weight, photoinitiator (manufactured by Ciba Geigy, Irgacure I-907), 2 parts by weight, photosensitizer (manufactured by Nippon Kayaku, DETX-S) 0.2 weight And 1.5 parts by weight of NMP were mixed with stirring. These were mixed to prepare a lower layer electroless plating adhesive B.

(15) First, apply the B electroless plating adhesive (viscosity 1.5 Pa · s) 44 prepared in (14) above on both sides of the substrate using a roll coater and leave it in a horizontal state for 20 minutes. After that, drying is performed at 60 ° C. for 30 minutes, and then an A electroless plating adhesive (viscosity 1.0 Pa · s) 46 is applied using a roll coater and left in a horizontal state for 20 minutes. Then, drying was performed at 60 ° C. for 30 minutes to form an adhesive layer 50 having a thickness of 40 μm (see FIG. 4 (P)).

(16) A photomask film on which a black circle of 85 μmφ was printed was adhered to both surfaces of the substrate on which the adhesive layer 50 was formed, and exposed at 500 mJ / cm ² with an ultrahigh pressure mercury lamp. This was spray-developed with a DMDG (diethylene glycol dimethyl ether) solution to form an opening serving as a via hole of 85 μmφ in the adhesive layer. Furthermore, the substrate was exposed at 3000 mJ / cm ² with an ultra-high pressure mercury lamp and subjected to heat treatment at 100 ° C. for 1 hour and then at 150 ° C. for 5 hours, whereby an opening having excellent dimensional accuracy corresponding to a photomask film ( An interlayer insulating material layer (adhesive layer) 50 having a thickness of 35 μm having a via hole forming opening 48) was formed (see FIG. 4Q). Note that the tin plating layer was partially exposed in the opening serving as the via hole.

(17) The substrate on which the via hole forming opening 48 is formed is immersed in chromic acid for 20 minutes to dissolve and remove the epoxy resin particles present on the surface of the adhesive layer, so that the surface of the adhesive layer 50 has Rmax = 1. A roughened surface 51 was formed by roughening at a depth of about -5 μm, and then immersed in a neutralized solution (manufactured by Shipley Co., Ltd.) and washed with water (FIG. 4 (R)).

(18) A palladium catalyst (manufactured by Atotech) is applied to the substrate 30 on which the surface of the adhesive layer has been roughened (roughening depth: 5 μm), whereby the surface of the adhesive layer 50 and the via hole opening 48 is applied. A catalyst nucleus was applied.

(19) The substrate was immersed in an electroless copper plating bath having the same composition as in (2) to form an electroless copper plating film 52 having a thickness of 0.6 μm on the entire roughened surface 51 (FIG. 4 (S )reference). At this time, since the electroless copper plating film 52 was thin, unevenness following the roughened surface 51 of the adhesive layer 50 was observed on the surface of the electroless plating film 52.

(20) A commercially available photosensitive dry film is attached to the electroless copper plating film 52, a mask is placed, exposed at 100 mJ / cm ² , developed with 0.8% sodium carbonate, and a plating resist with a thickness of 15 μm. 54 (see FIG. 4 (T)).

(21) Next, electrolytic copper plating was performed in accordance with the conditions of (6) above to form an electrolytic copper plating film 56 having a thickness of 15 μm (see FIG. 5 (U)).

(22) After stripping and removing the plating resist 56 with 5% KOH, the electroless plating film 52 under the plating resist 56 is etched and removed with a mixed solution of sulfuric acid and hydrogen peroxide to remove the electroless copper plating film. A conductor circuit 58 and a via hole 60, each having a thickness of 16 μm, are formed of 52 and an electrolytic copper plating film 56 (FIG. 5 (V)). Subsequently, a roughened layer 62 was formed on the surfaces of the conductor circuit 58 and the via hole 60 to obtain a multilayer printed wiring board having three layers on one side (see FIG. 5 (W)). Pd remaining on the roughened surface of the adhesive layer 50 was removed by immersing in chromic acid (800 g / l) for 1 to 10 minutes.

(23) The steps of (15) to (22) were repeated to further laminate one layer of the interlayer resin insulating layer 150 having the via hole 160 (FIG. 5 (X)).

(24) A commercially available solder resist composition was applied to a thickness of 20 μm on both surfaces of the wiring board obtained in (23) above. Next, after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, exposure was performed with 1000 mJ / cm 2 of ultraviolet rays, and DMTG development processing was performed. Further, the solder resist layer (thickness 20 μm) was formed by heating at 80 ° C. for 1 hour, 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours to open the pad portion 71 (opening diameter 200 μm). ) 70 was formed (see FIG. 6).

(25) Next, the substrate 30 on which the solder resist layer 70 is formed is applied to an electroless nickel plating solution having a pH of 5 consisting of 30 g / l nickel chloride, 10 g / l sodium hypophosphite, and 10 g / l sodium citrate. The nickel plating layer 72 having a thickness of 5 μm was formed in the opening 71 by dipping for 20 minutes. Further, the substrate 30 was placed on an electroless gold plating solution composed of 2 g / l potassium gold cyanide, 75 g / l ammonium chloride, 50 g / l sodium citrate and 10 g / l sodium hypophosphite at 93 ° C. The gold plating layer 74 having a thickness of 0.03 μm was formed on the nickel plating layer 72 by dipping for 2 seconds.

(26) A solder paste was printed in the opening 71 of the solder resist layer 70 and reflowed at 200 ° C. to form solder bumps 76U and 76D, thereby producing a printed wiring board having solder bumps.

As described above, according to the printed wiring board of the present invention, it is possible to provide a substrate having a high number of through holes and a small number of layers.

It is a figure which shows the manufacturing process of the multilayer printed wiring board based on the Example of this invention. It is a figure which shows the manufacturing process of the multilayer printed wiring board based on the Example of this invention. It is a figure which shows the manufacturing process of the multilayer printed wiring board based on the Example of this invention. It is a figure which shows the manufacturing process of the multilayer printed wiring board based on the Example of this invention. It is a figure which shows the manufacturing process of the multilayer printed wiring board based on the Example of this invention. It is sectional drawing which shows the multilayer printed wiring board based on the Example of this invention. It is BB sectional drawing of the multilayer printed wiring board shown in FIG. It is a top view of the multilayer core board | substrate of the package board | substrate concerning a prior art.

Explanation of symbols

14 Conductor circuit (conductor layer)
16 Through hole 22 Filler 26a Conductor layer 30 Core substrate (multilayer core substrate)
50 Interlayer resin insulation layer 58 Conductor circuit (conductor layer)
60 Via hole 150 Interlayer resin insulation layer 160 Via hole

Claims (4)

In a multilayer printed wiring board in which an interlayer resin insulation layer and a conductor layer are alternately laminated, and a build-up wiring layer in which each conductor layer is connected by a via hole is formed on both surfaces of the core substrate, The formed through hole is filled with a filler and formed with a conductor layer covering the exposed surface of the filler from the through hole,
A multilayer printed wiring board, wherein a via hole filled with a plating film is connected to the conductor layer. In a multilayer printed wiring board in which an interlayer resin insulation layer and a conductor layer are alternately laminated, and a build-up wiring layer in which each conductor layer is connected by a via hole is formed on both surfaces of the core substrate, The formed through hole is filled with a filler and formed with a conductor layer covering the exposed surface of the filler from the through hole,
A multilayer printed wiring board, wherein a via hole filled with a filler is connected to the conductor layer. 3. The multilayer printed wiring board according to claim 1, wherein a pitch interval between through holes formed in the core substrate is 700 μm or less. 4. The multilayer printed wiring board according to any one of claims 1 to 3, wherein in the build-up wiring layers on both surfaces of the core substrate, a conductor circuit constituting the conductor layer is wired toward an outer peripheral direction of the substrate.

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