JPH11261228A - Multilayered printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayered printed wiring board which has small dimensional changes in the X-Y and Z directions and less surface waviness and warping. SOLUTION: In a multilayered printed wiring board formed by alternately laminating interlayer resin insulating layers 50 and conductor layers 58 upon another on a core substrate 30, the core substrate 30 is formed by laminating six or more layers of prepreg 20 obtained by impregnating cloth, such as the glass cloth, etc., made of fibers having low thermal expansion with a bis(maleimide)triazine resin and having a thickness of <=0.15 mm upon another. The dimensional change and warping of the core substrate 30 formed of the prepreg 20, namely, the multilayered printed wiring board in the X-Y direction are prevented by increasing the number of the prepreg layers 20 by reducing the thickness of each prepreg layer 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board, and more particularly to a multilayer printed wiring board in which interlayer resin insulating layers and conductor layers are alternately laminated on a surface of a core substrate.

[0002]

2. Description of the Related Art In recent years, so-called build-up multilayer wiring boards have been receiving attention due to a demand for higher density of the multilayer wiring boards. This build-up multilayer wiring board is manufactured by a method disclosed in, for example, Japanese Patent Publication No. 4-55555. That is, an insulating material made of a photosensitive adhesive for electroless plating is applied on the core substrate, dried, exposed and developed to form an interlayer insulating material layer having a via hole opening. Next, after roughening the surface of the interlayer insulating material layer by treatment with an oxidizing agent or the like, a plating resist is provided on the roughened surface, and then electroless plating is performed on a portion where no resist is formed, thereby forming a conductor including via holes. Form a circuit pattern. By repeating such a process a plurality of times, a multilayered build-up wiring board can be obtained.

[0003]

In such a multilayer printed wiring board, a build-up layer is formed on a core substrate. In many cases, the positions of conductive pads on the core substrate and via holes in the build-up layer are different. There has been a problem that the connection is deviated and a good connection cannot be obtained. Further, in such a build-up multilayer wiring board, an IC chip is mounted by forming solder bumps on the surface. However, there is a problem that warpage often occurs and the IC chip cannot be mounted.

[0004] The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide an XY system.
It is an object of the present invention to provide a multilayer printed wiring board in which the dimensional change in the direction and the Z direction is small, and the surface undulation and warpage are small.

[0005]

Means for Solving the Problems As a result of intensive studies, the inventors of the present invention have found that the cause of the displacement of the via hole between the core substrate and the correlated insulating layer is due to the displacement of the core substrate in the X-Y direction. I found that. Further, the inventors have found that the cause of the warpage of the multilayer printed wiring board is also that the core substrate is warped. Further, the wiring pattern of the built-up layer formed on the surface of the core substrate is cut or short-circuited. It has been found that the cause is the undulation of the core substrate, and that the cause of the variation in the coating thickness of the roll coater is a poor accuracy in the Z direction. Conventionally, the core substrate has a thickness of about 0.6 to 1 mm by stacking three to five prepregs having a thickness of 0.2 mm. However, when the thickness is 0.
In the case of a 2 mm prepreg, the amount of resin is large, and the substrate formed by stacking the prepregs has warpage, undulation, XY directions,
It was found that the dimensional change in the Z direction could not be suppressed. Therefore, according to the present invention, in a multilayer printed wiring board in which an interlayer resin insulating layer and a conductor layer are alternately laminated on at least one surface of a core substrate, the core substrate has a low thermal expansion fiber cloth impregnated with a resin. 6 prepregs of 0.17mm or less
It is a technical feature that a plurality of layers are laminated and formed by heating and pressing. Further, another invention is a multilayer printed wiring board in which an interlayer resin insulating layer and a conductor layer are alternately laminated on at least one surface of a core substrate, wherein the core substrate is obtained by impregnating a resin with a low thermal expansion fiber cloth with a resin. A multi-layer printed wiring board characterized by being formed by heating and pressing six or more layers of prepreg, and having a thickness per layer of 0.1 mm or less.

According to the invention of the present application, the thickness per sheet of the resin-impregnated prepreg is reduced and the number thereof is increased, so that the dimensional changes, warpage and undulation in the XY directions and Z directions of the core substrate formed by laminating the prepregs are reduced. To prevent. Here, the thickness of the prepreg is preferably 0.17 mm or less (here, the thickness refers to the thickness of the prepreg before pressing). If it exceeds this, the amount of resin increases, and it is difficult to suppress dimensional changes and warpage in the X-Y directions. In addition, 0.05 mm or more is good. If the thickness is less than 0.05 mm, the strength as a substrate is reduced even when a large number of sheets are laminated. When such a prepreg is hot pressed, the thickness per layer is 0.0
The thickness is 3 mm to 0.1 mm, and the thickness per sheet after pressing can be reduced. The number of prepregs is preferably 6 or more. This is because, when the number is small, the warpage increases when the build-up layer cures and contracts. In addition, 15 or less sheets are good. This is because the larger the number, the heavier the substrate.

As the cloth of the low thermal expansion fiber, quartz, glass, alumina, ceramic fiber, titanium oxide,
Although there are aramid fibers, etc., the thermal expansion coefficient is 10 ppm /
A glass cloth which is a fiber of ° C. is optimal.

The resin layer is made of a fluororesin, an epoxy resin, a bismaleimide triazine resin, a polyimide resin,
At least one selected from polyethersulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), polyphenylether (PPE), polyetherimide (PI), and polyphenylene oxide (PPO) It is desirable that this is the case. This is because these are excellent in heat resistance.

In the present invention, it is desirable to use an adhesive for electroless plating as an insulating layer or an interlayer insulating layer constituting the build-up layer. In addition, the adhesive for electroless plating is obtained by dispersing heat-resistant resin particles soluble in a cured acid or oxidizing agent in an uncured heat-resistant resin hardly soluble in an acid or an oxidizing agent. Optimal. This is because, by treating with an acid and an oxidizing agent, the heat-resistant resin particles are dissolved and removed, and a roughened surface composed of an octopus pot-shaped anchor can be formed on the surface, and the adhesion with the upper layer can be increased. .

In the above-mentioned adhesive for electroless plating, the heat-resistant resin particles particularly subjected to the curing treatment include a heat-resistant resin powder having an average particle diameter of 10 μm or less, and an average particle diameter of 2 μm.
agglomerated particles obtained by aggregating a heat-resistant resin powder having a particle size of 2 m or less, a heat-resistant resin powder having an average particle size of 2 to 10 μm and an average particle size of 2
m and a mixture with a heat-resistant resin powder having a mean particle size of 2 or less.
Pseudo particles obtained by adhering at least one of a heat-resistant resin powder or an inorganic powder having an average particle diameter of 2 μm or less to the surface of a 10 μm heat-resistant resin powder, and an average particle diameter of 0.1 μm.
~ 0.8μm heat resistant resin powder and average particle size 0.8μm
It is desirable to use a mixture with a heat-resistant resin powder having a particle size exceeding 2 μm and a heat-resistant resin powder having an average particle diameter of 0.1 to 1.0 μm. This is because these can form a more complicated anchor and can enhance the adhesion.

The depth of the roughened surface is Rmax = 0.0
1-20 μm is preferred. This is to ensure adhesion. In particular, in the semi-additive method, 0.1 to 5 μm is preferable. This is because the electroless plating film can be removed while ensuring adhesion.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A process for manufacturing a printed wiring board according to an embodiment of the present invention will be described below. (1) Produce a core substrate. After immersing the cloth of low thermal expansion fiber in an impregnating liquid in which uncured thermosetting resin (epoxy resin) is dissolved in an organic solvent, or an impregnating liquid in which a thermoplastic resin is dissolved in an organic solvent, the surface of the cloth is Squeeze with rubber rollers or resin blades,
The prepreg is dried to form a B-stage prepreg having a thickness of 0.17 mm or less.

[0013] Six to fifteen B-stage prepregs having a thickness of 0.17 mm or less are laminated, and a
A copper foil of up to 20 μm is laminated and hot pressed to form a copper-clad laminate. The heating temperature depends on the resin,
0 ° C. The thickness per layer of the prepreg after the hot pressing is 0.1 mm or less. The copper clad laminate is etched to form a conductor circuit on the surface. Further, a roughened layer made of copper-nickel-phosphorus is formed on the lower conductive circuit surface of the wiring board. The roughened layer is formed by electroless plating. As the plating solution composition, the copper ion concentration, the nickel ion concentration, and the hypophosphite ion concentration were each 2.
2 × 10 ^{-2 to} 4.1 × 10 ^-2 mol / l, 2.2 × 10
^{−3 to} 4.1 × 10 ⁻³ mol / l, 0.20 to 0.25 m
ol / l is desirable. This is because the crystal structure of the film deposited in this range has a needle-like structure, and thus has an excellent anchor effect. A complexing agent or an additive may be added to the electroless plating solution in addition to the above compounds.

Other methods of forming the roughened layer include the above-described oxidation-reduction treatment and a method of forming a roughened surface by etching the copper surface along grain boundaries. Note that a through hole for electrically connecting the wiring layer on the front surface and the back surface is formed in the core substrate. A resin may be filled between the through hole and the conductor circuit of the core substrate to improve the smoothness of the substrate.

(2) Next, an interlayer resin insulating layer is formed on the wiring board manufactured in the above (1). In particular, in the present invention, it is desirable to use the above-mentioned adhesive for electroless plating as an interlayer resin insulating material.

(3) After the formed adhesive layer for electroless plating is dried, openings for forming via holes are provided if necessary. In the case of a photosensitive resin, an opening for forming a via hole is formed in the adhesive layer by exposing and developing and then thermosetting, and in the case of a thermosetting resin, by thermosetting and then laser processing. Section is provided.

(4) Next, the epoxy resin particles present on the surface of the cured adhesive layer are dissolved and removed with an acid or an oxidizing agent to roughen the surface of the adhesive layer. here,
As the acid, it is possible to use phosphoric acid, hydrochloric acid, sulfuric acid, or an organic acid such as formic acid or acetic acid, but it is particularly preferable to use an organic acid. This is because, when the roughening treatment is performed, the metal conductor layer exposed from the via hole is hardly corroded. On the other hand, it is desirable to use chromic acid and permanganate (such as potassium permanganate) as the oxidizing agent.

(5) Next, a catalyst nucleus is applied to the wiring board whose surface of the adhesive layer is roughened. It is desirable to use a noble metal ion or a noble metal colloid for providing the catalyst nucleus, and generally, palladium chloride or a palladium colloid is used. Note that heat treatment is preferably performed to fix the catalyst core. Palladium is preferred as such a catalyst core.

(6) Next, electroless plating is applied to the surface of the adhesive for electroless plating to form an electroless plating film on the entire roughened surface. The thickness of the electroless plating film is 1 to 5 μm, and more preferably 2 to 3 μm. Next, a plating resist is formed on the electroless plating film. As the plating resist composition, it is particularly desirable to use a composition comprising an acrylate of a cresol novolak or a phenol novolak type epoxy resin and an imidazole curing agent, but it is also possible to use a commercially available dry film.

(7) Next, electrolytic plating is applied to the portion where the plating resist is not formed to form a conductor circuit and a via hole. It is desirable to use copper plating as the electroless plating.

(8) After removing the plating resist, the electroless plating film is dissolved and removed with a mixed solution of sulfuric acid and hydrogen peroxide or an etching solution such as sodium persulfate and ammonium persulfate. Independent conductor circuits.

(9) Next, a roughened layer is formed on the surface of the conductor circuit. Examples of the method of forming the roughened layer include an etching process, a polishing process, an oxidation-reduction process, and a plating process. The oxidation-reduction treatment is performed by using NaOH (10 g / l), NaClO ₂ (40 g / l).
/ L), Na ₃ PO ₄ (6 g / l) in an oxidation bath (blackening bath), NaOH (10 g / l), NaBH ₄ (5 g / l).
l) is used as a reducing bath.

When forming a roughened layer of a copper-nickel-phosphorus alloy layer, it is deposited by electroless plating. As an electroless plating solution for this alloy, copper sulfate 1-4
0 g / l, nickel sulfate 0.1-6.0 g / l, citric acid 10-20 g / l, hypophosphite 10-100 g / l
1, boric acid 10 to 40 g / l, surfactant 0.01 to 1
It is desirable to use a plating bath having a liquid composition of 0 g / l.

(10) Next, an adhesive layer for electroless plating is formed on the substrate as an interlayer resin insulating layer. (11) Further, the steps (3) to (8) are repeated to provide a further upper layer conductive circuit, and a flat conductive pad functioning as a solder pad and a via hole are formed. (12) Next, a roughening layer is provided on the surface of the conductive pad and the via hole. The method of forming the roughened layer is the same as that described in (9).

(13) Next, a solder resist composition is applied to both sides of the printed wiring board after the treatment of the above (12). When applying a solder resist layer to both sides of the printed wiring board, sandwich the printed wiring board between a pair of application rolls of a roll coater in a state where the printed wiring board is set upright, and transport the printed wiring board from the lower side to the upper side to remove the printed circuit board. It is desirable to apply the solder resist composition on both sides simultaneously. The reason for this is that the current basic specifications of printed wiring boards are both sides,
Curtain coat method (flow resin from top to bottom like a waterfall,
This is because the method of applying the substrate by passing it through the resin <curtain>) can only be applied on one side. The above-mentioned solder resist composition can be used for the above-mentioned method of applying simultaneously on both sides. That is, since the above-mentioned solder resist composition has a viscosity of 1 to 10 Pa · s at 25 ° C., it does not flow even when the substrate is set upright and the transfer is good.

(14) Next, the coating film of the solder resist composition is dried at 60 to 80 ° C. for 5 to 60 minutes, and a photomask film having an opening formed thereon is placed on the coating film to expose and develop. The processing forms an opening exposing the pad portion of the conductor circuit. The coating film having an opening formed in this way is further treated at 80 ° C to 150 ° C for 1 to 1 hour.
It is cured by heat treatment for 10 hours. Thereby, the solder resist layer having the opening is in close contact with the roughened layer provided on the surface of the conductor circuit.

Here, the diameter of the opening may be larger than the diameter of the pad, and the pad may be completely exposed. In this case, even if the photomask is displaced, the pad is not covered with the solder resist, the solder resist does not contact the solder body, and the solder body does not become constricted, so that cracks hardly occur. vice versa,
The diameter of the opening can be smaller than the diameter of the pad. In this case, the roughened layer on the pad surface and the solder resist are in close contact with each other. Further, when the so-called semi-additive method is adopted, the depth of the roughened layer of the adhesive for electroless plating is reduced (1 to 3 μm), and the pad is easily peeled off because there is no plating resist. By making the opening diameter of the opening smaller than the pad diameter and covering a part of the pad with a solder resist layer, pad peeling can be suppressed.

(15) Further, a reinforcing layer is formed. The reinforcing layer is formed by printing a resin composition composed of, for example, an acrylate of an epoxy resin, polyethersulfone (PES), epoxy resin particles, and an imidazole curing agent, performing an ultraviolet exposure treatment, and further performing a heat treatment at 80 ° C. to 150 ° C. for 1 to 10 hours. To form a reinforcing layer having a thickness of 5 to 50 μm.

(16) Next, a "nickel-gold" metal layer is formed on the solder pad exposed from the opening. (17) Next, a solder body is supplied onto the solder pad portion exposed from the opening. As a method of supplying the solder body, a solder transfer method or a printing method can be used. Here, in the solder transfer method, a solder foil is attached to a prepreg, and the solder foil is etched leaving only a portion corresponding to an opening portion to form a solder pattern to form a solder carrier film. Is applied to a solder resist opening portion of a substrate, and then laminated such that a solder pattern is in contact with a pad, which is heated and transferred. on the other hand,
The printing method is a method in which a metal mask having a through-hole provided at a position corresponding to a pad is placed on a substrate, and a solder paste is printed and heated.

[0030]

Next, a method of manufacturing a multilayer printed wiring board according to an embodiment of the present invention will be described. Here, first,
Preparation of adhesive composition for electroless plating used for production of multilayer printed wiring board, lower interlayer resin insulation agent, resin filler,
The reinforcing layer composition of the solder resist layer will be described. A. Preparation of adhesive composition for electroless plating Cresol novolak type epoxy resin (Nippon Kayaku:
35% by weight of a 25% acrylate having a molecular weight of 2500)
Photosensitive monomer (Toagosei Co., Ltd .: trade name Aronix M3)
15) 3.15 parts by weight of an antifoaming agent (S-6 manufactured by San Nopco)
5) 0.5 parts by weight and 3.6 parts by weight of NMP were mixed with stirring.

Polyether sulfone (PES) 12
After mixing 7.2 parts by weight of an average particle diameter of 1.0 μm and 3.09 parts by weight of an epoxy resin particle (manufactured by Sanyo Kasei Co., Ltd., polymer pole) of 3.09 parts by weight, NMP30 Parts by weight were added and mixed by stirring with a bead mill.

2 parts by weight of an imidazole curing agent (trade name: 2E4MZ-CN, manufactured by Shikoku Chemicals), 2 parts by weight of a photoinitiator (Irgacure I-907, manufactured by Ciba Geigy), and a photosensitizer (DETX-S, manufactured by Nippon Kayaku) 0.2 parts by weight, NMP
1.5 parts by weight were stirred and mixed. These were mixed to obtain an adhesive composition for electroless plating.

B. Preparation of lower interlayer resin insulation agent Cresol novolak type epoxy resin (Nippon Kayaku:
35% by weight of a 25% acrylate having a molecular weight of 2500)
Photosensitive monomer (Toagosei Co., Ltd .: trade name Aronix M3)
15) 4 parts by weight, antifoaming agent (S-65, manufactured by San Nopco)
0.5 parts by weight and 3.6 parts by weight of NMP were stirred and mixed.

Polyether sulfone (PES) 12
14.49 parts by weight of an epoxy resin particle (manufactured by Sanyo Chemical Industries, trade name: Polymer Pole) having an average particle size of 0.5 μm.
Parts by weight, 30 parts by weight of NMP were further added, and the mixture was stirred and mixed by a bead mill.

2 parts by weight of an imidazole curing agent (trade name: 2E4MZ-CN, manufactured by Shikoku Chemicals), 2 parts by weight of a photoinitiator (Irgacure I-907, manufactured by Ciba Geigy), and a photosensitizer (DETX-S, manufactured by Nippon Kayaku) 0.2 parts by weight, NMP
1.5 parts by weight were stirred and mixed. These were mixed to obtain a lower layer resin insulating composition.

C. Preparation of Resin Filler 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell, molecular weight: 310, trade name: YL983U) and SiO ₂ spherical particles having an average particle diameter of 1.6 μm and coated with a silane coupling agent on the surface ( CRS1101-CE, manufactured by Admatech, where the maximum particle size is 170 parts by weight of the thickness of the inner layer copper pattern to be described later (12 μm or less), and 1.5 parts by weight of a leveling agent (manufactured by San Nopco, trade name Perenol S4) Was kneaded with three rolls. This gives the mixture a viscosity of 4 at 23 ± 1 ° C.
It was adjusted to 5,000 to 49,000 cps. Imidazole curing agent (Shikoku Chemicals, trade name: 2E4M
Z-CN) 6.5 parts by weight. These were mixed to adjust the resin filler.

D. Preparation of reinforcing layer composition of solder resist layer Cresol novolak type epoxy resin (Nippon Kayaku:
35% by weight of a 25% acrylate having a molecular weight of 2500)
Photosensitive monomer (Toagosei Co., Ltd .: trade name Aronix M3)
15) 4 parts by weight, antifoaming agent (S-65, manufactured by San Nopco)
0.5 parts by weight and 3.6 parts by weight of NMP were stirred and mixed. 12 parts by weight of polyether sulfone (PES), epoxy resin particles (Sanyo Kasei's product name Polymer Pole)
Was mixed with 14.49 parts by weight of a powder having an average particle size of 0.5 μm, and then 30 parts by weight of NMP was further added, followed by stirring and mixing with a bead mill. Imidazole curing agent (Shikoku Chemicals: trade name 2E4MZ
-CN) 2 parts by weight, photoinitiator (Irgacure I-907 manufactured by Ciba Geigy) 2 parts by weight, photosensitizer (Nippon Kayaku:
0.2 parts by weight of DETX-S) and 1.5 parts by weight of NMP were stirred and mixed. These were mixed to obtain a resin composition for a reinforcing layer.

Next, the manufacturing process of the multilayer printed wiring board will be described with reference to the drawings. (1) A precursor solution of a bismaleimide triazine resin is immersed in a glass cloth 10, squeezed with a rubber roller, adjusted to a thickness of 0.12 mm, sandwiched between Teflon sheets, and dried at 80 ° C. for 3 hours. Thus, the prepreg 20 in the B-stage state was set to have a thickness of 0.1 mm (see FIG. 1).

As shown in FIG. 2, this prepreg 20 is
Three sheets are laminated (only eight sheets are shown for convenience), and a copper foil 32 having a thickness of 12 μm is further laminated on both surfaces thereof. These are 20
Heat at a pressure of kg / cm ² at a temperature of 150 ° C. for 3 hours,
As shown in FIG. 3, a copper-clad bismaleimide triazine resin substrate 30A having a thickness of about 0.8 mm is obtained. Here, the thickness of each prepreg 20 is 0.06 mm on average. After drilling holes in the copper clad plate 30A to form a plating resist, as shown in FIG. 4, electroless plating is performed to form through holes 36, and the copper foil is etched in a pattern according to a conventional method. Thereby, the inner layer copper pattern 34 was formed on both surfaces of the substrate to obtain a core substrate.

(2) The core substrate 30 on which the inner layer copper pattern 34 is formed is washed with water and dried, and then NaOH (10 g /
l), NaClO ₂ (40 g / l), Na ₃ PO ₄ (6
g / l) was used as an oxidation bath (blackening bath), and a roughened layer 38 was provided on the entire surface of the conductor circuit 34 and the through hole 36 as shown in FIG. (3) The resin filler 40 formed by the above-described manufacturing method is applied to both surfaces of the substrate 30 using a roll coater as shown in FIG. 1 hour at 100 ° C, 120
The composition was cured by performing a heat treatment at 300C for 3 hours, 150C for 1 hour, and 180C for 7 hours. That is, in this step, the resin filler 40 is filled between the inner layer copper patterns 34 or in the through holes 36.

(4) The substrate 30 after the processing of the above (3)
As shown in FIG. 7, the resin filler 40 does not remain on the surface of the inner layer copper pattern 34 or the land surface of the through hole 36 by belt sanding using # 600 belt abrasive paper (manufactured by Sankyo Rikagaku). So that it is polished. Next, buffing was performed to remove scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate 40. Then, as shown in FIG. 8, the resin filler 40 filled in the through holes 36 and the like is formed.
Also, the roughened layer 38 on the upper surface of the conductor circuit 34 is removed, and both surfaces of the substrate are smoothed with the resin filler 40, and the resin filler 40 and the side surface of the conductor circuit 34 adhere to each other via the roughened layer 38, The core substrate 30 in which the inner wall of the through hole 36 and the resin filler 40 were in close contact with each other via the roughened layer 38 was obtained. That is, by this step, the surface of the resin filler 40 and the inner layer copper pattern 3
4 are coplanar. Here, the Tg point of the cured resin is 155.6 ° C., and the coefficient of linear thermal expansion is 44.5 × 10 ⁻⁶ / ° C.
Met.

(5) Further, as shown in FIG. 9, a 2.5 μm-thick roughened layer (irregular layer) 42 of a Cu—Ni—P alloy is formed on the exposed top surface of the conductor circuit 34 and the land of the through hole 36. 0.3 μm-thick S is formed on the surface of the roughened layer.
An n-layer (not shown) was provided.

The method of forming the roughened layer (irregular layer) 42 is as follows. The substrate 30 was acid-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid to provide a Pd catalyst. After activating this catalyst, copper sulfate 8 g / l and nickel sulfate 0 0.6 g / l, citric acid 15 g / l, sodium hypophosphite 29 g / l,
Boric acid 31 g / l, surfactant 0.1 g / l, pH = 9
, And a roughened layer of a Cu-Ni-P alloy was provided on the entire surface of the copper conductor circuit 34 and the through holes (including the inner wall) 36. Then, tin borofluoride 0.1 mol / l, thiourea 1.0 mol
/ L, a temperature of 50 ° C., and a pH = 1.2, and a Cu—Sn substitution reaction is performed, and a 0.3 μm-thick S
An n layer was provided (the Sn layer is not shown).

(6) The above-mentioned (B) is formed on both sides of the substrate 30.
Resin insulation agent (viscosity 1.5Pa.
s) 44 is applied by a roll coater as shown in FIG.
After being left in a horizontal state for 20 minutes, drying is performed at 60 ° C. for 30 minutes. Then, an adhesive 46 for electroless plating according to the manufacturing method of (A) is applied using a roll coater, and is then left in a horizontal state for 20 minutes. After standing, drying was performed at 60 ° C. for 30 minutes to form an adhesive layer 50 having a thickness of 35 μm.

(7) A photomask film (not shown) on which a black circle of 85 μmφ is printed is brought into close contact with both surfaces of the substrate on which the adhesive layer 50 is formed in the above (6), and is 500 mJ / cm by an ultra-high pressure mercury lamp. Exposure at ² . This is DMDG
By performing spray development with a solution, an opening 48 serving as a 85 μmφ via hole was formed in the adhesive layer 50 as shown in FIG. Further, the substrate was exposed at 3000 mJ / cm ² by an ultra-high pressure mercury lamp, and was exposed at 100 ° C. for 1 hour.
After that, by performing a heat treatment at 150 ° C. for 5 hours,
35 μm thick with openings (openings for forming via holes) 48 with excellent dimensional accuracy equivalent to a photomask film
An interlayer insulating material layer (adhesive layer) 50 was formed. Note that a tin plating layer (not shown) was partially exposed in the opening 48 serving as a via hole.

(8) The substrate subjected to the process (7) is
Immersed in 800 g / l chromic acid at 70 ° C. for 19 minutes,
The surface was roughened by dissolving and removing the resin particles to obtain a roughened surface 51 having a depth of 3 μm as shown in FIG. Then, it was immersed in a neutralization solution (manufactured by Shipley Mori) and washed with water. further,
By applying a palladium catalyst (manufactured by Atotech) to the surface of the roughened substrate 30, a catalyst nucleus was attached to the surface of the interlayer insulating material layer 50 and the inner wall surface of the via hole opening 48.

(9) The substrate was immersed in an electroless copper plating bath having the following composition to form an electroless copper plating film 52 having a thickness of 1.6 μm on the entire rough surface as shown in FIG. Electroless plating solution EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l Electroless plating conditions 30 at a liquid temperature of 70 ° C. Minute

(10) A commercially available photosensitive dry film is adhered to the electroless copper plating film, and a mask is placed on the film.
Exposure at mJ / cm ² and development processing with 0.8% sodium carbonate provided a plating resist 54 having a thickness of 15 μm as shown in FIG.

(11) Next, electrolytic copper plating was performed under the following conditions to form an electrolytic copper plating film 56 having a thickness of 15 μm as shown in FIG. Electrolytic plating solution Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (trade name: Capparaside GL, manufactured by Atotech Japan) 1 ml / l Electroplating conditions Current density 1 A / dm ² hours 30 minutes Temperature Room temperature

(12) The plating resist 54 is made of 5% KOH
Then, etching is performed with a mixed solution of sulfuric acid and hydrogen peroxide to dissolve and remove the electroless plating film 52 under the plating resist 54 as shown in FIG.
2 and an electrolytic copper plating film 56, a conductor circuit 58 having a thickness of 18 μm and a via hole 60 were formed. In addition, 70
The surface of the adhesive layer for electroless plating between the conductor circuit 58 and the via hole 60 was subjected to an etching treatment of 1 μm at a temperature of 800 ° C. for 3 minutes in 800 g / l chromic acid to remove the palladium catalyst on the surface.

(13) Substrate 30 on which conductor circuit 58 is formed
Was prepared by adding 8 g / l of copper sulfate, 0.6 g / l of nickel sulfate, 15 g / l of citric acid, 29 g / l of sodium hypophosphite, 31 g / l of boric acid, and 0.1 g / l of a surfactant.
= 9, and a thickness of 3 μm was applied to the surface of the conductor circuit 58 and the via hole 60 as shown in FIG.
A roughened layer 62 made of copper-nickel-phosphorus was formed.
When the roughened layer 62 was analyzed by EPMA (X-ray fluorescence spectrometer), Cu 98 mol%, Ni 1.5 mol%, P
The composition ratio was 0.5 mol%. Then, a Cu—Sn substitution reaction was performed under the conditions of tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l, temperature 50 ° C., and pH = 1.2, and a 0.3 μm thick layer was formed on the surface of the roughened layer 62. (The Sn layer is not shown).

(14) By repeating the steps (2) to (10), a conductor circuit in a further upper layer is formed. That is, an interlayer resin insulating agent (for the lower layer) is applied to both surfaces of the substrate 30 with a roller to form an insulating agent layer 144. Also, an adhesive for electroless plating (for upper layer) is applied on the insulating layer 144 using a roll coater, and the adhesive layer 1 is formed.
46 are formed (see FIG. 18). A photomask film is brought into close contact with both sides of the substrate 30 on which the insulating layer 144 and the adhesive layer 146 are formed, exposed and developed, and the interlayer resin insulating layer 15 having an opening (opening for forming a via hole) 148 is formed.
After forming 0, the surface of the interlayer resin insulating layer 150 is roughened (see FIG. 19). Thereafter, an electroless copper plating film 152 is formed on the surface of the substrate 30 subjected to the surface roughening treatment (see FIG. 20). Subsequently, after a plating resist 154 is provided on the electroless copper plating film 152, an electrolytic copper plating film 156 is formed on a portion where no resist is formed (see FIG. 21).
Then, after the plating resist 154 is peeled off with KOH, the electroless plating film 15 under the plating resist 154 is removed.
2 and the conductor circuit 158 and the via hole 160
Is formed (see FIG. 22). Further, the conductor circuit 158
Then, a roughened layer 162 is formed on the surface of the via hole 160 to complete a multilayer printed wiring board (see FIG. 23). In the process of forming the upper conductive circuit, S
No n-substitution is performed.

(15) Then, solder bumps are formed on the above-mentioned multilayer printed wiring board. First, adjustment of the solder resist composition for a solder bump will be described. A cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) is provided with 46.67 parts by weight of a photosensitizing oligomer (molecular weight 4000) in which 50% of epoxy groups are acrylated, and a bisphenol A type epoxy resin (manufactured by Yuka Shell, shrimp coat 10).
01) 14.121 parts by weight, 1.6 parts by weight of an imidazole curing agent (manufactured by Shikoku Chemicals, trade name: 2E4MZ-CN), and a polyvalent acrylic monomer as a photosensitive monomer (manufactured by Nippon Kayaku, trade name: R604) 1 0.5 parts by weight, similarly polyvalent acrylic monomer (manufactured by Kyoeisha Chemical, trade name: DPE6A)
3.0 parts by weight of a leveling agent composed of an acrylate polymer (manufactured by Kyoeisha, trade name: Polyflow No. 75:
0.36 parts by weight, and 2.0 parts by weight of Irgacure I907 (manufactured by Ciba-Geigy) as a photoinitiator, and 0.2 parts by weight of DETX-S (manufactured by Nippon Kayaku) as a photosensitizer. 1.0 part by weight of DGDG (dimethylene glycol dimethyl ether) was added to obtain a solder resist composition having a viscosity adjusted to 1.4 ± 0.3 Pa · s at 25 ° C. The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type) at 60 rpm with a rotor No. In the case of 4, 6 rpm, the rotor No. According to 3.

(16) The solder resist composition was applied to the substrate to a thickness of 20 μm. Next, after performing a drying process at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes,
It was exposed to ultraviolet rays of mJ / cm ² and subjected to DMTG development processing. Further, at 80 ° C. for 1 hour, at 100 ° C. for 1 hour, 12
Heat treatment at 0 ° C. for 1 hour and 150 ° C. for 3 hours,
As shown in FIG. 24, a solder resist layer (thickness: 20 μm) 70 having an opening 71 corresponding to the pad portion (opening diameter: 200 μm) was formed.

(17) The resin composition for reinforcing layer for reinforcing the solder resist layer of (D) is applied around the openings of the solder resist, exposed to 1000 mJ / cm ² , and further exposed at 80 ° C. for 1 hour. Time, 1 hour at 100 ° C, 12
Heat treatment at 0 ° C. for 1 hour and 150 ° C. for 3 hours,
As shown in FIG. 25, a reinforcing layer 78 having a thickness of 40 μm was formed.

(18) Next, the substrate 30 on which the solder resist layer 70 and the reinforcing layer 78 are formed is replaced with a nickel chloride 30
g / l, 10 g / l of sodium hypophosphite, and 10 g / l of sodium citrate, were immersed in an electroless nickel plating solution having a pH of 5 for 20 minutes. As shown in FIG. Was formed. Further, the substrate 30 is made of 2 g of potassium potassium cyanide.
/ L, 75 g / l of ammonium chloride, 50 g / l of sodium citrate, and 10 g / l of sodium hypophosphite at 93 ° C for 23 seconds under an electroless gold plating solution. A 0.03 μm gold plating layer 74 was formed. (19) The opening 71 of the solder resist layer 70
Then, a solder paste is printed and reflowed at 200 ° C. to form a solder bump 76. Since this substrate was formed for multi-piece production, a printed wiring board having several solder pumps was manufactured by cutting the completed substrate.

(Comparative Example) The multilayer printed wiring board of the comparative example has the wiring layers built up in the same manner as the multilayer printed wiring board of the embodiment, but differs only in the core substrate. That is, a core substrate having a thickness of 0.8 mm obtained by stacking four prepregs having a thickness of 0.2 mm was used. Note that the multilayer printed wiring boards of the example and the comparative example both have a vertical length of 340.
mm and a width of 250 mm.

A. Misalignment between inner layer pad of core substrate and via hole. In the example, no displacement was found, but in the comparative example, displacement between the via hole and the inner layer pad was confirmed. B. The amount of warpage The amount of warpage of the multilayer printed wiring board of the example is 70 μm at the maximum.
It was 150 μm in the comparative example. Thus, it has been found that the multilayer printed wiring board of the example can suppress the dimensional change and the amount of warpage in the XY directions. C. Thickness Accuracy In the example, the thickness of the core substrate was 0.8 ± 0.05 mm, and no defect due to the variation in the thickness of the core substrate occurred.

In the comparative example, the thickness of the core substrate is 0.8 ± 0.2.
The thickness was 10 mm, and the coating thickness of the roll coater fluctuated, so that openings for via holes were not formed or peeling occurred due to excessive development.

D. Surface undulation In the example, the undulation of the surface of the core substrate is 0.010 mm.
In this case, there was no defect that the pattern was cut or short-circuited.

In the comparative example, the undulation of the surface of the core substrate was 0.030 mm, and the plating resist did not follow,
Due to poor exposure and development, the pattern was cut, or a plating solution penetrated under the plating resist between the patterns to make the patterns conductive, thereby causing a short circuit.

[0062]

As described above, according to the printed wiring board of the present invention, dimensional changes in the X-Y and Z directions can be suppressed. Therefore, the inner layer pad (through hole) of the core substrate
And via holes in the interlayer resin insulation layer can be appropriately connected. In addition, since the amount of undulation and warpage of the surface can be suppressed, the IC chip can be reliably mounted.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a manufacturing process of a multilayer printed wiring board according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 7 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 8 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 9 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 10 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 11 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 12 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 13 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 14 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 15 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 16 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 17 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 18 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 19 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 20 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 21 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 22 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 23 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 24 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 25 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 26 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 glass cloth 20 prepreg 30 copper-clad bismimide triazine resin substrate 32 copper foil 48 opening for via hole 50 interlayer resin insulation layer 52 electroless plating 56 electrolytic plating 60 via hole

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Takashi Kariya, Inventor 1-1, northern Ibigawa-cho, Ibi-gun, Gifu Prefecture Inside the Ogaki-Kita Plant of Ibiden Co., Ltd.

Claims (4)

[Claims] 1. A multilayer printed wiring board in which an interlayer resin insulating layer and a conductor layer are alternately laminated on at least one surface of a core substrate, wherein the core substrate has a low thermal expansion fiber cloth impregnated with resin. A multilayer printed wiring board formed by laminating six or more prepregs each having a thickness of 0.17 mm or less. 2. A multilayer printed wiring board in which an interlayer resin insulating layer and a conductor layer are alternately laminated on at least one surface of a core substrate, wherein the core substrate comprises a prepreg obtained by impregnating a resin into a low thermal expansion fiber cloth. A multilayer printed wiring board formed by heat-pressing at least six layers and having a thickness of 0.1 mm or less per layer. 3. The multilayer printed wiring board according to claim 1, wherein the low thermal expansion fiber cloth is a glass cloth. 4. The resin layer is made of a fluorine resin, an epoxy resin, a bismaleimide triazine resin, a polyimide resin,
At least one selected from polyethersulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), polyphenylether (PPE), polyetherimide (PI), and polyphenylene oxide (PPO) The multilayer printed wiring board according to any one of claims 1 to 3, which is as described above.