JP2008263095A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the manufacture processes of a semiconductor device in a MOS structure. <P>SOLUTION: An insulating layer is formed on a semiconductor substrate, and a first trench reaching the semiconductor substrate from the insulating layer is formed selectively on the semiconductor substrate where the insulating layer is formed. An insulating film is formed on the surface of the first trench, and a trench gate is formed by embedding polysilicon up to a surface where the insulating layer is formed inside the first trench through the insulating film. Further, the insulating layer is thinned by etching the insulating layer, and the polysilicon is exposed from the surface of the insulating layer. Then, an oxidized layer is formed by oxidizing the polysilicon exposed from the surface of the insulating layer. Further, with the oxidized layer as a mask, a second trench reaching the semiconductor substrate from the surface of the insulating layer is formed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a vertical MOS semiconductor device.

  MOS field-effect transistors (MOSFETs) are usually fabricated by performing processes such as photolithography, ion implantation, thermal oxidation, and film formation on a semiconductor substrate such as silicon. A process with a small number of steps is desired. In particular, photolithography requires a series of steps of resist coating, pre-baking, exposure by an exposure apparatus, development, and drying. If it is used frequently, the throughput is significantly reduced, resulting in an increase in cost.

Further, in a vertical MOS semiconductor device in which a trench gate is formed as described in Patent Document 1, in the process of forming a trench contact as the miniaturization progresses, a positional shift at the time of exposure is performed. May occur. Such misalignment greatly affects the characteristics of the manufactured semiconductor device.
Japanese translation of PCT publication No. 2002-520851

  The present invention provides a method for manufacturing a semiconductor device with a small number of processes.

  According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming an insulating layer on a semiconductor substrate; and selectively reaching the semiconductor substrate from the insulating layer on the semiconductor substrate on which the insulating layer is formed. Forming a first trench, and forming an insulating film on the surface of the first trench, and passing through the insulating film to the surface where the insulating layer is formed in the first trench. Forming a trench gate by embedding, thinning the insulating layer by etching the insulating layer, exposing the polysilicon from the surface of the insulating layer, and exposing from the surface of the insulating layer. Forming an oxide layer by oxidizing the polysilicon, and forming a second trench from the surface of the insulating layer to the semiconductor substrate using the oxide layer as a mask. Characterized by comprising the step of. .

  In addition, a method for manufacturing a semiconductor device according to one embodiment of the present invention includes a step of forming an insulating layer over a semiconductor substrate, and the semiconductor substrate on which the insulating layer is formed selectively from the insulating layer to the semiconductor substrate. Forming a first trench to reach, etching the insulating layer in a direction along the surface of the semiconductor substrate to widen the diameter of the first trench, and insulating film on the surface of the first trench Forming a trench gate by embedding polysilicon through the insulating film to the surface where the insulating layer is formed in the first trench, and etching the insulating layer. Thinning the insulating layer to expose the polysilicon from the surface of the insulating layer; and oxidizing and oxidizing the polysilicon exposed from the surface of the insulating layer Forming, said oxide layer as a mask, characterized by comprising a step of forming a second trench extending from the surface of the insulating layer on the semiconductor substrate.

  The method for manufacturing a semiconductor device according to one embodiment of the present invention includes a step of forming a silicon nitride film and a silicon oxide layer on a semiconductor substrate in order from the bottom, and a semiconductor in which the silicon nitride film and the silicon oxide film are formed. Forming a first trench selectively reaching the semiconductor substrate from the silicon nitride film and the silicon oxide film on the substrate; forming an insulating film on a surface of the first trench; A step of forming a trench gate by embedding polysilicon in the first trench to a surface on which the silicon oxide layer is formed; and etching the silicon oxide layer to reduce the thickness of the silicon oxide layer. Exposing the polysilicon from the surface of the silicon oxide film, and exposing the polysilicon from the surface of the silicon oxide film. Forming an oxide layer by oxidizing the polysilicon, the oxide layer as a mask, comprising the a step of etching the semiconductor substrate surface.

  According to the present invention, in the method for manufacturing a semiconductor device, the number of steps at the time of manufacturing can be reduced, so that the manufacturing cost of the semiconductor device can be suppressed.

[First Embodiment]
The first embodiment is a method of manufacturing a semiconductor device having a MOS structure having a trench gate. This embodiment will be described with reference to FIGS. 1A and 1B.

  First, as shown in FIG. 1A (a), an N-type epitaxial layer 12 is formed by depositing silicon doped with P (phosphorus) by epitaxial growth on a single crystal N-type silicon substrate 11 which is a semiconductor substrate. After a SiN (silicon nitride) layer 14 is formed on the surface on which the N-type epitaxial layer 12 is formed, a P-type base layer 13 is formed by ion implantation of B (boron) or the like.

  Thereafter, after applying a photoresist on the SiN layer 14, pre-baking, exposure by an exposure apparatus, and development are performed, thereby forming a resist pattern 15 having an opening only in a region where a trench to be described later is formed.

  Next, as shown in FIG. 1A (b), by removing the SiN layer 14 in the region where the resist pattern 15 is not formed, a pattern composed of the resist pattern 15 and the SiN layer 14a is formed. Thereafter, trench 16 is formed by etching by RIE (Reactive Ion Etching) using resist pattern 15 and SiN layer 14a as a mask. The formed trench 16 penetrates the P-type base layer 13 and is formed by etching a part of the surface of the N-type epitaxial layer 12. Thereby, the P-type base layer 13a and the N-type epitaxial layer 12a in which the trench 16 is formed are formed.

  Next, as shown in FIG. 1A (c), the resist pattern 15 is removed and then thermal oxidation is performed, so that the surface of the trench 16, that is, the P-type base layer 13a forming the trench 16, the N-type A trench oxide layer 17 is formed on the surface of the epitaxial layer 12a.

  Next, as shown in FIG. 1A (d), a trench gate 18 is formed by embedding polysilicon in the trench 16 in which the trench oxide layer 17 is formed. The trench gate 18 is formed so as to be flush with the surface of the SiN layer 34b. Further, the trench gate 18 has high conductivity because P (phosphorus), which is an impurity element for forming the N-type, is contained at a high concentration.

  Next, as shown in FIG. 1B (e), a thin SiN layer 14b is formed by etching the surface of the SiN layer 14a. Specifically, the SiN layer 14b is formed by etching the surface of the SiN layer 14a by an etching method in which only SiN can be etched without etching Si.

  Next, as shown in FIG. 1B (f), an N-type source layer 19 is formed by ion implantation of As (arsenic). At this time, As ions are also implanted into the trench gate 18, but since the trench gate 18 contains N-type impurity ions at a high concentration in order to enhance conductivity, As is implanted. Has no effect.

  Next, as shown in FIG. 1B (g), the portion exposed on the surface of the trench gate 18 is oxidized by performing thermal oxidation. Thereby, the oxide layer 20 is formed. When silicon is oxidized by thermal oxidation or the like, since its volume generally expands, the oxide layer 20 is formed so as to cover the trench gate 18.

Next, as shown in FIG. 1B (h), the SiN layer 14b, the N-type source layer 19, and the P-type base layer 13a in a region where the oxide layer 20 is not formed are removed by etching by RIE or the like. . Specifically, silicon oxide (SiO ₂ ) is not etched, but after removing part of the SiN layer 14b under conditions that allow SiN to be etched, silicon oxide (SiO ₂ ) is not etched, but Si is etched. A part of the N-type source layer 19 and the P-type base layer 13a is removed under possible conditions. As a result, the SiN layer 14c, the N-type source layer 19a, and the P-type base layer 13b where the oxide layer 20 is not formed are etched to form the trench 21.

  Thereafter, as shown in FIG. 1C, the source electrode 22 is formed so as to be buried in the trench 21 and connected to the N-type source layer 19a and the P-type base layer 13b. Further, by forming the drain electrode 23 on the back surface of the semiconductor substrate 11, a MOS structure semiconductor device having a trench gate in the present embodiment is completed.

  In the present embodiment, the oxide layer 20 is used in the step of forming the trench 21 for forming the source electrode 22 by etching the N-type source layer 19. That is, in a general method, a resist pattern is used in the step of etching the N-type source layer 19, but in this embodiment, a photolithography step for forming this resist pattern is not necessary, and the step Can be shortened.

  Specifically, referring to FIG. 2, in a general method, an N-type epitaxial layer 92 is formed on an N-type silicon substrate 91 as shown in FIG. A base layer 93 is formed, an N-type source layer 96 is formed thereon, and a silicon oxide layer 94 is further formed thereon. In the N type epitaxial layer 92, the P type base layer 93, and the N type source layer 96, a trench oxide film 97 and a trench gate 98 are formed in the same manner as described with reference to FIG. Thus, in order to form a trench in the semiconductor device formed as shown in FIG. 2A, a resist pattern 95 as shown in FIG. 2B is formed.

  Specifically, the resist pattern 95 is formed by applying a resist on the silicon oxide film 94 and then performing pre-baking, exposure by an exposure apparatus, and development.

  Thereafter, as shown in FIG. 2C, a part of the silicon oxide film 94 is etched by anisotropic etching such as RIE using the resist pattern 95 as a mask, and only the region where the resist pattern 95 is formed remains. A silicon oxide layer 94a is formed.

  Thereafter, as shown in FIG. 2D, after the resist pattern 95 is removed, one of the N-type source layer 96 and the P-type base layer 93 is formed by anisotropic etching such as RIE using the silicon oxide layer 94a as a mask. The portion is etched, and the N-type source layer 96a and the P-type base layer 93a are etched to form a trench 99. Then, a source electrode is formed so as to be embedded in the trench 99, and a drain electrode is formed on the back surface of the semiconductor substrate 91.

  In this embodiment, since it is not necessary to form the resist pattern 95 shown in FIG. 2, one photolithography process can be reduced and the number of processes can be reduced.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIGS. 3A and 3B.

  First, as shown in FIG. 3A (a), a trench 36 is formed in an N-type epitaxial layer 32, a P-type base layer 33, and a SiN layer 34 on a single-crystal N-type silicon substrate 31 that is a semiconductor substrate. The trench 36 is formed by performing anisotropic etching after the resist pattern 35 is formed by photolithography.

  Next, as shown in FIG. 3A (b), the SiN layer 34 is isotropically etched in a direction parallel to the film surface. Thereby, the SiN layer 34a etched in the direction along the surface of the semiconductor substrate 31 is formed, and the diameter of the trench 36 is widened.

  Next, as shown in FIG. 3A (c), after removing the resist pattern 35, thermal oxidation is performed to obtain the surface of the trench 36, that is, the P-type base layer 33 forming the trench 36, the N-type A trench oxide layer 37 is formed on the surface of the epitaxial layer 32.

  Next, as shown in FIG. 3A (d), a trench gate 38 is formed by embedding polysilicon in the trench 36 in which the trench oxide layer 37 is formed. The trench gate 38 is formed so as to be flush with the surface of the SiN layer 34a. Further, the trench gate 38 has high conductivity because P (phosphorus), which is an impurity element for forming the N-type, is contained at a high concentration.

  Next, as shown in FIG. 3B (e), a thin SiN layer 34b is formed by etching the surface of the SiN layer 34a. Specifically, a thin SiN layer 34b is formed by etching the surface of the SiN layer 34a by an etching method capable of etching only SiN without etching Si.

  Next, as shown in FIG. 3B (f), an N-type source layer 39 is formed by ion implantation of As (arsenic). At this time, As ions are also implanted into the trench gate 38, but the trench gate 38 contains N-type impurity ions at a high concentration in order to enhance conductivity, and therefore As is implanted. Has no effect.

  Next, as shown in FIG. 3B (g), the portion exposed on the surface of the trench gate 38 is oxidized by performing thermal oxidation. Thereby, the oxide layer 40 is formed. When silicon is oxidized by thermal oxidation or the like, since its volume generally expands, the oxide layer 40 is formed so as to cover the trench gate 38.

Next, as shown in FIG. 3B (h), a part of the SiN layer 34b, the N-type source layer 39, and the P-type base layer 33 in the region where the oxide layer 40 is not formed is removed by etching by RIE or the like. . Specifically, silicon oxide (SiO ₂ ) is not etched, but after removing part of the SiN layer 34b under conditions that allow SiN to be etched, silicon oxide (SiO ₂ ) is not etched, but Si can be etched Under certain conditions, the N-type source layer 39 and the P-type base layer 33 are partially removed. As a result, the SiN layer 34c, the N-type source layer 39a, and the P-type base layer 33a where the oxide layer 40 is not formed are etched to form the trench 41.

  Thereafter, a source electrode (not shown) is buried in the trench 41 so as to be connected to the N-type source layer 39a and the P-type base layer 33a. Further, by forming a drain electrode (not shown) on the back surface of the semiconductor substrate 31, the MOS structure semiconductor device having a trench gate in the present embodiment is completed.

  In the present embodiment, the oxide layer 40 is used in the step of forming the trench 41 by etching the N-type source layer 39. That is, in a general method, a resist pattern is used in the step of etching the N-type source layer 39. However, in this embodiment, a photolithography step for forming the resist pattern is not necessary, and the manufacturing process is performed. The process can be shortened. In the present embodiment, since the SiN layer 34b having a wide aperture can be formed by performing isotropic etching, the oxide film 40 covering the trench gate 38 in a wide range can be formed. It is possible to increase the distance between the gate 38 and the trench 41.

[Third Embodiment]
Next, a third embodiment of the present invention will be described with reference to FIGS. 4A and 4B.

  First, as shown in FIG. 4A, an N-type epitaxial layer 52 is formed by depositing silicon doped with P (phosphorus) by epitaxial growth on a single crystal N-type silicon substrate 51 which is a semiconductor substrate. A SiN (silicon nitride) layer 54 is formed on the surface on which the N-type epitaxial layer 52 is formed, and then a P-type base layer 53 is formed by ion implantation of B (boron) or the like. A silicon oxide layer 61 is formed on the (silicon nitride) layer 54. Thereafter, after a photoresist is applied on the silicon oxide layer 61, pre-baking, exposure by an exposure apparatus, and development are performed to form a resist pattern 55 that is open only in a region where a trench to be described later is formed.

  Next, as shown in FIG. 4A (b), by removing the silicon oxide layer 61 and the SiN layer 54 in the region where the resist pattern 55 is not formed, the resist pattern 55, the silicon oxide layer 61a and the SiN layer 54a are removed. A pattern is formed. Thereafter, trench 56 is formed by etching by RIE (Reactive Ion Etching) using resist pattern 55 and SiN layer 54a as a mask. The formed trench 56 penetrates the P-type base layer 53 and is formed by etching a part of the surface of the N-type epitaxial layer 52. Thereby, the P-type base layer 53a and the N-type epitaxial layer 52a in which the trench 56 is formed are formed.

  Next, as shown in FIG. 4A (c), after removing the resist pattern 55, thermal oxidation is performed to obtain the surface of the trench 56, that is, the P-type base layer 53a forming the trench 56, the N-type A trench oxide layer 57 is formed on the surface of the epitaxial layer 52a.

  Next, as shown in FIG. 4A (d), a trench gate 58 is formed by embedding polysilicon in the trench 56 in which the trench oxide layer 57 is formed. The trench gate 58 is formed so as to be flush with the surface of the silicon oxide layer 61a. The trench gate 58 has high conductivity because P (phosphorus), which is an impurity element for forming the N-type, is contained at a high concentration.

Next, as shown in FIG. 4B (e), the silicon oxide layer 61a is removed by etching. Specifically, the silicon oxide layer 61a is removed by an etching method that can etch only silicon oxide (SiO ₂ ) without etching Si, and the surface of the SiN layer 54a is exposed.

  Next, as shown in FIG. 4B (f), an N-type source layer 59 is formed by ion implantation of As (arsenic). At this time, As ions are also implanted into the trench gate 58. Since the trench gate 58 contains N-type impurity ions at a high concentration in order to enhance conductivity, As is implanted. Has no effect.

  Next, as shown in FIG. 4B (g), the polysilicon exposed on the surface of the trench gate 58 is oxidized by performing thermal oxidation. Thereby, the oxide layer 60 is formed. When silicon is oxidized by thermal oxidation or the like, since its volume generally expands, the oxide layer 60 is formed so as to cover the trench gate 58.

Next, as shown in FIG. 4B (h), the SiN layer 54a, the N-type source layer 59, and the P-type base layer 53a in a region where the oxide layer 60 is not formed are removed by etching by RIE or the like. . Specifically, silicon oxide (SiO ₂ ) is not etched, but after removing part of the SiN layer 54a under conditions that allow SiN to be etched, silicon oxide (SiO ₂ ) is not etched, but Si can be etched Under certain conditions, part of the N-type source layer 59 and the P-type base layer 53a is removed. Thereby, the region SiN layer 54b where the oxide layer 60 is not formed, the N-type source layer 59a, and the P-type base layer 53b are etched to form the trench 62.

  Thereafter, a source electrode (not shown) is buried in the trench 62 and formed so as to be connected to the N-type source layer 59a and the P-type base layer 53b. Further, by forming a drain electrode (not shown) on the back surface of the semiconductor substrate 51, the MOS structure semiconductor device having a trench gate in the present embodiment is completed.

  In the present embodiment, the oxide layer 60 is used in the step of forming the trench 62 for etching the N-type source layer 59. That is, in a general method, a resist pattern is used in the step of etching the N-type source layer 59. However, in this embodiment, a photolithography step for forming the resist pattern is not necessary, and the manufacturing process is performed. The process can be shortened.

[Fourth Embodiment]
A fourth embodiment of the present invention will be described with reference to FIGS. 5A and 5B.

  First, as shown in FIG. 5A, a trench 76 is formed in an N-type epitaxial layer 72, a P-type base layer 73, and a silicon oxide layer 74 on a single crystal N-type silicon substrate 71 which is a semiconductor substrate. The trench 76 is formed by anisotropic etching after the resist pattern 75 is formed by photolithography.

  Next, as shown in FIG. 5A (b), the silicon oxide layer 74 is isotropically etched in a direction parallel to the film surface. Thereby, a silicon oxide layer 74a etched in the surface direction is formed.

  Next, as shown in FIG. 5A (c), after removing the resist pattern 75, thermal oxidation is performed to obtain the surface of the trench 76, that is, the P-type base layer 73 forming the trench 76, the N-type A trench oxide layer 77 is formed in a region where the surface of the epitaxial layer 72 is exposed.

  Next, as shown in FIG. 5A (d), a trench gate 78 is formed by embedding polysilicon in the trench 76 in which the trench oxide layer 77 is formed. The trench gate 78 is formed so as to be flush with the surface of the silicon oxide layer 74a. The trench gate 78 has high conductivity because P (phosphorus), which is an impurity element for forming the N-type, is contained at a high concentration.

  Next, as shown in FIG. 5B (e), the surface of the silicon oxide layer 74a is etched to form a thin silicon oxide layer 74b. Specifically, a thin silicon oxide layer 74b is formed by etching the surface of the silicon oxide layer 74a by an etching method capable of etching only silicon oxide without etching Si.

  Next, as shown in FIG. 5B (f), an N-type source layer 79 is formed by ion implantation of As (arsenic). At this time, As ions are also implanted into the trench gate 78, but the trench gate 78 contains N-type impurity ions at a high concentration in order to enhance conductivity, so that As is implanted. There is no effect.

  Next, as shown in FIG. 5B (g), the portion exposed on the surface of the trench gate 78 is oxidized by performing thermal oxidation. Thereby, the oxide layer 80 is formed. When silicon is oxidized by thermal oxidation or the like, since its volume generally expands, the oxide layer 80 is formed so as to cover the trench gate 78.

Next, as shown in FIG. 5B (h), the silicon oxide layer 74b, the N-type source layer 79, and the P-type base layer 73 in a region where the oxide layer 80 is not formed are removed by etching using RIE or the like. To do. Specifically, after removing a part of the silicon oxide layer 74b, the silicon oxide (SiO ₂ ) is not etched, but the N-type source layer 79 and a part of the P-type base layer 73 are partially removed depending on the conditions under which Si can be etched. Remove. As a result, the silicon oxide layer 74c where the oxide layer 80 is not formed, the N-type source layer 79a, and the P-type base layer 73a are etched to form the trench 81. Since the oxide film 80 is sufficiently thicker than the silicon oxide film 74b, the oxide film 80 remains even if a part of the silicon oxide film 74b is removed.

  Thereafter, a source electrode (not shown) is buried in the trench 81 and formed so as to be connected to the N-type source layer 79a and the P-type base layer 73a. Further, by forming a drain electrode (not shown) on the back surface of the semiconductor substrate 71, the semiconductor device having the MOS structure having the trench gate in this embodiment is completed.

  In the present embodiment, the oxide layer 80 is used in the step of forming the trench 81 for etching the N-type source layer 79. That is, in a general method, a resist pattern is used in the step of etching the N-type source layer 79, but in this embodiment, a photolithography step for forming the resist pattern is not necessary, and the manufacturing process is performed. The process can be shortened. In the present embodiment, since the silicon oxide layer 74b having a wide diameter can be formed by performing isotropic etching in the film surface direction, the oxide film 80 covering the trench gate 78 in a wide range is formed. Therefore, the distance between the trench gate 78 and the trench 81 can be increased.

  As mentioned above, although the manufacturing method of the semiconductor device in this invention was demonstrated in detail in embodiment, this invention is not limited to the said embodiment, It can take another form.

Manufacturing process diagram of semiconductor device of MOS structure in the first embodiment (1) Semiconductor device manufacturing process diagram of MOS structure in the first embodiment (2) Manufacturing process diagram of a semiconductor device having a MOS structure in the first embodiment (3) Manufacturing process diagram of general MOS structure semiconductor device Semiconductor device manufacturing process diagram of MOS structure in the second embodiment (1) Semiconductor device manufacturing process diagram of MOS structure in the second embodiment (2) Semiconductor device manufacturing process diagram of MOS structure in the third embodiment (1) Semiconductor device manufacturing process diagram of MOS structure in the third embodiment (2) Semiconductor device manufacturing process diagram of MOS structure in the fourth embodiment (1) Semiconductor device manufacturing process diagram of MOS structure in the fourth embodiment (2)

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... N-type silicon substrate, 12, 12a ... N-type epitaxial layer, 13, 13a, 13b ... P-type base layer, 14, 14b, 14c ... SiN layer, 15 ... Photoresist , 16 ... trench, 17 ... trench oxide layer, 18 ... trench gate, 19, 19a ... N-type source layer, 20 ... oxide layer.

Claims (5)

Forming an insulating layer on the semiconductor substrate;
Forming a first trench selectively reaching the semiconductor substrate from the insulating layer in the semiconductor substrate on which the insulating layer is formed;
Forming an insulating film on the surface of the first trench, and forming a trench gate by embedding polysilicon through the insulating film to the surface where the insulating layer is formed in the first trench; When,
Thinning the insulating layer by etching the insulating layer to expose the polysilicon from the surface of the insulating layer;
Oxidizing the polysilicon exposed from the surface of the insulating layer to form an oxide layer;
Forming a second trench reaching the semiconductor substrate from the surface of the insulating layer using the oxide layer as a mask. Forming an insulating layer on the semiconductor substrate;
Forming a first trench selectively reaching the semiconductor substrate from the insulating layer in the semiconductor substrate on which the insulating layer is formed;
Etching the insulating layer in a direction along the surface of the semiconductor substrate to widen the diameter of the first trench;
Forming an insulating film on a surface of the first trench, and forming a trench gate by embedding polysilicon through the insulating film to a surface where the insulating layer is formed in the first trench; ,
Thinning the insulating layer by etching the insulating layer to expose the polysilicon from the surface of the insulating layer;
Oxidizing the polysilicon exposed from the surface of the insulating layer to form an oxide layer;
Forming a second trench reaching the semiconductor substrate from the surface of the insulating layer using the oxide layer as a mask.   The method for manufacturing a semiconductor device according to claim 1, wherein the insulating layer is made of silicon nitride. Forming a silicon nitride film and a silicon oxide layer on the semiconductor substrate sequentially from the bottom;
Selectively forming a first trench reaching the semiconductor substrate from the silicon nitride film and the silicon oxide film in the semiconductor substrate on which the silicon nitride film and the silicon oxide film are formed;
An insulating film is formed on the surface of the first trench, and a trench gate is formed by burying polysilicon through the insulating film to the surface where the silicon oxide layer is formed in the first trench. Process,
Thinning the silicon oxide layer by etching the silicon oxide layer to expose the polysilicon from the surface of the silicon oxide film;
Oxidizing the polysilicon exposed from the surface of the silicon oxide film to form an oxide layer;
Etching the surface of the semiconductor substrate using the oxide layer as a mask;
A method for manufacturing a semiconductor device, comprising:   The semiconductor substrate is a semiconductor substrate in which a first conductivity type epitaxial layer, a second conductivity type base layer, and a first conductivity type source layer are sequentially formed on a first conductivity type silicon substrate. Item 5. A method for manufacturing a semiconductor device according to any one of Items 1 to 4.

Images