JP5354160B2 - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method using a self-aligned silicide process, whereby a semiconductor device having a poly-resistor can be obtained by a simple process. <P>SOLUTION: The manufacturing method of the semiconductor device includes a process to form an element separating layer 20 on a semiconductor substrate 10, a process to form a resistance layer 110 in the upper part of the element separating layer, a process to form a first insulating layer 120 for covering the resistance layer, a process to form a gate oxide film 220 in the upper part of the semiconductor substrate which forms a region divided by the element separating layer, a process to form a gate electrode 210 in the upper part of the gate oxide film, a process to form a side wall 240 in the side wall of the gate electrode, a process to form source and drain regions by injecting dopants into the a region where the semiconductor substrate is exposed, a process to expose the resistance layer by patterning the first insulating layer, and a process to form a silicide layer 30 in the region where the resistance layer is exposed on the gate electrode, and on the source and drain regions. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In a semiconductor device, generally, a technique in which a transistor element, a resistance element, and the like are mounted on the same silicon substrate is known. In such a semiconductor device, a MOS (Metal Oxide Semiconductor) transistor can be used as a transistor element, and a poly resistor made of polycrystalline silicon can be used as a resistance element.

  In such a semiconductor device, a silicide layer is formed on the gate electrode, the source / drain region, and the contact region of the poly resistor in order to reduce the resistance of the MOS transistor and the contact resistance. As a technique for forming a silicide layer in these regions, a self-aligned silicide process is known. According to this technique, a silicide layer can be formed in a predetermined region without passing through a photolithography process by utilizing the property that only a metal in contact with silicon reacts to form a silicide.

Here, in the manufacturing process of a semiconductor device, the poly resistor is generally covered with silicon nitride mainly for preventing out diffusion in the gate oxide film forming process. Therefore, in order to silicidize the poly-resistive contact region, a photolithography process for removing the silicon nitride and exposing the silicon is added. As described above, when a semiconductor device having a poly resistance is manufactured by using a self-aligned silicide process, there is a problem that the number of steps increases and the process becomes complicated.
Japanese Patent Laid-Open No. 11-135777

  One of the objects of the present invention is to provide a manufacturing method capable of obtaining a semiconductor device having a poly resistance using a self-aligned silicide process in a simple process.

A method for manufacturing a semiconductor device according to the present invention includes:
Forming an element isolation layer on a semiconductor substrate;
Forming a resistance layer above the element isolation layer;
Forming a first insulating layer covering the resistive layer;
Forming a second insulating layer covering the first insulating layer;
Forming a gate oxide film in a region above the semiconductor substrate and partitioned by the element isolation layer;
Forming a gate electrode above the gate oxide film;
Forming a third insulating layer on the entire upper surface of the semiconductor substrate;
Etching the third insulating layer and the second insulating layer to form a sidewall on the side wall of the gate electrode, and removing the second insulating layer;
Implanting impurities into exposed regions of the semiconductor substrate to form source and drain regions;
Exposing the resistive layer by patterning the first insulating layer;
Forming a silicide layer on the exposed region of the resistance layer, on the gate electrode, and on the source and drain regions.

  In the method for manufacturing a semiconductor device according to the present invention, the second insulating layer can be removed in the step of etching the third insulating layer and forming the sidewall. This eliminates the step of removing the second insulating layer in the step of exposing the resistance layer in the contact region. Therefore, it is possible to obtain a semiconductor device having a polyresistance using a self-aligned silicide process in a simple process.

  In the description of the present invention, the word “upper” is referred to as, for example, another specific member (hereinafter referred to as “B member”) formed “above” a “specific member (hereinafter referred to as“ A member ”). ) "Etc. In the description according to the present invention, in this case, the B member is formed directly on the A member, and the B member is formed on the A member via another member. The word “above” is used as a case where the case is included.

In the method for manufacturing a semiconductor device according to the present invention,
The second insulating layer may be patterned in a process in which the sidewall is formed by etching the third insulating layer.

In the method for manufacturing a semiconductor device according to the present invention,
The second insulating layer may be formed to have the same film thickness as the third insulating layer is removed in the step of forming the sidewall by etching the third insulating layer. .

In the method for manufacturing a semiconductor device according to the present invention,
The step of etching the third insulating layer and the second insulating layer includes forming the sidewalls and removing the second insulating layer so that the third insulating layer and the second insulating layer are removed. The etching can be performed under etching conditions that provide a selectivity.

In the method for manufacturing a semiconductor device according to the present invention,
The second insulating layer may be made of silicon nitride.

In the method for manufacturing a semiconductor device according to the present invention,
The third insulating layer may be made of silicon oxide.

In the method for manufacturing a semiconductor device according to the present invention,
The resistance layer may be made of polycrystalline silicon.

In the method for manufacturing a semiconductor device according to the present invention,
The step of etching the third insulating layer and the second insulating layer may be performed by dry etching.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

1. Semiconductor Device FIG. 1 is a cross-sectional view schematically showing a semiconductor device 1000 according to this embodiment. As shown in FIG. 1, the semiconductor device 1000 includes a semiconductor substrate 10, an element isolation layer 20, a poly resistor 100, and a transistor 200.

  The semiconductor substrate 10 is made of a first conductivity type (for example, P type) silicon substrate.

  The element isolation layer 20 is formed on the semiconductor substrate 10. The element isolation layer 20 includes, for example, a LOCOS (Local Oxidation of Silicon) layer, a semi-recessed LOCOS layer, and a trench insulating layer. In the illustrated example, the element isolation layer 20 is a LOCOS layer. The element isolation layer 20 can partition the transistor 200.

  The poly resistor 100 is formed on the element isolation layer 20. The poly resistor 100 includes a resistance layer 110, a first insulating layer 120, and a silicide layer 30.

  The resistance layer 110 is formed on the element isolation layer 20. The resistance layer 110 is made of, for example, polycrystalline silicon into which impurities are implanted.

  The first insulating layer 120 is formed on the resistance layer 110. The first insulating layer 120 is made of, for example, silicon oxide. The first insulating layer 120 can serve as a mask when forming the silicide layer 30 in the contact region 140. The first insulating layer 120 can be used as a dielectric film of a capacitor (not shown).

  The silicide layer 30 is formed in the contact region 140 on the resistance layer 110. The silicide layer 30 can form an ohmic contact with the bottom of a contact (not shown) to reduce contact resistance. The silicide layer 30 is made of a compound of silicon and metal. More specifically, the silicide layer 30 is made of, for example, tungsten silicide, molybdenum silicide, titanium silicide, cobalt silicide, nickel silicide, or the like.

  The transistor 200 is formed on the semiconductor substrate 10 in a region partitioned by the element isolation layer 20. The transistor 200 is a MOS (Metal Oxide Semiconductor) transistor. Transistor 200 includes gate electrode 210, gate oxide film 220, source and drain regions 230 a and 230 b, sidewalls 240, and silicide layer 30.

  Gate electrode 210 is formed on gate oxide film 220. The gate electrode 210 is made of, for example, polycrystalline silicon.

  The gate oxide film 220 is formed on the semiconductor substrate 10. The gate oxide film 220 is made of, for example, silicon oxide.

  Source and drain regions 230 a and 230 b are formed in the semiconductor substrate 10. The source and drain regions 230a and 230b are made of a second conductivity type (for example, N-type) impurity region.

  The side wall 240 is formed on the side wall of the gate electrode 210. The sidewall 240 is made of, for example, HTO (High Temperature Oxide).

  Silicide layer 30 is formed on gate electrode 210 and on source and drain regions 230a and 230b. The silicide layer 30 can reduce the resistance of the gate electrode 210 and the source and drain regions 230a and 230b. The silicide layer 30 is formed in the same process as the silicide layer 30 of the poly resistor 100 described above, and can be made of the same material.

2. Next, a method for manufacturing a semiconductor device according to this embodiment will be described with reference to the drawings. 2-8 is sectional drawing which shows typically the manufacturing process of the semiconductor device 1000 concerning this embodiment.

  As shown in FIG. 2, the element isolation layer 20 is formed on the semiconductor substrate 10. The element isolation layer 20 is formed by, for example, the LOCOS method. Specifically, for example, a silicon nitride film (not shown) is formed on the semiconductor substrate 10, and the silicon nitride film is patterned into a predetermined shape and then thermally oxidized.

  Next, the resistance layer 110 is formed. Impurities are implanted into the resistance layer 110 by ion implantation. The resistance of the resistance layer 110 can be adjusted by the amount and type of impurities.

  As shown in FIG. 3, the resistance layer 110 is patterned into a predetermined shape. The patterning is performed by, for example, a photolithography technique. Next, heat treatment of the resistance layer 110 is performed. Thereby, the crystallinity of the resistance layer 110 can be restored and impurities can be activated.

  As shown in FIG. 4, a first insulating layer 120 covering the resistance layer 110 is formed. The first insulating layer 120 is formed by, for example, a thermal oxidation method.

  As shown in FIG. 5, a second insulating layer 130 that covers the first insulating layer 120 is formed. The second insulating layer 130 is formed by, for example, a CVD method and patterned by a photolithography technique. The second insulating layer 130 can suppress out-diffusion of impurities in the resistance layer 110 in a step of forming a gate oxide film 220 described later. The second insulating layer 130 is preferably made of, for example, silicon nitride so as not to be affected in the pre-oxide film (not shown) removing step before the gate oxide film 220 is formed. The second insulating layer 130 may be formed to have the same thickness as that from which the third insulating layer 240d is removed in the step of forming the sidewalls 240 by etching the third insulating layer 240d. . The film thickness of the second insulating layer 130 is, for example, 150 to 200 nm.

  As shown in FIG. 6, a gate oxide film 220 and a gate electrode 210 are formed. The gate oxide film 220 is formed by, for example, a thermal oxidation method after removing a pre-oxide film (not shown). The temperature of thermal oxidation is about 900 ° C., for example. The gate electrode 210 is formed by, for example, forming a film by a CVD method and patterning by a photolithography technique.

Next, sidewalls 240 are formed on the sidewalls of the gate electrode 210. First, the third insulating layer 240d is formed on the entire upper surface of the semiconductor substrate 10. That is, the third insulating layer 240 d is formed so as to cover the element isolation layer 20, the second insulating layer 130, the semiconductor substrate 10, and the gate electrode 210. The third insulating layer 240d is made of, for example, HTO (High Temperature Oxide). Next, the sidewalls 240 are formed by etching back the third insulating layer 240d by dry etching. Dry etching is performed using, for example, a mixed gas of CHF ₃ , O ₂ , and He.

  Here, the second insulating layer 130 is patterned in the step of forming the sidewalls 240 by etching the third insulating layer 240d. The second insulating layer 130 may be formed to have the same thickness as that from which the third insulating layer 240d is removed. Therefore, as shown in FIG. 7, the second insulating layer 130 is removed in the step of etching the third insulating layer 240d. Accordingly, a photolithography process for removing the second insulating layer 130 can be omitted. In addition, the second insulating layer 130 is formed under an etching condition that provides a selection ratio between the third insulating layer 240d and the second insulating layer 130 so that the sidewall 240 is formed and the second insulating layer 130 is removed. It may be removed by etching. Although not shown, the second insulating layer 130 and the third insulating layer 240d may remain on the sidewall of the resistance layer 110.

  As shown in FIG. 8, source and drain regions 230 a and 230 b are formed in the exposed region of the semiconductor substrate 10. Specifically, for example, N-type impurities are implanted to form the source and drain regions 230a and 230b. Impurity can be implanted using the gate electrode 210 and the sidewall 240 as a mask.

  Next, the first insulating layer 120 in the contact region 140 is removed. Thereby, the resistance layer 110 in the contact region 140 can be exposed. As described above, since the second insulating layer 130 is removed, the first insulating layer 120 in the contact region 140 can be easily removed by using a photolithography technique.

  As shown in FIG. 1, the silicide layer 30 is formed on the gate electrode 210, the source and drain regions 230 a and 230 b, and the contact region 140 of the resistance layer 110. The silicide layer 30 is formed by a self-aligned silicide process. Specifically, the silicide layer 30 is formed by forming a metal layer (not shown) on the entire surface and then performing heat treatment. The self-aligned silicide process refers to a technique of selectively forming a metal silicide layer on a portion where silicon is exposed, utilizing the property that only a metal in contact with silicon reacts to form a silicide. Next, the metal that has not been silicided is removed by etch back.

  Through the above steps, the semiconductor device 1000 can be manufactured.

  The manufacturing method of the semiconductor device 1000 has the following features, for example.

  In the method for manufacturing the semiconductor device 1000, a self-aligned silicide process can be used. Thereby, the silicide layer 30 can be formed in a predetermined region in a self-aligning manner.

  In the method for manufacturing the semiconductor device 1000, the second insulating layer 130 can be removed in the step of etching the third insulating layer 240d to form the sidewalls 240. Accordingly, the step of removing the second insulating layer 130 in the step of exposing the resistance layer 110 in the contact region 140 can be omitted. Therefore, the semiconductor device 1000 having the poly resistor 100 using the self-aligned silicide process can be obtained by a simple process.

  Although the embodiments of the present invention have been described in detail as described above, those skilled in the art will readily understand that many modifications are possible without substantially departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention.

FIG. 3 is a cross-sectional view schematically showing the semiconductor device according to the embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on this embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on this embodiment.

Explanation of symbols

10 semiconductor substrate, 20 element isolation layer, 30 silicide layer, 100 poly resistance, 110 resistance layer, 120 first insulating layer, 130 second insulating layer, 140 contact region, 200 transistor, 210 gate electrode, 220 gate oxide film, 230a 230b, source and drain regions, 240 sidewalls, 240d third insulating layer, 1000 semiconductor device

Claims (4)

Forming an element isolation layer on a semiconductor substrate;
Forming a resistance layer above the element isolation layer;
Forming a first insulating layer covering the resistive layer;
Forming a second insulating layer made of silicon nitride covering the first insulating layer;
Forming a gate oxide film in a region above the semiconductor substrate and partitioned by the element isolation layer;
Forming a gate electrode above the gate oxide film;
Forming a third insulating layer made of silicon oxide on the entire upper surface of the semiconductor substrate;
Etching the third insulating layer and the second insulating layer to form a sidewall on the side wall of the gate electrode, and removing the second insulating layer;
Implanting impurities into exposed regions of the semiconductor substrate to form source and drain regions;
Exposing the resistive layer by patterning the first insulating layer;
And exposed regions of said resistive layer, and the upper of the gate electrode, viewed including the upper of the source and drain regions, and forming a silicide layer on the,
Etching the third insulating layer and the second insulating layer to form a sidewall on a sidewall of the gate electrode, and removing the second insulating layer, the sidewall is formed; and A method of manufacturing a semiconductor device, which is performed under an etching condition that provides a selection ratio between the third insulating layer and the second insulating layer such that the second insulating layer is removed . In claim 1,
The method for manufacturing a semiconductor device, wherein the second insulating layer is patterned in a step of etching the third insulating layer to form the sidewall. In claim 1 or 2 ,
The method for manufacturing a semiconductor device, wherein the resistance layer is made of polycrystalline silicon. In any one of Claims 1 thru | or 3 ,
The method of manufacturing a semiconductor device, wherein the step of etching the third insulating layer and the second insulating layer is performed by dry etching.

Images