JP5162935B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

Conventionally, in a method of manufacturing a semiconductor device having a polysilicon resistance element made of a polysilicon film, impurity implantation into a gate electrode, a polysilicon resistance element, or the like is performed using phosphorus ions (P ⁺ ). Then, heat treatment is performed on the gate electrode, the polysilicon resistance element, etc. in order to activate the impurities implanted into the gate electrode, the polysilicon resistance element, etc. Hereinafter, the heat treatment for activating the impurities is referred to as impurity activation heat treatment. Further, silicide is formed on the gate electrode, the polysilicon resistance element, or the like that has been subjected to impurity activation heat treatment by using a silicide formation technique.
JP 2006-40947 A JP 2006-80218 A

  However, when heat treatment for activating the impurities is performed, phosphorous ions are diffused outward (out-diffusion), and the impurity concentration of the polysilicon resistance element fluctuates. Further, the impurity implantation into the polysilicon resistance element (particularly the electrode lead-out region) is only performed at the time of polysilicon film formation, and the impurity concentration of the polysilicon resistance element fluctuates. Here, the electrode lead-out region is a predetermined region provided in the polysilicon resistance element, and is a region for electrically connecting the lead-out electrode and the polysilicon resistance element. When silicide is formed in the electrode extraction region by the silicide formation technique, the variation in the impurity concentration at the contact interface between the silicide formed in the electrode extraction region and polysilicon increases. As a result, there has been a problem that variations in the contact resistance value generated at the contact interface between the silicide and the polysilicon in the electrode lead-out region become large and the device characteristics become unstable. An object of the present invention is to suppress a variation in impurity concentration in a polysilicon resistance element.

The present invention employs the following means in order to solve the above problems. That is, the method for manufacturing a semiconductor device of the present invention includes:
Forming a polysilicon film on the substrate;
A first implantation step of implanting impurities into the polysilicon film before forming a predetermined pattern in the polysilicon film;
Forming a first diffusion barrier film on the polysilicon film;
And a step of performing a heat treatment for activating the impurities implanted into the polysilicon film.

  According to the method of manufacturing a semiconductor device of the present invention, impurities are implanted into the polysilicon film before the predetermined pattern is formed, and the first diffusion prevention film is formed on the polysilicon film. Since the first diffusion preventing film is formed on the polysilicon film, outward diffusion of impurities in the polysilicon film caused by heat treatment is suppressed. Therefore, it is possible to suppress the outward diffusion of impurities in the polysilicon film caused by the heat treatment before the predetermined pattern is formed in the polysilicon film. As a result, it is possible to suppress fluctuations in the impurity concentration in the polysilicon film.

The method for manufacturing a semiconductor device according to the present invention further includes a step of forming a gate electrode and a resistance element by removing the first diffusion prevention film and forming a predetermined pattern on the polysilicon film. Also good. According to the method for manufacturing a semiconductor device of the present invention, it is possible to produce a gate electrode and a resistance element in which variation in impurity concentration in the polysilicon film is suppressed by forming a predetermined pattern in the polysilicon film. Become.

In addition, a method for manufacturing a semiconductor device of the present invention includes:
The substrate includes source / drain regions;
A second implantation step of implanting the impurity into the source / drain regions and the resistance element;
Forming a second diffusion barrier film on the surface of the source / drain region and the surface of the resistance element;
And a step of performing a heat treatment for activating the impurities implanted into the source / drain regions and the resistance element.

  According to the method for manufacturing a semiconductor device of the present invention, an impurity is implanted into a resistance element, and a second diffusion prevention film is formed on the surface of the resistance element. Since the resistance element is formed with the second diffusion prevention film, it is possible to suppress outward diffusion of impurities in the resistance element caused by heat treatment. As a result, it is possible to suppress fluctuations in the impurity concentration in the resistance element.

In addition, a method for manufacturing a semiconductor device of the present invention includes:
The second injection step includes
Covering the surface of the gate electrode, the surface of the source / drain region and the surface of the resistance element with an oxide film;
Forming a resist pattern having an opening at a predetermined position on the oxide film covering the resistance element;
Removing the oxide film below the predetermined position using the resist pattern as a mask to form an electrode lead portion in the resistance element and removing the oxide film covering the surface of the source / drain region;
A step of injecting the impurity into the source / drain region and the electrode lead portion.

  According to the method for manufacturing a semiconductor device of the present invention, impurities are implanted into the electrode lead portion of the resistance element, and the second diffusion prevention film is formed on the surface of the resistance element. Since the electrode lead-out portion of the resistance element is formed with the second diffusion prevention film, it is possible to suppress the outward diffusion of impurities around the electrode lead-out portion caused by the heat treatment. As a result, it is possible to suppress fluctuations in the impurity concentration around the electrode lead portion.

In addition, a method for manufacturing a semiconductor device of the present invention includes:
The second injection step includes
Covering the surface of the gate electrode, the surface of the source / drain region and the surface of the resistance element with an oxide film;
Forming a resist pattern having an opening at a predetermined position on the oxide film covering the resistance element;
By removing the oxide film below the predetermined position using the resist pattern as a mask, an electrode lead portion is formed in the resistance element, a side wall is formed on a side surface of the resistance element, and an upper surface of the gate electrode is covered. Removing the oxide film, forming a sidewall on the side surface of the gate electrode, and removing the oxide film covering the surface of the source / drain region;
A step of injecting the impurity into the source / drain region and the electrode lead portion.

  In the method of manufacturing a semiconductor device according to the present invention, the second implantation step may inject the impurity into the resistance element simultaneously with the implantation of the impurity into the source / drain region. According to the method for manufacturing a semiconductor device of the present invention, impurities are implanted into the resistance elements at the same time as the impurities are implanted into the source / drain regions. Therefore, it is not necessary to separately implant the impurity into the source / drain region and to implant the impurity into the resistance element, and the process can be simplified.

In addition, a method for manufacturing a semiconductor device of the present invention includes:
Removing the second diffusion barrier film and forming a metal film on the gate electrode, the source / drain region, and the resistance element;
The method may further comprise a step of forming silicide on the gate electrode, the source / drain region, and the resistance element by heat-treating the substrate.

  According to the semiconductor device manufacturing method of the present invention, silicide is formed in the gate electrode, the source / drain region, and the resistance element by heat-treating the substrate. Since the fluctuation of the impurity concentration in the resistance element is suppressed, it is possible to stabilize the resistance at the contact interface between the silicide formed in the resistance element and the polysilicon in the resistance element.

  In the method for manufacturing a semiconductor device of the present invention, the impurity may be arsenic ions. Furthermore, in the method for manufacturing a semiconductor device of the present invention, the metal may be cobalt.

  According to the present invention, it is possible to suppress the fluctuation of the impurity concentration in the polysilicon resistance element.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The configuration of the following embodiment is an exemplification, and the present invention is not limited to the configuration of the embodiment.

  With reference to FIGS. 1 to 11, the semiconductor device and the manufacturing method thereof according to the present embodiment will be described. Each of FIGS. 1 to 11 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the present embodiment.

First, as shown in FIG. 1, an element isolation film 2 is formed on a silicon substrate 1. For example, the element isolation film 2 is formed by a LOCOS (Local Oxidation of Silicon) method or a trench isolation method. Next, ion implantation (impurity implantation) is performed on the silicon substrate 1, and an N-type transistor region (N-type source / drain region) 3 and a P-type transistor region (P-type source / drain region) 4 are formed on the silicon substrate 1. Form. In the present embodiment, an N-type transistor region 3 is formed by implanting boron ions (B ⁺ ) into the silicon substrate 1, and a P-type transistor region 4 is formed by implanting phosphorus ions (P ⁺ ) into the silicon substrate 1. To do.

  Then, a gate oxide film 5 is formed on the N-type transistor region 3 and the P-type transistor region 4 of the silicon substrate 1. For example, the gate oxide film 5 is grown on the N-type transistor region 3 and the P-type transistor region 4 of the silicon substrate 1 by using a thermal oxidation method.

Next, a polysilicon film 6 is formed on the element isolation film 2 and the gate oxide film 5. For example, using CVD (Chemical Vapor Deposition) method, silane gas is thermally decomposed in nitrogen,
A polysilicon film 6 is grown.

Then, as shown in FIG. 2, a resist (resist pattern) 7 is formed on the polysilicon film 6, and ion implantation is performed on the polysilicon film 6. In this case, the resist 7 is formed in the vertical direction of the P-type transistor region 4. That is, a resist 7 for preventing ion implantation into the polysilicon film 6 formed in the vertical direction of the P-type transistor region 4 is formed. In this embodiment, arsenic ions (As ⁺ ) that are N-type impurities are used as ions to be implanted into the polysilicon film 6.

Next, as shown in FIG. 3, on the polysilicon film 6, a silicon oxide film (SiO ₂ ) 8 (first
Equivalent to a diffusion barrier film). In this case, the silicon oxide film 8 is formed by low-temperature film formation using a CVD method or the like. Then, impurity activation heat treatment is performed on the polysilicon film 6. Specifically, impurity activation heat treatment is performed by heating the silicon substrate 1.

  Next, as shown in FIG. 4, the gate electrode 9A, the gate electrode 9B, and the polysilicon resistance element 10 are formed. Specifically, the silicon oxide film 8 is removed with hydrogen fluoride (solution). Then, patterning is performed on the polysilicon film 6 by photolithography and dry etching to form gate electrodes 9A, 9B, and polysilicon resistance elements 10 having desired shapes. The gate electrode 9A is formed on the gate oxide film 5 formed on the N-type transistor region 3. The gate electrode 9B is formed on the gate oxide film 5 formed on the P-type transistor region 4. The polysilicon resistance element 10 is formed on the element isolation film 2. In this case, as shown in FIG. 4, the polysilicon resistance element 10 is formed on the element isolation film 2 different from the element isolation film 2 for isolating the N-type transistor area 3 and the P-type transistor area 4.

  Then, as shown in FIG. 5, an N-type LDD (lightly doped drain) region 20 is formed in the N-type transistor region 3, and a P-type LDD (lightly doped drain) region 21 is formed in the P-type transistor region 4. Specifically, by photolithography, other than the N-type transistor region 3 is covered with a resist (not shown), and low-concentration phosphorus ions are implanted into the N-type transistor region 3. In this case, by implanting phosphorus ions into the shallow portion of the N-type transistor region 3, the N-type LDD region 20 is formed in the shallow portion of the N-type transistor region 3. At this time, since the gate electrode 9A serves as a mask for ion implantation, the N-type LDD region 20 is formed in a self-aligned manner with the gate electrode 9A.

  Further, by photolithography, other than the P-type transistor region 4 is covered with a resist (not shown), and low-concentration boron ions are implanted into the P-type transistor region 4. In this case, boron ions are implanted into a shallow portion of the P-type transistor region 4, thereby forming a P-type LDD region 21 in the shallow portion of the P-type transistor region 4. At this time, since the gate electrode 9B serves as a mask for ion implantation, the P-type LDD region 21 is formed in a self-aligned manner with the gate electrode 9B.

  Next, a sidewall oxide film (not shown) is formed by CVD so as to cover the entire surface of the silicon substrate 1 including the gate electrode 9A, the gate electrode 9B, and the polysilicon resistance element 10. Then, as shown in FIG. 6, in order to form the resistance element oxide film 31 on the polysilicon resistance element 10, a resist (resist pattern) is formed on the sidewall oxide film formed on the polysilicon resistance element 10. 22 is formed and anisotropic etching is performed. When anisotropic etching is performed, sidewalls 30 are formed on the side surface of the gate electrode 9A, the side surface of the gate electrode 9B, and the side surface of the polysilicon resistance element 10.

At this time, the resistor element oxide film 31 and the electrode lead-out forming portion 32 are formed on the polysilicon resistor element 10 using the resist 22 as a mask. That is, as shown in FIG. 6, a part of the resistance element oxide film 31 is removed, and the electrode lead-out forming portion 32 is opened. The electrode lead forming portion 32 is a portion to which the lead electrode is connected in the upper surface portion of the polysilicon resistance element 10. Therefore, the resistance element oxide film 31 is not formed on the electrode lead forming portion 32. The electrode lead forming portion 32 is formed at an arbitrary position on the upper surface of the polysilicon resistance element 10.

  Then, as shown in FIG. 7, a resist (resist pattern) 40 for ion implantation is formed in the N-type transistor region 3 and the polysilicon resistance element 10 by photolithography. That is, the resist 40 covers the areas other than the N-type transistor region 3 and the polysilicon resistance element 10. Next, high-concentration arsenic ions are implanted into the N-type transistor region 3 and the polysilicon resistance element 10. Arsenic ions are not implanted into the P-type transistor region 4 due to the resist 40 formed in the vertical direction of the P-type transistor region 4.

  By implanting high-concentration arsenic ions into a deep portion of the N-type transistor region 3, an N-type high-concentration region 41 is formed up to a deep portion of the N-type transistor region 3. At this time, since the sidewall 30 formed on the side surface of the gate electrode 9A serves as a mask for ion implantation, the N-type high concentration region 41 is self-aligned with the sidewall 30 formed on the side surface of the gate electrode 9A. It is formed.

  Further, arsenic ions are not implanted into the polysilicon resistor element 10 except from the electrode lead-out forming portion 32 by the resistor element oxide film 31 formed on the polysilicon resistor element 10. In the semiconductor device and the manufacturing method thereof according to the present embodiment, the arsenic ion implantation energy is controlled so that the arsenic ions stop inside the resistance element oxide film 31 formed on the polysilicon resistance element 10. Therefore, arsenic ions are not implanted into the polysilicon resistance element 10 immediately below the resistance element oxide film 31.

  On the other hand, the resistive element oxide film 31 is not formed on the electrode lead forming portion 32. Therefore, arsenic ions are implanted into the polysilicon resistance element 10 from the electrode lead forming portion 32. As a result, an N-type impurity region 42 is formed immediately below and around the electrode lead forming portion 32. At this time, since the resistor element oxide film 31 formed on the polysilicon resistor element 10 serves as a mask for ion implantation, the N-type impurity region 42 is formed in the resistor element oxide film 31 formed on the polysilicon resistor element 10. And self-aligned.

  Next, as shown in FIG. 8, a resist (resist pattern) 50 for performing ion implantation into the P-type transistor region 4 is formed by photolithography. That is, the resist 50 is covered except for the P-type transistor region 4. Next, high-concentration boron ions are implanted into the P-type transistor region 4. Boron ions are not implanted into the N-type transistor region 3 by the resist 50 formed in the vertical direction of the N-type transistor region 3. Boron ions are not implanted into the polysilicon resistance element 10 by the resist 50 formed in the vertical direction of the polysilicon resistance element 10.

  Then, by implanting high-concentration boron ions into a deep portion of the P-type transistor region 4, a P-type high concentration region 51 is formed up to a deep portion of the P-type transistor region 4. At this time, since the sidewall 30 formed on the side surface of the gate electrode 9B serves as a mask for ion implantation, the P-type high concentration region 51 is self-aligned with the sidewall 30 formed on the side surface of the gate electrode 9B. It is formed.

Next, as shown in FIG. 9, a silicon oxide film 60 is formed on the entire surface of the silicon substrate 1 including the N-type transistor region 3, the P-type transistor region 4, and the polysilicon resistance element 10. In this case, the silicon oxide film 60 is formed by low-temperature film formation by a CVD method or the like. Then, impurity activation heat treatment is performed on the N-type transistor region 3, the P-type transistor region 4, and the polysilicon resistance element 10. Specifically, by heating the silicon substrate 1, the N-type LDD region 20, the N-type high concentration region 41, the P-type LDD region 21, the P-type high concentration region 51, the gate electrode 9A, the gate electrode 9B, and the N-type Impurity activation heat treatment is performed on the impurity region 42.

  Next, the silicon oxide film 60 and the gate oxide film 5 are removed with hydrogen fluoride (solution). In this case, the sidewall 30 and the resistance element oxide film 31 are prevented from being removed by hydrogen fluoride by adjusting the concentration of hydrogen fluoride.

  Then, as shown in FIG. 10, silicide 70 is formed in the N-type high concentration region 41, the gate electrode 9A, the P-type high concentration region 51, the gate electrode 9B, and the N-type impurity region 42. Specifically, cobalt is deposited on the N-type high concentration region 41, the gate electrode 9 A, the P-type high concentration region 51, the gate electrode 9 B, and the N-type impurity region 42, and is applied to the silicon substrate 1. Heat treatment. By performing the heat treatment, cobalt and silicon are combined to form silicide 70.

  Next, an element interlayer insulating film 80 is formed on the silicon substrate 1 by a CVD method. Then, after forming a contact hole in the element interlayer insulating film 80 by photolithography and etching, an extraction electrode 81 is formed. FIG. 11 shows a cross-sectional view of the semiconductor device after the extraction electrode 81 is formed.

  In the semiconductor device and the manufacturing method thereof according to the present embodiment, an example in which the N-type transistor region 3 and the P-type transistor region 4 are formed on the silicon substrate 1 has been described, but the present invention is not limited to this. That is, only the N-type transistor region 3 may be formed on the silicon substrate 1 or only the P-type transistor region 4 may be formed on the silicon substrate 1.

  In the semiconductor device and the manufacturing method thereof according to this embodiment, as described with reference to FIG. 2, the impurity implanted into the polysilicon film 6 is arsenic ions. As described with reference to FIG. 3, after the silicon oxide film 8 is formed on the polysilicon film 6, impurity activation heat treatment is performed on the polysilicon film 6. By performing such a process, the amount of impurities released from the polysilicon film 6 is reduced as compared with the case where the impurity activation heat treatment is performed on the polysilicon film 6 into which phosphorus ions are implanted as impurities. can do. That is, outward diffusion of impurities implanted into the polysilicon film 6 can be suppressed.

  Here, a silicon oxide film 8 is formed on the polysilicon film 6 implanted with arsenic ions as impurities, and an impurity activation heat treatment is performed on the polysilicon film 6, and a polysilicon film implanted with phosphorus ions as impurities. The difference from the case where the impurity activation heat treatment is performed on 6 will be described.

  FIG. 12A is an explanatory diagram when impurity activation heat treatment is performed on the polysilicon film 6 in which phosphorus ions are implanted as impurities. When phosphorus ions are implanted into the polysilicon film 6 and impurity activation heat treatment is performed, the out-diffusion of phosphorus ions in the polysilicon film 6 occurs, so that the impurity concentration in the polysilicon film 6 varies.

FIG. 12B is an explanatory diagram when the silicon oxide film 8 is formed on the polysilicon film 6 into which arsenic ions are implanted as impurities, and the impurity activating heat treatment is performed on the polysilicon film 6. When arsenic ions are implanted into the polysilicon film 6 and impurity activation heat treatment is performed, outward diffusion can be suppressed. Since arsenic ions have a larger mass than phosphorous ions, the amount of arsenic ions released out of the polysilicon film 6 is reduced, and outward diffusion is suppressed. Further, when the silicon oxide film 8 is formed on the polysilicon film 6 and the impurity activation heat treatment is performed, the silicon oxide film 8 prevents the phosphorus ions from being released out of the polysilicon film 6. Diffusion is suppressed. Therefore, the fluctuation of the impurity concentration in the polysilicon film 6 is suppressed.

  In the semiconductor device and the manufacturing method thereof according to this embodiment, as described with reference to FIG. 7, the impurity implanted to form the N-type impurity region 42 in the polysilicon resistance element 10 is arsenic ions. As described with reference to FIG. 9, after forming the silicon oxide film 60 on the N-type impurity region 42, the N-type impurity region 42 is subjected to impurity activation heat treatment. By performing such a process, the out-diffusion of the impurity implanted into the polysilicon resistance element 10 is compared with the case where the impurity activation heat treatment is performed on the polysilicon resistance element 10 implanted with phosphorus ions as impurities. Can be suppressed.

  Here, a silicon oxide film 60 is formed on the polysilicon resistor element 10 implanted with arsenic ions as impurities, and an impurity activation heat treatment is performed on the polysilicon resistor element 10, and a polycrystal in which phosphorus ions are implanted as impurities. A difference from the case where the impurity activation heat treatment is performed on the silicon resistance element 10 will be described.

  In the semiconductor device and the manufacturing method thereof according to this embodiment, arsenic ions are implanted into the polysilicon resistance element 10 from the electrode lead-out forming portion 32 as described with reference to FIG. FIG. 13 is a detailed explanatory view of the polysilicon resistance element 10 described with reference to FIG. As shown in FIG. 13, when arsenic ions are implanted into the polysilicon resistance element 10 from the electrode lead forming portion 32, an N-type impurity region 42 is formed immediately below and around the electrode lead forming portion 32.

  FIG. 14 is a detailed explanatory view of the polysilicon resistance element 10 described with reference to FIG. That is, FIG. 14 shows a case where arsenic ions are implanted into the polysilicon resistance element 10 to form a silicon oxide film 60 on the polysilicon resistance element 10 and then an impurity activation heat treatment is performed on the polysilicon resistance element 10. It is explanatory drawing. When arsenic ions are implanted into the polysilicon resistance element 10 and impurity activation heat treatment is performed on the polysilicon resistance element 10, outward diffusion can be suppressed. Since arsenic ions have a mass larger than that of phosphorus ions, the amount of arsenic ions released out of the polysilicon resistance element 10 is reduced, and outward diffusion is suppressed. In addition, when a silicon oxide film 60 is formed on the polysilicon resistor element 10 and impurity activation heat treatment is performed on the polysilicon resistor element 10, phosphorus ions are released from the polysilicon resistor element 10. Since the oxide film 60 prevents, outward diffusion is suppressed. Therefore, the fluctuation of the impurity concentration in the polysilicon resistance element 10 is suppressed.

  In the semiconductor device and the manufacturing method thereof according to the present embodiment, as described with reference to FIG. 10, the polysilicon is formed on the N-type impurity region 42 of the polysilicon resistance element 10 and heat treatment is performed. Silicide 70 is formed in N-type impurity region 42 of resistance element 10. In the semiconductor device and the manufacturing method thereof according to the present embodiment, arsenic ions are implanted into the polysilicon resistor element 10 and the silicon oxide film 60 is formed on the polysilicon resistor element 10. A heat treatment is performed. By such processing, fluctuations in the impurity concentration in the N-type impurity region 42 of the polysilicon resistance element 10 are suppressed. Therefore, when the silicide 70 is formed in the N-type impurity region 42 of the polysilicon resistance element 10, the resistance at the contact interface between the silicide 70 and the polysilicon can be stabilized.

FIG. 15 is a detailed explanatory diagram of the polysilicon resistance element 10 described with reference to FIG. 10, and is an enlarged view of the boundary between the silicide 70 and the polysilicon 90 of the polysilicon resistance element 10. For example, the resistance at the contact interface between the silicide 70 and the polysilicon 90 is substantially the same at the boundary A between the silicide 70 and the polysilicon 90 and at the boundary B between the silicide 70 and the polysilicon 90. This is because the arsenic ion concentration in the polysilicon resistance element 10 does not vary greatly depending on the depth of the polysilicon resistance element 10. FIG. 16 shows the relationship between the depth of the polysilicon resistance element 10 and the arsenic ion concentration in the polysilicon resistance element 10. As shown in FIG. 16, the arsenic ion concentration in the polysilicon resistor element 10 is substantially constant even when the depth of the polysilicon resistor element 10 is different.

  In the semiconductor device and the manufacturing method thereof according to the present embodiment, the resistance at the contact interface between the polysilicon 90 of the polysilicon resistance element 10 and the silicide 70 formed in the polysilicon resistance element 10 can be stabilized. Therefore, it is possible to provide stable device characteristics.

  On the other hand, when phosphorus ions are implanted as impurities into the polysilicon resistance element 10 and an impurity activation heat treatment is performed without forming the silicon oxide film 60 on the polysilicon resistance element 10, Due to the diffusion, the impurity concentration in the polysilicon resistance element 10 varies. FIG. 17 is an explanatory diagram when impurity activation is performed without implanting phosphorus ions as impurities into the polysilicon resistance element 10 and forming the silicon oxide film 60 on the polysilicon resistance element 10. As shown in FIG. 17, since the silicon oxide film 60 is not formed on the polysilicon resistor element 10, the outward diffusion of phosphorus ions in the polysilicon resistor element 10 is not suppressed, and the impurities in the polysilicon resistor element 10 Concentration varies. When the silicide 70 is formed in the polysilicon resistance element 10 with the impurity concentration varied, the resistance at the contact interface between the silicide 70 and the polysilicon 90 varies.

  FIG. 18 is an enlarged view of the boundary between the silicide 70 and the polysilicon 90 of the polysilicon resistance element 10 in which the impurity concentration varies. For example, the resistance at the contact interface between the silicide 70 and the polysilicon 90 is different between the boundary C between the silicide 70 and the polysilicon 90 and the boundary D between the silicide 70 and the polysilicon 90. This is because the phosphorus ion concentration in the polysilicon resistance element 10 varies due to the depth of the polysilicon resistance element 10 in which the impurity concentration varies. FIG. 19 shows the relationship between the depth of the polysilicon resistor element 10 whose impurity concentration has changed and the phosphorus ion concentration in the polysilicon resistor element 10 whose impurity concentration has changed. As shown in FIG. 19, the phosphorus ion concentration in the polysilicon resistor element 10 with the changed impurity concentration varies depending on the depth of the polysilicon resistor element 10 with the changed impurity concentration.

It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on this embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on this embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on this embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on this embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on this embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on this embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on this embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on this embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on this embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on this embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on this embodiment. (A) is explanatory drawing at the time of performing impurity activation heat processing with respect to the polysilicon film 6 which implanted phosphorus ion as an impurity, (b) is silicon oxide on the polysilicon film 6 which implanted arsenic ion as an impurity. FIG. 10 is an explanatory diagram when a film 8 is formed and impurity activation heat treatment is performed on the polysilicon film 6. FIG. 8 is a detailed explanatory diagram of the polysilicon resistance element 10 described with reference to FIG. 7. When arsenic ions are implanted into the polysilicon resistance element 10 and the silicon oxide film 60 is formed on the polysilicon resistance element 10 (polysilicon film 6), an impurity activation heat treatment is performed on the polysilicon resistance element 10. It is explanatory drawing. FIG. 11 is a detailed explanatory diagram of the polysilicon resistance element 10 described with reference to FIG. 10. 4 is a diagram showing the relationship between the depth of an N-type impurity region 42 of the polysilicon resistance element 10 and the arsenic ion concentration in the polysilicon resistance element 10. FIG. 7 is an explanatory diagram when impurity activation heat treatment is performed without implanting phosphorus ions as impurities into the polysilicon resistance element 10 and forming the silicon oxide film 60 on the polysilicon resistance element 10; FIG. 4 is an enlarged view of a boundary between a silicide 70 and polysilicon of the polysilicon resistance element 10 in which the impurity concentration varies. FIG. It is a figure which shows the relationship between the depth of the polysilicon resistance element 10 in which impurity concentration changed, and the phosphorus ion density | concentration in the polysilicon resistance element 10 in which impurity concentration changed.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation film 3 N-type transistor area 4 P-type transistor area 5 Gate oxide film 6 Polysilicon film 7 Resist 8 Oxide films 9A and 9B Gate electrode 10 Polysilicon resistance element 20 N-type LDD area 21 P-type LDD area 22 Resist 30 Side wall 31 Resistance element oxide film 32 Electrode lead formation part 40 Resist 41 N-type high concentration region 42 N-type impurity region 50 Resist 51 P-type high concentration region 60 Silicon oxide film 70 Silicide 80 Element interlayer insulating film 81 Lead electrode

Claims (4)

Forming a polysilicon film on the substrate;
A first implantation step of implanting a first impurity into the polysilicon film;
After the first implantation step, forming a first diffusion barrier film on the polysilicon film;
Performing a first heat treatment for activating the first impurity implanted in the polysilicon film after the step of forming the first diffusion barrier film ;
After the step of performing the first heat treatment, removing the first diffusion barrier film and etching the polysilicon film to form a gate electrode and a resistance element;
Coating the substrate, the gate electrode and the resistance element with an oxide film;
Forming a resist pattern on the oxide film covering the resistance element;
Etching the oxide film using the resist pattern as a mask forms a sidewall on the side wall of the gate electrode, covers a part of the resistance element, and exposes another part of the resistance element. A step of leaving an oxide film;
Using the gate electrode and the sidewall as a mask, a second impurity is implanted into the substrate to form a source / drain region, and the remaining oxide film is used as a mask to the second part of the resistance element. A second implantation step of implanting impurities to form an electrode lead portion;
After the second implantation step, forming a second diffusion barrier film on the gate electrode, the source / drain region, the resistance element, and the remaining oxide film;
After the step of forming the second diffusion barrier film, a second heat treatment for activating the second impurity implanted into the gate electrode, the source / drain region, and the other part of the resistance element. A process of performing
After the step of performing the second heat treatment, forming a lead electrode in contact with the electrode lead portion;
A method for manufacturing a semiconductor device comprising: After the second implantation step, a step of the second diffusion preventing film is removed, forming a metal and on the gate electrode and the source / drain regions on the on the resistive element,
Forming a silicide on the gate electrode, the source / drain region, and the resistance element by heat-treating the substrate after forming the metal ;
The method for manufacturing a semiconductor device according to claim 1 , further comprising: The method for manufacturing a semiconductor device according to claim 2, wherein the metal is cobalt. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the first impurity and the second impurity are arsenic ions. 5.

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