JP2007141889A - Semiconductor device and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a process for fabricating a semiconductor device having a P-channel field effect transistor and an N-channel field effect transistor in which performance of these field effect transistors can be enhanced easily. <P>SOLUTION: A sequential laminate of gate insulating films 11 and 21, polysilicon electrodes 63a and 63b, and gap films 65a and 65b is formed on a semiconductor substrate 10 for every field effect transistor to be formed, and then sidewall spacers 17 and 27 are formed on the opposite side faces of each polysilicon electrode in the linewidth direction directly or through offset spacer films 15 and 25. An interlayer insulating film 73a having an upper surface located on a plane including the upper surface of each cap film is formed and then these cap films are removed to expose the upper surface of each polysilicon electrode. A first metal layer 75a or a second metal layer 79 are then formed thereon and underlying polysilicon electrodes are silicificated entirely by that metal layer to form a gate electrode composed of silicide of different metals. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a P-channel field effect transistor and an N-channel field effect transistor, the gate electrodes of which are made of different metal silicides, and a method for manufacturing the same.

  The integration density of circuit elements in a semiconductor integrated circuit has been steadily increasing, and higher performance and miniaturization of individual circuit elements have been achieved with higher integration. Field effect transistors frequently used in semiconductor integrated circuits are no exception, and their performance and miniaturization are being promoted.

  In obtaining a high-performance and fine field-effect transistor, the gate electrode is usually formed of a material having higher conductivity than polysilicon (impurities doped), for example, metal or metal silicide. However, in order to form a fine metal gate electrode, it is necessary to overcome problems that are difficult to deal with by silicon miniaturization techniques such as selective etching and cleaning of a metal film. On the other hand, the fine metal silicide gate electrode is formed by forming a predetermined metal layer on or around the polysilicon electrode after forming the fine polysilicon electrode. It can be said that it is on the extension of the conventional technique. For this reason, in obtaining a high-performance and fine field-effect transistor, a metal silicide gate electrode is used more frequently than a metal gate electrode.

Field effect transistors used in semiconductor integrated circuits include P-channel field effect transistors and N-channel field effect transistors, and threshold voltages (V _th ) desired for these field effect transistors are different from each other. In order to obtain a high-performance field effect transistor, it is necessary to control the threshold voltage (V _th ) to be within a desired range.

For example, the threshold voltage (V _th ) of a field effect transistor having a polysilicon gate electrode is determined depending on the type and dose of impurities doped into polysilicon as a gate electrode material, heat treatment conditions for activating the impurities, etc. It is controllable by selecting suitably. On the other hand, it is difficult to control the threshold voltage (V _th ) of a field effect transistor having a gate electrode made of metal silicide even if the conductivity of polysilicon as a gate electrode material is controlled. In order to control the voltage (V _th ), the content of the metal element (excluding silicon; the same shall apply hereinafter) in the metal silicide gate electrode and the type of metal element constituting the metal silicide are appropriately selected. Is required.

When the threshold voltage (V _th ) of each of the P-channel field effect transistor and the N-channel field effect transistor is controlled by appropriately selecting the type of metal element constituting the metal silicide, generally, the gate electrode of the P-channel field effect transistor is used. A metal silicide having a high work function is used, and a metal silicide having a low work function is used for the gate electrode of the N-channel field effect transistor. As a method for manufacturing a semiconductor device having a P-channel field effect transistor and an N-channel field effect transistor having gate electrodes formed of different metal silicides, for example, the manufacturing method of the invention described in Patent Document 1 is known. ing.

  In the method of manufacturing a semiconductor device according to the present invention, first, dummy electrodes are formed in the gate electrode formation regions of the P-channel field-effect transistor and the N-channel field-effect transistor in the semiconductor substrate. These dummy electrodes are removed after an interlayer insulating film having an upper surface located on a plane including the upper surface of the dummy electrode is formed. As a result, a recess surrounded by the interlayer insulating film is formed on the semiconductor substrate. Therefore, an electrical insulating film to be a gate insulating film is formed on the surface of the semiconductor substrate exposed at the bottom of the recess. At this time, the electrical insulating film is also formed on the inner wall of the recess. After polysilicon is deposited in each recess to form a polysilicon electrode, a source region and a drain region are formed on the semiconductor substrate, and different types of metal layers are formed on the individual polysilicon electrodes. Thereafter, heat treatment is performed to cause each polysilicon electrode to react with the metal layer thereon, thereby silicidizing the polysilicon electrode to obtain gate electrodes made of different metal silicides.

JP 2004-158593 A

  In the manufacturing method of the invention described in Patent Document 1, since the electric insulating film having the same composition as the gate insulating film is formed on the inner wall of the concave portion together with the gate insulating film when the gate insulating film is formed. In the field effect transistor obtained by the process, the electrical insulating film is positioned on the side surface in the line width direction of the gate electrode, and the following problems occur.

  That is, in recent years, as one method for obtaining a high-performance and fine field-effect transistor, it has been proposed to form a gate insulating film with a high dielectric constant dielectric having a dielectric constant higher than that of silicon oxide. However, if this high dielectric constant dielectric film is also formed on the side surface in the line width direction of the gate electrode, the fringe capacitance between the gate electrode and the source region, and the fringe capacitance between the gate electrode and the drain region. Each tends to be large. When these fringe capacities increase, it becomes difficult to obtain a high-performance field effect transistor having a high operating speed.

  The present invention has been made in view of the above, and has a P-channel field-effect transistor and an N-channel field-effect transistor, and a semiconductor device and a method of manufacturing the same that can easily improve the performance of each of these field-effect transistors The purpose is to obtain.

  A semiconductor device of the present invention that achieves the above object includes a semiconductor substrate, a P-channel field effect transistor having a gate electrode formed on the semiconductor substrate via a gate insulating film, and a gate insulating film on the semiconductor substrate. And an N-channel field effect transistor having a gate electrode formed therebetween, wherein the entire gate electrode of the P-channel field effect transistor is made of a first metal silicide and the gate of the N-channel field effect transistor. The entire electrode is made of a silicide of a second metal having a work function smaller than that of the first metal, and an offset made of a silicon-based insulating film formed in contact with the gate insulating film on both side surfaces in the line width direction of each of the gate electrodes. A sidewall spacer is formed through a spacer film or directly. It is.

  A method of manufacturing a semiconductor device of the present invention that achieves the above object includes a semiconductor substrate, a P-channel field effect transistor having a gate electrode formed on the semiconductor substrate via a gate insulating film, and the semiconductor substrate. A method for manufacturing a semiconductor device comprising an N channel field effect transistor having a gate electrode formed on a gate insulating film on the first element region corresponding to the P channel field effect transistor and the N channel field effect transistor. A corresponding second element region is formed, and the first element region is exposed on a semiconductor substrate on which an element isolation film having a predetermined pattern for locally exposing the first element region and the second element region is formed. P channel disposed on a region to be a channel region of a P channel field effect transistor through a first electrical insulating film covering the surface Forming a first polysilicon electrode serving as a gate electrode of the field effect transistor and a first cap film located on the first polysilicon electrode, and a second electrical insulating film covering the exposed surface of the second element region; A second polysilicon electrode disposed on a region to be a channel region of the N-channel field effect transistor and serving as a source of a gate electrode of the N-channel field effect transistor, and a second cap positioned on the second polysilicon electrode Electrode-cap film forming step for forming a film, and patterning the first and second electrical insulating films to form gate insulating films under the first and second polysilicon electrodes, respectively. A gate insulating film is formed on both side surfaces in the line width direction of the patterning step and each of the first polysilicon electrode and the second polysilicon electrode. A side wall spacer forming step of forming a side wall spacer directly through an offset spacer film made of a silicon-based insulating film formed in contact with, and a plane including the upper surfaces of the first cap film and the second cap film An interlayer insulating film forming step of forming an interlayer insulating film having an upper surface positioned on the first cap film, and after removing the first cap film and the second cap film, a first metal made of a first metal is formed on the first polysilicon electrode. Forming a metal layer, and forming a second metal layer made of a second metal having a work function smaller than that of the first metal on the second polysilicon electrode, and the first metal layer and the first metal layer The entire first polysilicon electrode is silicided with the first metal by reacting with the polysilicon electrode, and the second metal layer and the second polysilicon electrode are reacted to form the second. And a silicidation step of siliciding the entire polysilicon electrode with a second metal.

  In the semiconductor device of the present invention, the gate electrode in the P-channel field effect transistor and the gate electrode in the N-channel field effect transistor are formed of different metal silicides, so that the threshold voltage of these field effect transistors is set to a desired value. Easy to control. Further, sidewall spacers are formed on both side surfaces in the line width direction of each gate electrode via an offset spacer film made of a silicon-based insulating film having an interface with the gate insulating film, or directly. Even when the gate insulating film is formed of a high dielectric constant dielectric, it is easy to suppress an increase in the fringe capacitance between the gate electrode and the source region and an increase in the fringe capacitance between the gate electrode and the drain region. Moreover, according to the method for manufacturing a semiconductor device of the present invention, the semiconductor device of the above-described invention can be obtained.

  Therefore, according to these inventions, it is easy to obtain a semiconductor device including a high-performance P-channel field effect transistor and an N-channel field effect transistor, and as a result, it is easy to obtain a high-performance electronic device.

  Embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described below in detail with reference to the drawings. These inventions are not limited to the embodiments described below.

  FIG. 1 is a cross-sectional view schematically showing an example of the semiconductor device of the present invention. A semiconductor device 50 shown in the figure includes a complementary metal oxide semiconductor (CMOS) transistor 40 formed on a semiconductor substrate 10, and the CMOS transistor 40 includes a P-channel field effect transistor 20 and an N-channel field effect transistor 30. Have.

The semiconductor substrate 10 is obtained by forming a predetermined element region on the P-type silicon substrate 1, and an N-type well 4 is formed in the first element region R ₁ corresponding to the P-channel field effect transistor 20. A P-type well 8 is formed in the second element region R ₂ corresponding to the effect transistor 30. In the N-type well 4, a source region 2s and a drain region 2d made of a P ⁺ -type impurity diffusion region are formed at a predetermined interval. An extension portion ex ₁ composed of a P-type impurity diffusion region is formed at each end of the source region 2s on the drain region 2d side and each end of the drain region 2d on the source region 2s side. On the other hand, in the P-type well 8, a source region 6s and a drain region 6d made of an N ⁺ -type impurity diffusion region are formed at a predetermined interval. Extension portions ex ₂ each including an N-type impurity diffusion region are formed at the end of the source region 6s on the drain region 6d side and the end of the drain region 6d on the source region 6s side, respectively.

“P-type”, “P ⁺ -type”, “N-type”, and “N ⁺ -type” represent semiconductor conductivity types, respectively. P-type impurity (acceptor) concentration in the "P ⁺ -type" is higher than the P-type impurity concentration in the "P-type", N-type impurity (donor) concentration in the "N ⁺ type" is in the "N-type" It is higher than the N-type impurity concentration.

  The P-channel field effect transistor 20 and the N-channel field effect transistor 30 are electrically isolated from each other by an element isolation film 9 made of silicon oxide or the like. Similarly, the CMOS transistor 40 is electrically isolated from the other elements (not shown) formed on the semiconductor substrate 10 by the element isolation film 9.

P-channel field effect transistor 20 has a source region 2s, and a drain region 2d, an extension unit ex _1, the channel region 2c located between the extension portions ex ₁ among the N-type well 4, the channel region 2c A gate electrode 13 made of metal silicide is disposed above the gate insulating film 11.

  The gate insulating film 11 is formed of, for example, silicon oxide, silicon oxynitride, or a high dielectric constant dielectric (hafnium oxide, hafnium silicate, nitrogen-doped hafnium oxide, nitrogen-doped hafnium silicate, or the like). The gate electrode 13 is a silicide of a metal having a high work function such as nickel (Ni), platinum (Pt), iridium (Ir), palladium (Pd), rhodium (Rh), ruthenium (Ru), tungsten (W), etc. The whole is formed by the hatching).

  Offset spacer films 15 are formed on both side surfaces of the gate electrode 13 in the line width direction, and side wall spacers 17 are formed on side surfaces of these offset spacer films 15 in the line width direction. Each offset spacer film 15 prevents punch-through (reduction in the distance between the source and drain) between the source and drain due to diffusion accompanying activation of impurities after extension implantation described later. A silicon-based insulating film formed in contact with the gate insulating film 11, such as a silicon oxide film, is formed. The thickness of these offset spacer films 15 can be appropriately selected within a range of, for example, about 10 nm or less. Each side wall spacer 17 has a two-layer structure of a first side wall 17a disposed on the offset spacer film 15 and a second side wall 17b disposed on the first side wall 17a. ing. The first sidewall 17a is made of, for example, silicon oxide, and the second sidewall 17b is made of, for example, silicon nitride. The thickness of these sidewall spacers 17 (total thickness on the side surface of the gate electrode 13) can be appropriately selected within a range of, for example, about 50 nm or less.

On the other hand, N-channel field effect transistor 30 has a source region 6s, and a drain region 6d, an extension unit ex _2, a channel region 6c located between the extension portions ex ₂ among P type well 8, this channel A gate electrode 23 is provided on the region 6c with a gate insulating film 21 interposed therebetween.

  The gate insulating film 21 is formed of, for example, silicon oxide, silicon oxynitride, or a high dielectric constant dielectric (hafnium oxide, hafnium silicate, nitrogen-doped hafnium oxide, nitrogen-doped hafnium silicate, as in the P-channel field effect transistor 20. Etc.). The gate electrode 23 is contained in the gate electrode 13 such as a metal silicide different from the gate electrode 13 described above, specifically, hafnium (Hf), ytterbium (Yb), erbium (Er), zirconium (Zr), or the like. The whole is formed by a metal silicide having a work function smaller than that of the metal (metal element).

  Offset spacer films 25 made of a silicon-based insulating film such as a silicon oxide film are formed on both side surfaces in the line width direction of the gate electrode 23. Side wall spacers are formed on side surfaces in the line width direction of these offset spacer films 25, respectively. 27 is formed. Each offset spacer film 25 prevents punch-through (reduction in the distance between the source / drain) between the source and drain due to diffusion accompanying activation of impurities after extension implantation described later. It is formed in contact with the gate insulating film 21. The thickness of these offset spacer films 25 can be appropriately selected within a range of about 10 nm or less, for example. Each side wall spacer 27 has a two-layer structure of a first side wall 27a disposed on the offset spacer film 25 and a second side wall 27b disposed on the first side wall 27a. ing. Similar to the sidewall spacer 17 in the P-channel field effect transistor 20 described above, the first sidewall 27a is formed of, for example, silicon oxide, and the second sidewall 17b is formed of, for example, silicon nitride. The film thickness of these sidewall spacers 27 (total film thickness on the side surface of the gate electrode 23) can be appropriately selected within a range of, for example, about 50 nm or less.

  A first interlayer insulating film 42 is provided outside the sidewall spacers 17 and 27 in the field effect transistors 20 and 30 so as to cover the source regions 2s and 6s and the drain regions 2d and 6d. A second interlayer insulating film 44 is provided so as to cover the interlayer insulating film 42 and the gate electrodes 13 and 23. The first interlayer insulating film 42 and the second interlayer insulating film 44 are contact plugs penetrating the interlayer insulating films 42 and 44 and having one end in contact with the source region 2s, the drain region 2d, the drain region 6d, or the source region 6s. The required number 46 is formed. A predetermined upper wiring 48 is connected to the other end of each contact plug 46. In FIG. 1, four contact plugs 46 and four upper wirings 48 appear.

In the CMOS transistor 40 having the structure described above, the gate electrode 13 of the P-channel field effect transistor 20 and the gate electrode 23 of the N-channel field effect transistor 30 are formed of different metal silicides. , 23, the threshold voltage (V _th ) of each of the P-channel field effect transistor 20 and the N-channel field effect transistor 30 can be easily controlled to a desired value. Further, even when the gate insulating films 11 and 21 are formed of a high dielectric constant dielectric, since the offset spacer films 17 and 27 are formed on the side surfaces of the gate electrodes 13 and 23, the gate electrode 13 and the source region 2s Fringe capacitance between the gate electrode 13 and the drain region 2d, fringe capacitance between the gate electrode 23 and the source region 6s, and fringe capacitance between the gate electrode 23 and the drain region 6d, respectively. Easy to keep small values.

  Therefore, in the above-described CMOS transistor 40, it is easy to improve the performance of each of the P-channel field effect transistor 20 and the N-channel field effect transistor 30, and as a result, the overall performance of the semiconductor device 50 including the CMOS transistor 40 is also improved. easy.

  The offset spacer films 15 and 25 described above can be omitted. When the offset spacer films 15 and 25 are omitted, the side wall spacers 17 and 27 are directly formed on both side surfaces of the gate electrodes 13 and 23 in the line width direction. Further, it is possible to use an N-type silicon substrate instead of the P-type silicon substrate 1 shown in FIG. Furthermore, it is not always necessary to form a well in each element region corresponding to the field effect transistor. When a P-type polysilicon substrate is used, the formation of the P-type well can be omitted. When an N-type polysilicon substrate is used, the formation of the N-type well can be omitted.

  The semiconductor device 50 described above can be obtained by the manufacturing method (semiconductor device manufacturing method) of the present invention. As described above, this manufacturing method includes an electrode-cap film forming process, a patterning process, a sidewall spacer forming process, an interlayer insulating film forming process, a metal layer forming process, and a silicidation process. Hereinafter, the reference numerals used in FIG.

(Electrode-cap film forming process)
In the electrode-cap film forming step, a first element region corresponding to the P-channel field effect transistor and a second element region corresponding to the N-channel field effect transistor are formed, and the first element region and the second element region are respectively formed. On a region to be a channel region of a P-channel field effect transistor on a semiconductor substrate on which an element isolation film having a predetermined pattern to be locally exposed is formed via a first electric insulating film covering an exposed surface of the first element region And a first polysilicon electrode serving as a source of the gate electrode of the P-channel field effect transistor and a first cap film located on the first polysilicon electrode are formed. In addition, a second electrode serving as the source of the gate electrode of the N-channel field effect transistor is disposed on the region serving as the channel region of the N-channel field effect transistor via the second electrical insulating film covering the exposed surface of the second element region. A polysilicon electrode and a second cap film located on the second polysilicon electrode are formed.

  In order to form the first polysilicon electrode, the first cap film, the second polysilicon electrode, and the second cap film, first, the first electrical insulating film and the second electrical insulating film are formed on the semiconductor substrate. Further, a base material on which the polysilicon film that covers these electrical insulating films and the element isolation film, and the inorganic film that covers the polysilicon film is formed, or the base material is formed. Buy.

FIG. 2 is a cross-sectional view schematically showing an example of the base material. In the base material BM shown in the figure, the first electric insulating film 61a, the second electric insulating film 61b, the polysilicon film 63, and the inorganic film 65 are formed on the semiconductor substrate 10A. The semiconductor substrate 10A has a first element region R ₁ corresponding to a P-channel field effect transistor and a second element region R ₂ corresponding to an N-channel field effect transistor formed on a P-type silicon substrate 1, and these elements A device isolation film 9 having a predetermined pattern for locally exposing each of the regions R ₁ and R ₂ is formed. An N-type well 4 is formed in the first element region R ₁ , and a P-type well 8 is formed in the second element region R ₂ . The element isolation film 9 is formed by a method such as LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation).

It is also possible to use an N-type silicon substrate instead of the P-type silicon substrate 1. In addition, it is not always necessary to form a well in each of the element regions R ₁ and R _{2. When} a P-type polysilicon substrate is used, the formation of the P-type well can be omitted. When the type polysilicon substrate is used, the formation of the N type well can be omitted.

The first electrically insulating film 61a is to cover the first exposed surface of the device region R ₁ is formed on a P-type silicon substrate 1, the second electrical insulating film 61b is exposed in the second element region R ₂ It is formed on a P-type silicon substrate 1 so as to cover the surface. The first electrical insulating film 61a is a film that becomes the source of the gate insulating film 11 (see FIG. 1), and the second electrical insulating film 61b is a film that becomes the source of the gate insulating film 21 (see FIG. 1). These electrical insulating films 61a and 61b are formed of silicon oxide, silicon oxynitride, high dielectric constant dielectric (hafnium oxide, hafnium silicate, nitrogen-doped hafnium oxide, nitrogen-doped hafnium silicate, or the like). In forming each of the electric insulating films 61a and 61b, a thermal oxidation method, a physical vapor deposition method (PVD method), a chemical vapor deposition method (CVD method), or the like is appropriately applied depending on the composition. .

  The polysilicon film 63 is a film that becomes the source of the first polysilicon electrode and the second polysilicon electrode described above. For example, undoped polysilicon is deposited on the element isolation film 9 and the electrical insulating films 61a and 61b by the CVD method. It is formed by depositing or by depositing polysilicon to which an impurity (dopant) is added. In addition, the inorganic film 65 is a film that is a source of the above-described first cap film and second cap film (a film that functions as a stopper film in an interlayer insulating film forming step described later). It is formed by depositing silicon nitride or the like on the silicon film 63.

  If necessary, the portion corresponding to the channel region 2c (see FIG. 1) of the P-channel field effect transistor 20 in the N-type well 4 and the channel region 6c of the N-channel field-effect transistor 30 in the P-type well 8 are used. A channel profile may be controlled by doping a portion corresponding to (see FIG. 1) with an impurity (dopant) via the electric insulating film 61a or the electric insulating film 61b. Similarly, the conductivity may be controlled by doping the polysilicon film 63 with an impurity (dopant) using an ion implantation method or a solid phase diffusion method.

  The first polysilicon electrode and the first cap film thereon, and the second polysilicon electrode and the second cap film thereon are formed by patterning the inorganic film 65 and the polysilicon film 63 described above. . The first polysilicon electrode is disposed on a region corresponding to the channel region 2c (see FIG. 1), and the second polysilicon electrode is disposed on a region corresponding to the channel region 6c (see FIG. 1).

  The patterning at this time is, for example, forming a photoresist layer on the inorganic film 65, patterning the photoresist layer by a photolithography method to form a resist pattern of a predetermined shape, and then using this resist pattern as an etching mask Then, the inorganic film 65 and the polysilicon film 63 can be etched sequentially. Further, the inorganic film 65 is etched using the resist pattern as an etching mask to form a first cap film and a second cap film, and then the first cap film and the second cap film are used as an etching mask to form a polycrystal. It can also be performed by etching the silicon film 63.

  FIG. 3A is a cross-sectional view schematically showing an example of a photoresist layer 67 formed on the inorganic film 65, and FIG. 3B is formed on the inorganic film 65 by patterning the photoresist layer 67. It is sectional drawing which shows roughly an example of the resist pattern 67p used. FIG. 3C shows the first polysilicon electrode 63a, the first cap film 65a, and the second poly-silicon formed by sequentially etching the inorganic film 65 and the polysilicon film 63 using the resist pattern 67p as an etching mask. It is sectional drawing which shows roughly an example of each of the silicon electrode 63b and the 2nd cap film 65b. The heights of the first polysilicon electrode 63a and the second polysilicon electrode 63b with respect to the P-type silicon substrate 1 are substantially the same, and the first cap film 65a with respect to the P-type silicon substrate 1 and The heights of the second cap films 65b are also substantially the same. The upper surface of the first cap film 65a and the upper surface of the second cap film 65b are located on substantially the same plane.

  The etchant used when patterning the inorganic film 65 by wet etching is appropriately selected according to the composition of the inorganic film 65. When the inorganic film 65 is made of silicon nitride, for example, hot phosphoric acid or the like can be used as an etchant. Further, when patterning the polysilicon film 63 by wet etching, for example, ammonia perwater, hydrofluoric acid, or the like can be used as an etchant. When the inorganic film 65 and the polysilicon film 63 are patterned by dry etching, for example, an etching gas such as a gas containing at least one of chlorine and hydrogen bromide (HBr) can be used. Note that the resist pattern 67p can also be formed by using a lithography method other than the photolithography method, for example, an electron beam lithography method or an X-ray lithography method.

(Patterning process)
In the patterning step, each of the above-described electrical insulating films is patterned to form a gate insulating film under each of the first polysilicon electrode and the second polysilicon electrode. In the case of forming a field effect transistor in which offset spacer films are formed on both sides of the gate electrode in the line width direction, prior to patterning the above-described electric insulating film, silicon-based insulation that is the source of the offset spacer film is used. It is preferable to form a film.

  FIG. 4A is a cross-sectional view schematically showing an example of the silicon-based insulating film. The silicon-based insulating film 69 shown in the figure is formed so as to cover the first polysilicon electrode 63a, the second polysilicon electrode 63b, the electric insulating films 61a and 61b, and the element isolation film 9. The silicon insulating film 69 is made of a silicon insulating material such as silicon oxide, silicon oxynitride, or silicon nitride.

  FIG. 4B is a cross-sectional view schematically showing an example of the gate insulating film formed by patterning the above-described electrical insulating films 61a and 61b. As shown in the figure, the gate insulating film 11 is formed under the first polysilicon electrode 63a, and the gate insulating film 21 is formed under the second polysilicon electrode 63b. The gate insulating film 11 is formed by patterning the electric insulating film 61a, and the gate insulating film 21 is formed by patterning the electric insulating film 61b.

  When the silicon-based insulating film 69 described above is formed, the offset spacer film and the gate insulating film can be formed by the same etching process. On the side surfaces (including both side surfaces in the line width direction) of the stack of the first polysilicon electrode 63a and the first cap film 65a and the stack of the second polysilicon electrode 63b and the second cap film 65b. The offset spacer film 15 or the offset spacer film 25 is formed from the silicon-based insulating film 69. Each offset spacer film 15, 25 is in contact with the corresponding gate insulating film 11, 21. The patterning of the electrical insulating films 61a and 61b and the silicon-based insulating film 69 can be performed, for example, by performing dry etching on these films 61a, 61b, and 69 without using an etching mask.

  When a field effect transistor having a source region and a drain region having an LDD (Lightly Doped Drain) structure is to be formed, after the above-described offset spacer films 15 and 25 and gate insulating films 11 and 21 are formed, a P-type transistor is formed. It is preferable to dope impurities into the silicon substrate 1 (by performing extension implantation and subsequent activation) to form an impurity diffusion region with a small impurity dose and a shallow impurity implantation depth. Impurity diffusion regions corresponding to the P-channel field effect transistor are formed in the P-type silicon substrate 1 so as to face each other across the polysilicon electrode 63a when viewed in plan, and the impurity diffusion region corresponding to the N-channel field effect transistor The regions are formed in the P-type silicon substrate 1 so as to face each other across the polysilicon electrode 63b when viewed in plan.

FIG. 5 is a cross-sectional view schematically showing an example of the impurity diffusion region. As shown in the figure, among the N-type wells 4 formed on the P-type silicon substrate 1, when viewed in plan, the first polysilicon electrode 63a is lateral to the line width direction (the right and left sides in FIG. 5). ), A P-type impurity diffusion region LD ₁ having a small impurity dose and a shallow impurity implantation depth is formed. Each of the P-type wells 8 formed on the P-type silicon substrate 1 is located on the side of the second polysilicon electrode 63b in the line width direction (on the right side and the left side in FIG. 5) when viewed in plan. In the region, an N-type impurity diffusion region LD ₂ having a small impurity dose and a shallow impurity implantation depth is formed. The P-type impurity diffusion region LD ₁ is the source of the extension portion ex ₁ shown in FIG. 1, and the N-type impurity diffusion region LD ₂ is the source of the extension portion ex ₂ shown in FIG.

(Sidewall spacer formation process)
In the side wall spacer forming step, the side wall spacers are formed on the both sides in the line width direction of each of the first polysilicon electrode and the second polysilicon electrode via the offset spacer film described above or directly. The sidewall spacer is formed of, for example, silicon oxide or silicon nitride, and the layer structure can be a single layer structure, or a stacked structure in which two or more layers are stacked in the thickness direction. You can also. The sidewall spacer is formed by, for example, etching back the film after forming the film as a base.

FIG. 6A is a cross-sectional view schematically illustrating an example of a stacked film formed when forming a sidewall spacer having a stacked structure. The laminated film 71 shown in the figure is a first spacer formed so as to cover the first cap films 65a and 65b, the offset spacer films 15 and 25, the impurity diffusion regions LD ₁ and LD ₂ , and the element isolation film 9. A film 71a and a second spacer film 71b formed so as to cover the first spacer film 71a are provided. The first spacer film 71a is made of, for example, silicon oxide, and the second spacer film 71b is made of, for example, silicon nitride.

  FIG. 6B is a cross-sectional view schematically illustrating an example of a sidewall spacer having a stacked structure. The side wall spacers 17 and 27 shown in the figure are formed by etching back the laminated film 71 described above. Each sidewall spacer 17 is formed outside the offset spacer film 15, and each sidewall spacer 27 is formed outside the offset spacer film 25. Each side wall spacer 17 has a two-layer structure of a first side wall 17a disposed on the offset spacer film 15 and a second side wall 17b disposed on the first side wall 17a. Similarly, each sidewall spacer 27 has a two-layer structure including a first sidewall 27a disposed on the offset spacer film 25 and a second sidewall 27b disposed on the first sidewall 27a. ing.

  The source region and the drain region corresponding to each field effect transistor are formed after the sidewall spacer is formed. These source region and drain region can be formed as follows, for example. First, a donor is ion-implanted into a region corresponding to each of the source region and the drain region of the P-channel field effect transistor in the N-type well 4 by an ion implantation method using an ion implantation mask having a predetermined shape, for example. An addition region is formed. In addition, an acceptor is ion-implanted into a region corresponding to each of the source region and the drain region of the N-channel field effect transistor in the P-type well 8 by, for example, ion implantation using an ion implantation mask having a predetermined shape, so that the impurity-added region Form. Thereafter, heat treatment for impurity activation is performed on these impurity-added regions, thereby forming necessary impurity diffusion regions (source region and drain region) at a time.

The impurity dose in each impurity diffusion region is larger than the impurity dose in the impurity diffusion regions LD ₁ and LD ₂ described above. The impurity implantation depth in these impurity diffusion regions is deeper than the impurity implantation depth in the impurity diffusion regions LD ₁ and LD ₂ described above. By forming the source region and the drain region on the P-type silicon substrate 1, the P-type silicon substrate 1 becomes the semiconductor substrate 10 shown in FIG.

  FIG. 7 is a cross-sectional view schematically showing an example of each of the source region and the drain region described above. As shown in the figure, a source region 2s and a drain region 2d are formed in the N-type well 4 so as to face each other across the first polysilicon electrode 63a when seen in a plan view. The drain region 6d and the source region 6s are formed so as to face each other across the second polysilicon electrode 63b when seen in a plan view.

The end of the source region 2s on the drain region 2d side reaches below the side wall spacer 17 on the source region 2s side, and the impurity diffusion region LD ₁ (see FIG. extension unit ex ₁ consisting of a part of the 6-2 references) are continuous. Further, the end of the drain region 2d on the source region 2s side reaches below the side wall spacer 17 on the drain region 2d side, and the impurity diffusion region LD ₁ (see FIG. extension unit ex ₁ consisting of a part of the 6-2 references) are continuous. Region between the extension part ex ₁ of the extension portion ex ₁ and drain region 2d side of the source region 2s side, a channel region 2c.

Similarly, the end of the drain region 6d on the source region 6s side reaches below the sidewall spacer 27 on the drain region 6d side, and the impurity diffusion region LD is closer to the source region 6s than this end. ₂ is an extension part ex ₂ consisting of a part of (see Figure 6-2) are continuous. Further, the end of the source region 6s on the drain region 6d side reaches to the lower side of the sidewall spacer 27 on the source region 6s side, and the impurity diffusion region LD ₂ (see FIG. extension unit ex ₂ consisting of a part of the 6-2 references) are continuous. Region between the extension part ex ₂ of the extension portion of the drain region 6d side ex ₂ and the source region 6s side, a channel region 6c.

(Interlayer insulation film formation process)
In the interlayer insulating film forming step, an interlayer insulating film whose upper surface is located on a plane including the upper surfaces of the first cap film and the second cap film (interlayer insulating film serving as a source of the first interlayer insulating film 42 shown in FIG. 1) Form. This interlayer insulating film is formed, for example, by forming a thick insulating film on the entire surface of the P-type silicon substrate 1 on the side where the first polysilicon electrode 63a and the second polysilicon electrode 63b are formed by CVD or the like. The insulating film is formed by thinning it by a method such as CMP (Chemical Mechanical Polishing). Since the interlayer insulating film is exposed to a heat treatment in a silicidation process to be described later, the interlayer insulating film is made of an inorganic material that does not deform or diffuse into the P-type silicon substrate 1, for example, USG (Un-doped Silicate Glass). It is preferable to form.

  FIG. 8A is a cross-sectional view schematically illustrating an example of the above-described thick insulating film. As shown in the figure, the insulating film 73 covers the first cap film 65a and the second cap film 65b so that the first polysilicon electrode 63a and the second polysilicon electrode 63b are formed on the P-type silicon substrate 1. It is formed on the entire surface on the side where it is formed.

  FIG. 8-2 is a sectional view schematically showing an example of the interlayer insulating film. The interlayer insulating film 73a shown in the figure is formed by thinning the insulating film 73 shown in FIG. 8A by a method such as CMP, and the upper surface thereof has the first cap film 65a and the second cap film 65a. The cap film 65b is located on a plane including the upper surface. The first cap film 65a and the second cap film 65b function as stopper films when the insulating film 73 is thinned by a method such as CMP.

(Metal layer forming process)
In the metal layer forming step, after removing the first cap film and the second cap film, a first metal layer made of the first metal is formed on the first polysilicon electrode, and the second polysilicon electrode is formed on the first polysilicon electrode. Forms a second metal layer made of a second metal having a work function lower than that of the first metal. Each cap film can be removed by wet etching, for example. When each cap film is formed of silicon nitride, for example, hot phosphoric acid can be used as an etchant.

  By removing each cap film, a recess is formed above each of the first polysilicon electrode and the second polysilicon electrode. Therefore, the recess is formed so as to fill the recess formed above the first polysilicon electrode. One metal layer is formed, and the second metal layer is formed so as to fill a recess formed above the second polysilicon electrode. These first metal layer and second metal layer can be formed by, for example, a PVD method. The thickness of each metal layer is appropriately selected according to the thickness and line width of each polysilicon electrode so that the entire first polysilicon electrode or the entire second polysilicon electrode can be silicided. Note that either the first metal layer or the second metal layer may be formed first. Hereinafter, with reference to FIGS. 9-1 to 9-5, the first metal layer and the second metal layer are formed by taking a case where the first metal layer is formed before the second metal layer as an example. This will be specifically described.

FIG. 9A is a cross-sectional view schematically showing an example of a recess formed on the first polysilicon electrode and the second polysilicon electrode by removing the first cap film and the second cap film, respectively. . As shown in the figure, a recess C ₁ having a shape corresponding to the contour shape of the first cap film 65a (see FIG. 8-2) is formed on the first polysilicon electrode 63a, and the second polysilicon electrode 63b. A recess C ₂ having a shape corresponding to the contour shape of the second cap film 65b (see FIG. 8-2) is formed on the top.

In forming the first metal layer on the first polysilicon electrode 63a, for example, by the PVD method, on the polysilicon electrodes 63a and 63b and the interlayer insulating film 73a so as to fill the recesses C ₁ and C _2. Then, a first metal is deposited to form a conductive layer, and then a region of the conductive layer located on and around the second polysilicon electrode 63b is removed. At this time, a resist pattern having a predetermined shape is provided on the conductive layer on and around the first polysilicon electrode 63a, and an etching process is performed using the resist pattern as an etching mask, so that the second polysilicon electrode 63b and The conductive layer around it is selectively removed. Since the specific example of the first metal has already been exemplified in the description of the gate electrode 13 in the semiconductor device 50 shown in FIG. 1, the description thereof is omitted here.

FIG. 9-2 shows an example of a conductive layer formed by depositing a first metal on the polysilicon electrodes 63a and 63b and the interlayer insulating film 73a so as to fill the recesses C ₁ and C _2. FIG. The conductive layer 75 shown in the figure is formed by isotropically depositing a first metal on each of the polysilicon electrodes 63a and 63b and the interlayer insulating film 73a, and from above the first polysilicon electrode 63a. It extends over the second polysilicon electrode 63b and the interlayer insulating film 73a.

  FIG. 9-3 is a cross-sectional view schematically showing an example of a resist pattern formed on the conductive layer when the conductive layer on and around the second polysilicon electrode is selectively removed. As shown in the figure, the resist pattern 77 covers the conductive layer 75 on and around the first polysilicon electrode 63a, and exposes the conductive layer 75 on and around the second polysilicon electrode 63b. Formed on the conductive layer 75.

  FIG. 9-4 is a cross-sectional view schematically showing an example of the first metal layer formed on the first polysilicon electrode 63a. The first metal layer 75a shown in the figure is formed by patterning the conductive layer 75 by an etching process using the resist pattern 77 as an etching mask. The first metal layer 75a is formed on and around the first polysilicon electrode 63a. Is formed. The upper surface of the second polysilicon electrode 63b and its periphery are exposed without being covered with the first metal layer 75a. The resist pattern 77 (see FIG. 9-4) is peeled off after the formation of the first metal layer 75a.

FIG. 9-5 is a cross-sectional view schematically showing an example of the second metal layer formed on the second polysilicon electrode. The second metal layer 79 shown in the figure, so as to fill the recess C ₂ on the second polysilicon electrode 63b, for example, by PVD, on the interlayer insulating film 73a from the second polysilicon electrode 63b and the first metal It is formed over the layer 75a. A specific example of the second metal has already been exemplified in the description of the gate electrode 23 in the semiconductor device 50 illustrated in FIG. 1, and thus the description thereof is omitted here.

(Silicidation process)
In the silicidation step, the first metal layer and the first polysilicon electrode described above are reacted to silicide the entire first polysilicon electrode with the first metal, and the second metal layer, the second polysilicon electrode, To cause the entire second polysilicon electrode to be silicided with the second metal.

  The silicidation of the first polysilicon electrode 63a and the second polysilicon electrode 63b is performed, for example, by using the semiconductor substrate 10 on which the first metal layer 75a and the second metal layer 79 are formed in an inert gas atmosphere at several hundred to 900 ° C. This is done by heating to the extent. The processing time for silicidation is appropriately selected according to the thickness of each of the first polysilicon electrode 63a and the second polysilicon electrode 63b, the composition of each of the first metal layer 75a and the second metal layer 79, the processing temperature, and the like. Is done. After silicidation, the remaining metal layer is removed by etching, for example.

  FIG. 10 is a cross-sectional view schematically showing an example of each gate electrode formed by silicidation described above. The gate electrode 13 shown in the figure is a gate electrode corresponding to the P-channel field effect transistor 20 (see FIG. 1), and is formed by siliciding the entire first polysilicon electrode 63a with the first metal. ing. The gate electrode 23 is a gate electrode corresponding to the N-channel field effect transistor 30 (see FIG. 1), and is formed by siliciding the entire second polysilicon electrode 63b with the second metal. .

  In the semiconductor device 50 shown in FIG. 1, after performing the silicidation process as described above, an insulating layer serving as a base of the second interlayer insulating film 44 (see FIG. 1) is formed of a desired organic material or inorganic material. By forming a predetermined number of contact plugs 46 (see FIG. 1) at predetermined locations between the insulating layer and the interlayer insulating film 73a, the upper wiring 48 (see FIG. 1) is connected to each contact plug. Obtainable.

  In forming the insulating layer that is the source of the second interlayer insulating film 44, a spin coating method, a CVD method, or the like can be applied depending on the material. Each contact plug 46 is formed, for example, by forming a contact hole by anisotropic etching at a predetermined location between the insulating layer that is the source of the second interlayer insulating film 44 and the interlayer insulating film 73a. It can be formed by depositing a conductive material such as a tungsten-aluminum alloy by an evaporation method and then removing the excess conductive material deposited on the insulating layer. By forming the contact hole in the interlayer insulating film 73a, the first interlayer insulating film 42 shown in FIG. 1 is obtained, and the contact hole is formed in the insulating layer that is the basis of the second interlayer insulating film 44. By forming, the second interlayer insulating film 44 shown in FIG. 1 is obtained. Each upper wiring 48 is formed, for example, by forming a conductive film on the second interlayer insulating film 44 after forming each contact plug 46 and forming an etching mask of a predetermined shape on the conductive film and then etching the conductive film. Can be formed. It is also possible to use damascene wiring as the upper wiring 48.

  The semiconductor device of the present invention only needs to have a P-channel field effect transistor and an N-channel field effect transistor, and these P-channel field effect transistor and N-channel field effect transistor may constitute a CMOS transistor. It does not have to be configured. Similarly, the method for manufacturing a semiconductor device according to the present invention can be applied to the manufacture of a semiconductor device having a P-channel field effect transistor and an N-channel field effect transistor. The effect transistor may or may not constitute a CMOS transistor. Various modifications, modifications, combinations, and the like are possible in addition to the above-described embodiments.

It is sectional drawing which shows roughly an example of the semiconductor device of this invention. An example of a substrate used when forming the first polysilicon electrode, the first cap film, the second polysilicon electrode, and the second cap film in the electrode-cap film forming step in the method of manufacturing a semiconductor device of the present invention. It is sectional drawing shown roughly. It is sectional drawing which shows roughly an example of the photoresist layer formed on an inorganic film at the electrode-cap film formation process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of the resist pattern formed on an inorganic film at the electrode-cap film formation process in the manufacturing method of the semiconductor device of this invention. Section which shows roughly an example of each of the 1st polysilicon electrode, the 1st cap film, the 2nd polysilicon electrode, and the 2nd cap film which are formed at the electrode-cap film formation process in the manufacturing method of the semiconductor device of this invention FIG. It is sectional drawing which shows roughly an example of the silicon-type insulating film used as the origin of the offset spacer film | membrane formed as needed at the patterning process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of the gate insulating film formed at the patterning process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of the impurity diffusion area | region formed as needed during transfer from the patterning process in the manufacturing method of the semiconductor device of this invention to a sidewall spacer formation process. It is sectional drawing which shows roughly an example of the laminated film formed when forming the side wall spacer of laminated structure in the side wall spacer formation process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of the side wall spacer of the laminated structure among the side wall spacers formed at the side wall spacer formation process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of each of the source region and drain region which are formed during the transition from the sidewall spacer forming step to the interlayer insulating film forming step in the semiconductor device manufacturing method of the present invention. It is sectional drawing which shows roughly an example of the thick insulation film used as the origin of the interlayer insulation film formed at the interlayer insulation film formation process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of the interlayer insulation film formed at the interlayer insulation film formation process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of the recessed part formed by each removing a 1st cap film and a 2nd cap film at the metal layer formation process in the manufacturing method of the semiconductor device of this invention. The conductive layer formed over the first polysilicon electrode, the second polysilicon electrode and the interlayer insulating film when the first metal layer is formed in the metal layer forming step in the semiconductor device manufacturing method of the present invention. It is sectional drawing which shows an example schematically. It is sectional drawing which shows roughly an example of the resist pattern used when forming a 1st metal layer at the metal layer formation process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of the 1st metal layer formed on a 1st polysilicon electrode at the metal layer formation process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of the 2nd metal layer formed on a 2nd polysilicon electrode at the metal layer formation process in the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows roughly an example of each gate electrode formed at the silicidation process in the manufacturing method of the semiconductor device of this invention.

Explanation of symbols

2c Channel region of P-channel field effect transistor 6c Channel region of N-channel field effect transistor 9 Element isolation film 10 Semiconductor substrate 11, 21 Gate insulating film 13, 23 Gate electrode 15, 25 Offset spacer film 17, 27 Side wall spacer 20 P Channel field effect transistor 30 N channel field effect transistor 50 Semiconductor device 61a First electrical insulating film 61b Second electrical insulating film 63a First polysilicon electrode 63b Second polysilicon electrode 65a First cap film 65b Second cap film 73a Interlayer insulation Film 75a first metal layer 79 second metal layer R ₁ first element region R ₂ second element region

Claims (2)

A semiconductor substrate, a P-channel field effect transistor having a gate electrode formed on the semiconductor substrate via a gate insulating film, and an N-channel field effect transistor having a gate electrode formed on the semiconductor substrate via a gate insulating film A semiconductor device comprising:
The whole gate electrode of the P-channel field effect transistor is made of a first metal silicide, and the whole gate electrode of the N-channel field effect transistor is made of a second metal silicide having a work function smaller than that of the first metal. Side wall spacers are formed on both side surfaces in the line width direction of each gate electrode via offset spacer films made of a silicon-based insulating film formed in contact with the gate insulating film or directly. A featured semiconductor device. A semiconductor substrate, a P-channel field effect transistor having a gate electrode formed on the semiconductor substrate via a gate insulating film, and an N-channel field effect transistor having a gate electrode formed on the semiconductor substrate via a gate insulating film A method of manufacturing a semiconductor device comprising:
A first element region corresponding to the P channel field effect transistor and a second element region corresponding to the N channel field effect transistor are formed, and the first element region and the second element region are locally exposed, respectively. A semiconductor substrate on which an element isolation film having a predetermined pattern is formed is disposed on a region to be a channel region of the P-channel field effect transistor via a first electric insulating film covering an exposed surface of the first element region. Forming a first polysilicon electrode serving as a gate electrode of the P-channel field effect transistor and a first cap film located on the first polysilicon electrode, and covering an exposed surface of the second element region The N channel field effect is disposed on a region to be a channel region of the N channel field effect transistor through a second electrical insulating film. A cap film formation process, - electrodes the underlying second polysilicon electrode of the gate electrode, and forming a second cap layer located on the second polysilicon electrode of the transistor
Patterning the first electrical insulating film and the second electrical insulating film, respectively, to form a gate insulating film under each of the first polysilicon electrode and the second polysilicon electrode; and
The sidewalls of the first polysilicon electrode and the second polysilicon electrode on both side surfaces in the line width direction via offset spacer films made of a silicon-based insulating film formed in contact with the gate insulating film, or directly A sidewall spacer forming step of forming a spacer;
An interlayer insulating film forming step of forming an interlayer insulating film having an upper surface located on a plane including the upper surfaces of the first cap film and the second cap film;
After removing each of the first cap film and the second cap film, a first metal layer made of a first metal is formed on the first polysilicon electrode, and the first polysilicon layer is formed on the second polysilicon electrode. A metal layer forming step of forming a second metal layer made of a second metal having a work function smaller than that of the first metal;
The first metal layer and the first polysilicon electrode are reacted to silicide the entire first polysilicon electrode with the first metal, and the second metal layer and the second polysilicon electrode are A silicidation step of reacting and siliciding the entire second polysilicon electrode with the second metal;
A method for manufacturing a semiconductor device, comprising:

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