JP2010050131A - Method of manufacturing semiconductor apparatus, and semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor apparatus capable of selectively turning a prescribed region on a resistance layer to silicide by a simple process without adding any special processes. <P>SOLUTION: The method includes: a step for forming a gate electrode 50 on an insulating layer 40 in a first device formation region 1 and forming a conductive layer 50 on the insulating layer 40 of a second device formation region 2; a step for partially removing the insulating layer 40 and exposing a semiconductor substrate 10 of the first device formation region 1 and a resistance layer 30 of the second device formation region 2; a step for forming source and drain regions 70a, 70b by implanting impurities to the exposed semiconductor substrate 10 of the first device formation region 1; and a step for forming a silicide layer 80 on the source region and the drain regions 70a, 70b and on the exposed resistance layer 30 of the second device formation region 2. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  In a semiconductor device, generally, a technique in which a transistor element, a resistance element, and the like are mounted on the same silicon substrate is known.

  In MOS (Metal Oxide Semiconductor) transistors, as miniaturization progresses, impurity regions in the source region and the drain region become thinner to suppress the short channel effect. Therefore, a salicide technique is known in which a silicide layer is formed in a self-mixing manner in the source region and the drain region in order to prevent an increase in the layer resistance of the source region and the drain region.

  Here, when the source region and the drain region are salicided, even the resistance layer of the resistance element is salicided, which causes a problem that a desired resistance cannot be obtained.

For example, Patent Document 1 discloses a method in which a region of a resistance element is covered with a sidewall insulating layer and a desired region is selectively salicided.
JP-A-5-259115

  However, in the method disclosed in Patent Document 1, it is necessary to add a step of forming a resist layer in order to form a sidewall insulating layer that covers the region of the resistance element, which may complicate the process.

  One of the objects of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device that can selectively salicide a predetermined region on a resistance layer by a simple process without adding a special process. There is.

A method for manufacturing a semiconductor device according to the present invention includes:
A method of manufacturing a semiconductor device having a first element formation region and a second element formation region,
Forming a resistance layer in the second element formation region;
Forming an insulating layer above the semiconductor substrate in the first element formation region and above the resistance layer in the second element formation region;
Forming a gate electrode above the insulating layer in the first element forming region and simultaneously forming a conductive layer above the insulating layer in the second element forming region;
Removing a part of the insulating layer to expose the semiconductor substrate in the first element formation region and the resistance layer in the second element formation region;
Implanting impurities into the semiconductor substrate exposed in the first element formation region to form a source region and a drain region;
Forming a silicide layer on the source region and the drain region and on the exposed resistance layer of the second element formation region;
including.

  The manufacturing method of a semiconductor device according to the present invention can selectively salicide a predetermined region on the resistance layer by a simple process without adding a special process.

  In the description of the present invention, the word “upper” is, for example, “forms another specific thing (hereinafter referred to as“ B ”)“ above ”a specific thing (hereinafter referred to as“ A ”)”. Etc. In the description according to the present invention, in the case of this example, the case where B is directly formed on A and the case where B is formed on A via another are included. The word “upward” is used.

In the method for manufacturing a semiconductor device according to the present invention,
The step of forming the resistance layer includes
The resistance layer can be formed by implanting impurities into the semiconductor substrate in the second element formation region.

In the method for manufacturing a semiconductor device according to the present invention,
Furthermore, the method may include a step of forming an element isolation layer that partitions the first element formation region and the second element formation region.

In the method for manufacturing a semiconductor device according to the present invention,
The step of forming the resistance layer includes
Forming a low resistance layer having a resistance lower than that of the resistance layer above the semiconductor substrate in the second element formation region, and implanting impurities into the low resistance layer to increase the resistance; Can be formed.

In the method for manufacturing a semiconductor device according to the present invention,
The low resistance layer may be made of polysilicon.

In the method for manufacturing a semiconductor device according to the present invention,
And a step of forming an element isolation layer on the semiconductor substrate in the second element formation region,
The element isolation layer is formed to partition the first element formation region,
The resistance layer may be formed on the element isolation layer in the second element formation region.

In the method for manufacturing a semiconductor device according to the present invention,
Furthermore, a step of forming a sidewall on the sidewall of the gate electrode and the conductive layer can be provided.

In the method for manufacturing a semiconductor device according to the present invention,
The gate electrode and the conductive layer may be made of polysilicon.

A semiconductor device according to the present invention includes:
A semiconductor device having a first element formation region and a second element formation region,
A semiconductor substrate;
A resistance layer formed in the second element formation region;
An insulating layer formed above the semiconductor substrate in the first element formation region and above the resistance layer in the second element formation region;
A gate electrode formed above the insulating layer in the first element formation region;
A conductive layer formed above the insulating layer in the second element formation region;
A source region and a drain region formed in the semiconductor substrate in the first element formation region;
A silicide layer formed on the source region and the drain region, and on the resistance layer of the second element formation region;
Including
The gate electrode and the conductive layer are made of the same material.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

1. 1. First embodiment 1.1. FIG. 1 is a cross-sectional view schematically showing a semiconductor device 100 according to the first embodiment. As illustrated in FIG. 1, the semiconductor device 100 includes a semiconductor substrate 10 and an element isolation layer 20.

  The semiconductor substrate 10 is made of a first conductivity type (for example, P type) silicon substrate.

  The element isolation layer 20 is formed on the semiconductor substrate 10. The element isolation layer 20 includes, for example, a LOCOS (Local Oxidation of Silicon) layer, a semi-recessed LOCOS layer, and a trench insulating layer. In the illustrated example, the element isolation layer 20 is a LOCOS layer. The element isolation layer 20 can partition the first element formation region 1 and the second element formation region 2.

(1) First Element Formation Region In the first element formation region 1, a MOS transistor 1T is formed as shown in FIG. The MOS transistor 1T includes an insulating layer 40, a gate electrode 50, sidewalls 60, source and drain regions 70a and 70b, and a silicide layer 80.

  The insulating layer 40 is formed on the semiconductor substrate 10. The insulating layer 40 is made of, for example, silicon dioxide.

  The gate electrode 50 is formed on the insulating layer 40. The gate electrode 50 is made of, for example, polysilicon.

  The side wall 60 is formed on the side wall of the gate electrode 50. The sidewall 60 is made of, for example, silicon dioxide.

  The source and drain regions 70 a and 70 b are formed in the semiconductor substrate 10. The source and drain regions 70a and 70b are made of a second conductivity type (for example, N-type) impurity region.

  The silicide layer 80 is formed on the source and drain regions 70a and 70b. The silicide layer 80 can also be formed on the gate electrode 50. The silicide layer 80 is made of, for example, a compound of silicon and metal. More specifically, the silicide layer 80 is made of, for example, tungsten silicide, molybdenum silicide, titanium silicide, cobalt silicide, nickel silicide, or the like. The silicide layer 80 can reduce the contact resistance between the source and drain regions 70a and 70b and the wiring layer (not shown).

(2) Second Element Formation Region In the second element formation region 2, a resistor 2R is formed as shown in FIG. The resistor 2 </ b> R includes a resistance layer 30, an insulating layer 40, a conductive layer 50, a sidewall 60, and a silicide layer 80. The insulating layer 40, the sidewall 60, and the silicide layer 80 are made of the materials described in the description of the MOS transistor 1T.

  The resistance layer 30 is formed on the semiconductor substrate 10. The resistance layer 30 is made of, for example, an N-type impurity region.

  The insulating layer 40 is formed on the resistance layer 30. The insulating layer 40 can insulate the resistance layer 30 and the conductive layer 50.

  The conductive layer 50 is formed on the insulating layer 40. The conductive layer 50 is made of the same material as the gate electrode 50 of the MOS transistor 1T. Therefore, the conductive layer 50 and the gate electrode 50 can be formed simultaneously. The conductive layer 50 is made of, for example, polysilicon. The conductive layer 50 can prevent a silicide layer from being formed in a region other than the predetermined region on the resistance layer 30. In other words, the conductive layer 50 allows the resistance layer 30 to selectively form a silicide layer in a predetermined region. If a silicide layer is formed in a region other than the predetermined region on the resistance layer 30, the resistance layer 30 may not be used as a high resistance layer.

  The side wall 60 is formed on the side wall of the conductive layer 50. The sidewall 60 can reliably insulate the silicide layer 80 formed on the resistance layer 30 from the conductive layer 50.

  The silicide layer 80 is formed on the resistance layer 30. The silicide layer 80 can also be formed on the conductive layer 50. The silicide layer 80 can reduce contact resistance between the resistance layer 30 and a wiring layer (not shown).

1.2. Semiconductor Device Manufacturing Method According to First Embodiment Next, a semiconductor device manufacturing method according to the first embodiment will be described with reference to the drawings. 2 to 4 are cross-sectional views schematically showing the manufacturing process of the semiconductor device 100 according to the first embodiment.

  As shown in FIG. 2, the element isolation layer 20 is formed on the semiconductor substrate 10. The element isolation layer 20 is formed by, for example, the LOCOS method. That is, for example, a silicon nitride film (not shown) is formed on the semiconductor substrate 10, the silicon nitride film is patterned into a predetermined shape, and then thermally oxidized.

  As shown in FIG. 3, for example, an N-type impurity is implanted into the semiconductor substrate 10 in the second element formation region 2 to form the resistance layer 30. The impurity is implanted, for example, using a resist layer (not shown) as a mask. The resistance of the resistance layer 30 can be adjusted by the amount and type of impurities.

  As shown in FIG. 4, an insulating layer 40 is formed on the semiconductor substrate 10 in the first element formation region 1 and on the resistance layer 30 in the second element formation region 2. Then, simultaneously with forming the gate electrode 50 on the insulating layer 40 in the first element formation region 1, the conductive layer 50 is formed on the insulating layer 40 in the second element formation region 2. Specifically, first, for example, an oxide film (not shown) is formed on the semiconductor substrate 10. The oxide film is formed by, for example, a thermal oxidation method. Next, for example, a polysilicon layer (not shown) is formed on the entire surface, and a resist layer (not shown) having a predetermined pattern is formed on the polysilicon layer. Next, the polysilicon layer is patterned using the resist layer as a mask. Next, for example, a part of the oxide film is wet-etched using a polysilicon layer as a mask to expose the semiconductor substrate 10 in the first element formation region 1 and the resistance layer 30 in the second element formation region 2. Thus, the insulating layer 40 made of an oxide film, and the gate electrode 50 and the conductive layer 50 made of a polysilicon layer can be formed.

  As shown in FIG. 4, sidewalls 60 are formed on the sidewalls of the gate electrode 50 in the first element formation region 1 and the sidewalls of the conductive layer 50 in the second element formation region 2. The sidewall 60 is formed, for example, by forming an oxide film (not shown) on the entire surface and then etching back by dry etching.

  As shown in FIG. 4, for example, N-type impurities are implanted into the semiconductor substrate 10 exposed in the first element formation region 1 to form source and drain regions 70a and 70b. The impurity is implanted, for example, using a resist layer (not shown) as a mask.

  As shown in FIG. 1, a silicide layer 80 is formed on the source and drain regions 70a and 70b and on the exposed resistance layer 30 of the second element formation region 2. Furthermore, a silicide layer 80 can be formed on the gate electrode 50 in the first element formation region 1 and on the conductive layer 50 in the second element formation region 2. Specifically, the silicide layer 80 forms a metal layer (not shown) on the entire surface, and then heat-treats to react the metal layer with, for example, silicon contained in the resistance layer 30 or the like. Can be formed.

  Through the above steps, the semiconductor device 100 can be manufactured.

  The manufacturing method of the semiconductor device 100 has the following features, for example.

  In the method for manufacturing the semiconductor device 100, the gate electrode 50 in the first element formation region 1 and the conductive layer 50 in the second element formation region 2 can be formed simultaneously. The silicide layer 80 can be selectively formed in a predetermined region on the resistance layer 30 by the conductive layer 50. That is, in the method for manufacturing the semiconductor device 100, a predetermined region on the resistance layer 30 can be selectively salicided by a simple process without adding a special process.

  In the method for manufacturing the semiconductor device 100, the sidewall 60 can be formed on the sidewall of the gate electrode 50 in the first element formation region 1 and the sidewall of the conductive layer 50 in the second element formation region 2. Therefore, the silicide layer 80 formed on the resistance layer 30 and the conductive layer 50 can be reliably insulated.

2. Second Embodiment 2.1. Semiconductor Device According to Second Embodiment FIG. 5 is a cross-sectional view schematically showing a semiconductor device 200 according to the second embodiment. Hereinafter, in the semiconductor device 200 according to the second embodiment, members having the same functions as those of the constituent members of the semiconductor device 100 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. .

  In the semiconductor device 200, as shown in FIG. 5, the element isolation layer 20 is formed on the semiconductor substrate 10 in the second element formation region 2. Furthermore, the element isolation layer 20 defines the first element formation region 1. In the second element formation region 2, a resistor 200R is formed.

  The resistor 200R has a resistance layer 230. The resistance layer 230 is formed on the element isolation layer 20 in the second element formation region 2. The resistance layer 230 is made of, for example, polysilicon into which impurities are implanted.

2.2. Semiconductor Device Manufacturing Method According to Second Embodiment Next, a semiconductor device manufacturing method according to the second embodiment will be described. FIG. 6 is a cross-sectional view schematically showing the manufacturing process of the semiconductor device 200 according to the second embodiment. Hereinafter, in the method for manufacturing the semiconductor device 200 according to the second embodiment, members having the same functions as the constituent members of the method for manufacturing the semiconductor device 100 according to the first embodiment are denoted by the same reference numerals, Detailed description is omitted.

  As shown in FIG. 6, the resistance layer 230 is formed on the element isolation layer 20 in the second element formation region 2. Specifically, first, a low resistance layer (not shown) is formed on the entire surface. Next, for example, impurities are implanted into the low resistance layer to form a high resistance layer. Then, a resist layer (not shown) having a predetermined pattern is formed on the high resistance layer, and is patterned using the resist layer as a mask. Thus, the resistance layer 230 can be formed. More specifically, the low resistance layer can be made of polysilicon. That is, the resistance layer 230 can be formed by implanting impurities into polysilicon.

  In the method for manufacturing the semiconductor device 200, as in the method for manufacturing the semiconductor device 100, a predetermined region on the resistance layer 230 can be selectively salicided by a simple process without adding a special process.

  Although the embodiments of the present invention have been described in detail as described above, those skilled in the art will readily understand that many modifications are possible without substantially departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention.

1 is a cross-sectional view schematically showing a semiconductor device according to a first embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on 1st Embodiment. Sectional drawing which shows typically the semiconductor device which concerns on 2nd Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on 2nd Embodiment.

Explanation of symbols

1 first element formation region, 1T MOS transistor, 2 second element formation region,
2R resistor, 10 semiconductor substrate, 20 element isolation layer, 30 resistor layer, 40 insulating layer,
50 gate electrode, 50 conductive layer, 60 sidewall,
70a, 70b source region and drain region, 80 silicide layer,
100 semiconductor device, 200 semiconductor device, 200R resistance, 230 resistance layer

Claims (9)

A method of manufacturing a semiconductor device having a first element formation region and a second element formation region,
Forming a resistance layer in the second element formation region;
Forming an insulating layer above the semiconductor substrate in the first element formation region and above the resistance layer in the second element formation region;
Forming a gate electrode above the insulating layer in the first element forming region and simultaneously forming a conductive layer above the insulating layer in the second element forming region;
Removing a part of the insulating layer to expose the semiconductor substrate in the first element formation region and the resistance layer in the second element formation region;
Implanting impurities into the semiconductor substrate exposed in the first element formation region to form a source region and a drain region;
Forming a silicide layer on the source region and the drain region and on the exposed resistance layer of the second element formation region;
A method for manufacturing a semiconductor device, comprising: In claim 1,
The step of forming the resistance layer includes
A method of manufacturing a semiconductor device, wherein the resistance layer is formed by implanting impurities into the semiconductor substrate in the second element formation region. In claim 2,
Furthermore, the manufacturing method of a semiconductor device which has the process of forming the element isolation layer which divides the said 1st element formation area and the said 2nd element formation area. In claim 1,
The step of forming the resistance layer includes
By forming a low resistance layer having a lower resistance than the resistance layer above the semiconductor substrate in the second element formation region, and implanting impurities into the low resistance layer to increase the resistance, the resistance layer A method of manufacturing a semiconductor device. In claim 4,
The method of manufacturing a semiconductor device, wherein the low resistance layer is made of polysilicon. In claim 4 or 5,
And a step of forming an element isolation layer on the semiconductor substrate in the second element formation region,
The element isolation layer is formed to partition the first element formation region,
The method of manufacturing a semiconductor device, wherein the resistance layer is formed on the element isolation layer in the second element formation region. In any one of Claims 1 thru | or 6.
Furthermore, the manufacturing method of a semiconductor device which has the process of forming a side wall in the side wall of the said gate electrode and the said conductive layer. In any one of Claims 1 thru | or 7,
The method for manufacturing a semiconductor device, wherein the gate electrode and the conductive layer are made of polysilicon. A semiconductor device having a first element formation region and a second element formation region,
A semiconductor substrate;
A resistance layer formed in the second element formation region;
An insulating layer formed above the semiconductor substrate in the first element formation region and above the resistance layer in the second element formation region;
A gate electrode formed above the insulating layer in the first element formation region;
A conductive layer formed above the insulating layer in the second element formation region;
A source region and a drain region formed in the semiconductor substrate in the first element formation region;
A silicide layer formed on the source region and the drain region, and on the resistance layer of the second element formation region;
Including
The semiconductor device, wherein the gate electrode and the conductive layer are made of the same material.

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