KR20080094501A - Semiconductor device and method for forming of the same - Google Patents
Semiconductor device and method for forming of the same Download PDFInfo
- Publication number
- KR20080094501A KR20080094501A KR1020070039017A KR20070039017A KR20080094501A KR 20080094501 A KR20080094501 A KR 20080094501A KR 1020070039017 A KR1020070039017 A KR 1020070039017A KR 20070039017 A KR20070039017 A KR 20070039017A KR 20080094501 A KR20080094501 A KR 20080094501A
- Authority
- KR
- South Korea
- Prior art keywords
- region
- groove
- film
- gate
- forming
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 title claims description 24
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 229920005591 polysilicon Polymers 0.000 claims abstract description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 12
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 19
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 230000001965 increasing effect Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 230000001939 inductive effect Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005304 joining Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The semiconductor device has a gate forming region and an LDD forming region and a junction forming region disposed at both sides of the gate forming region, wherein a first groove is formed in the junction forming region, and a depth shallower than the first groove in the LDD forming region. A semiconductor substrate having a second groove formed thereon; An LDD region formed to fill the second groove and formed of a low concentration polysilicon film; A tension film formed on a surface of the first groove such that tensile stress is induced in a channel portion corresponding to the gate formation region; A junction region formed to bury the first groove including the tensile film and made of a high concentration polysilicon film; And a gate formed on the gate formation region of the semiconductor substrate.
Description
1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.
2A to 2E are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention.
Explanation of symbols on the main parts of the drawings
100
106: low concentration polysilicon film 108: silicon nitride film
110: low concentration polysilicon film 112: gate insulating film
114: metal film 116: hard mask film
118: gate
T: 1st groove T ': 2nd groove
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same, which can increase the mobility of charge by inducing a tensile stress in a channel portion of the semiconductor device. will be.
With advances in semiconductor technology, high speed and high integration of semiconductor devices are rapidly progressing, and accordingly, demands for semiconductor devices for miniaturization of patterns and high precision of pattern dimensions are increasing.
In addition, the transistors formed in the semiconductor devices are highly demanded for low power and high speed operation due to the high integration of the semiconductor devices, and thus, strained silicon capable of increasing the mobility of charge in the channel portion of the semiconductor devices is increased. The structure was developed.
Generally, the manufacturing method of the semiconductor element of a strained silicon structure is advanced by the following method.
First, a first film having a lattice constant greater than that of silicon is formed on a semiconductor substrate made of silicon having a certain lattice constant.
Then, a silicon layer is formed on the first layer so that the concentration of silicon is gradually increased again to form a strained silicon layer having a higher lattice constant than the silicon layer constituting the semiconductor substrate, that is, the lattice spacing is wider. do.
Subsequently, after forming an isolation layer on the semiconductor substrate on which the strained silicon is formed, the strained silicon layer is etched to expose the source / drain junction region, and an epitaxial layer is formed on the etched region.
Thereafter, the strained silicon layer is stressed by the growth of the epitaxial layer, and the lattice structure of the strained silicon layer is deformed by heterojunction with the epitaxial layer, thereby forming a strained channel having a larger lattice spacing. Then, the fabrication of the semiconductor device of the strained silicon structure is completed.
In the semiconductor device of the strained silicon structure, the strained silicon layer is stressed by the epitaxial layer and forms a strained channel having a larger lattice spacing, thereby moving the silicon layer in which the mobility of charge moving through the channel is common. Since it has a larger value than the charge, the mobility of the charge is increased.
However, the above-described strained silicon structure is complicated because the source / drain junction region is formed by removing the junction region in the form of a recess and growing an epitaxial layer in the region.
The present invention provides a semiconductor device and a method of manufacturing the same, which can increase the mobility of charge by inducing a tensile stress in the channel portion of the semiconductor device.
A semiconductor device according to the present invention has a gate forming region and an LDD forming region and a junction forming region disposed on both sides of the gate forming region, wherein a first groove is formed in the junction forming region, and the first region is formed in the LDD forming region. A semiconductor substrate having a second groove having a depth smaller than that of the groove; An LDD region formed to fill the second groove and formed of a low concentration polysilicon film; A tension film formed on a surface of the first groove such that tensile stress is induced in a channel portion corresponding to the gate formation region; A joining region formed to fill the first groove including the tensile film, and formed of a high concentration polysilicon film; And a gate formed on the gate formation region of the semiconductor substrate.
The tensile film is characterized by having a thickness of 50 ~ 100∼.
The tensile film is characterized in that the silicon nitride film.
In addition, in the method of manufacturing a semiconductor device according to the present invention, a first groove is formed by selectively etching the junction formation region of a semiconductor substrate having a gate formation region, an LDD formation region disposed on both sides of the gate formation region, and a junction formation region. Forming; Selectively etching the LDD formation region of the semiconductor substrate to form a second groove having a depth lower than the first groove; Selectively forming a low concentration polysilicon film to fill the second groove to form an LDD region; Selectively forming a tensile film on a surface of the first groove such that a tensile stress is induced in a channel portion corresponding to the gate formation region; Selectively forming a high concentration polysilicon film to fill the first groove including the tensile film to form a junction region; And forming a gate on the gate formation region of the semiconductor substrate.
Selective etching of the junction formation region and the LDD region of the semiconductor substrate may be performed using a nitride film as an etching mask.
The tensile film is characterized by having a thickness of 50 ~ 100∼.
The tensile film is formed of a silicon nitride film.
After forming the gate, the method further comprises the step of performing an ion implantation process to increase the doping concentration of the junction region.
(Example)
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
According to the present invention, a groove is formed by recessing a junction region of a semiconductor substrate active region, and a silicon nitride film is formed on the surface of the groove with a thin thickness to directly induce tensile stress in the channel portion of the semiconductor device. Can effectively increase the mobility of the charge.
In addition, as in the conventional strained silicon structure, the junction region may be formed of a high concentration polysilicon film without a complicated process such as the growth of the epitaxial layer, and thus the junction region may be formed by a simple method.
Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described.
1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.
As shown, an LDD formation region and a junction formation region are formed in the active region of the
Therefore, by forming a thin
2A through 2E are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention.
Referring to FIG. 2A, a
Thereafter, a first mask pattern is formed in the active region of the
Referring to FIG. 2B, after the first nitride layer 204 is removed, a second mask pattern for exposing the LDD formation region to the
Referring to FIG. 2C, the
Referring to FIG. 2D, the
Thereafter, a high
Here, the
Referring to FIG. 2E, after the
Here, an ion implantation process may be additionally performed to increase the concentration of the high
As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.
As described above, the present invention recesses the junction region of the semiconductor substrate active region to form a groove, and forms a silicon nitride film with a thin thickness on the surface of the groove directly to the tensile stress in the channel portion of the semiconductor device (Tensile stress) ), It can effectively increase the mobility of the charge.
In addition, as in the conventional strained silicon structure, the junction region may be formed of a high concentration polysilicon film without a complicated process such as the growth of the epitaxial layer, and thus the junction region may be formed by a simple method.
Claims (8)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070039017A KR20080094501A (en) | 2007-04-20 | 2007-04-20 | Semiconductor device and method for forming of the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070039017A KR20080094501A (en) | 2007-04-20 | 2007-04-20 | Semiconductor device and method for forming of the same |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20080094501A true KR20080094501A (en) | 2008-10-23 |
Family
ID=40154675
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020070039017A KR20080094501A (en) | 2007-04-20 | 2007-04-20 | Semiconductor device and method for forming of the same |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20080094501A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100934789B1 (en) * | 2007-08-29 | 2009-12-31 | 주식회사 동부하이텍 | Semiconductor device and manufacturing method thereof |
-
2007
- 2007-04-20 KR KR1020070039017A patent/KR20080094501A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100934789B1 (en) * | 2007-08-29 | 2009-12-31 | 주식회사 동부하이텍 | Semiconductor device and manufacturing method thereof |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9589848B2 (en) | FinFET structures having silicon germanium and silicon channels | |
KR101537079B1 (en) | A transistor with an embedded strain inducing material having a gradually shaped configuration | |
US7531438B2 (en) | Method of fabricating a recess channel transistor | |
KR101229186B1 (en) | Finfets with multiple fin heights | |
JP5107680B2 (en) | Semiconductor device | |
US8183640B2 (en) | Method of fabricating transistors and a transistor structure for improving short channel effect and drain induced barrier lowering | |
JP2006019727A (en) | Strained p-type metal oxide semiconductor field effect transistor (mosfet) structure having slanted, incorporated silicon-germanium source-drain and/or extension, and manufacturing method for the same | |
JP2006303501A (en) | STEP-EMBEDDED SiGe STRUCTURE WITH ENHANCED PFET MOBILITY | |
US8097517B2 (en) | Method for manufacturing semiconductor device with improved short channel effect of a PMOS and stabilized current of a NMOS | |
US8431460B2 (en) | Method for fabricating semiconductor device | |
CN102709250B (en) | Semiconductor device manufacturing method utilizing stress memorization technology | |
CN102709249B (en) | Manufacturing method for semi-conductor appliance through application of stress memory technology | |
KR100525960B1 (en) | Method of forming semiconductor device | |
KR20080094501A (en) | Semiconductor device and method for forming of the same | |
US10366991B1 (en) | Semiconductor device and manufacturing method thereof | |
KR20100089364A (en) | Method of fabricating a semiconductor device having a transistor | |
JP2009016423A (en) | Semiconductor device and manufacturing method thereof | |
KR100673104B1 (en) | Method for forming transistor of semiconductor devices | |
KR101068137B1 (en) | Method for manufacturing high voltage transistor | |
KR100557967B1 (en) | Method of manufacturing semiconductor device | |
US20120315734A1 (en) | Method for fabricating semiconductor device | |
KR101194742B1 (en) | Method for forming semiconductor device | |
CN104022081A (en) | Method for manufacturing semiconductor device | |
KR20090025843A (en) | Semiconductor device and method for manufacturing the same | |
CN112201625A (en) | Method for forming source-drain region epitaxial layer of semiconductor device and semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WITN | Withdrawal due to no request for examination |