KR20080094501A - Semiconductor device and method for forming of the same - Google Patents

Semiconductor device and method for forming of the same Download PDF

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Publication number
KR20080094501A
KR20080094501A KR1020070039017A KR20070039017A KR20080094501A KR 20080094501 A KR20080094501 A KR 20080094501A KR 1020070039017 A KR1020070039017 A KR 1020070039017A KR 20070039017 A KR20070039017 A KR 20070039017A KR 20080094501 A KR20080094501 A KR 20080094501A
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KR
South Korea
Prior art keywords
region
groove
film
gate
forming
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KR1020070039017A
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Korean (ko)
Inventor
이태훈
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020070039017A priority Critical patent/KR20080094501A/en
Publication of KR20080094501A publication Critical patent/KR20080094501A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The semiconductor device has a gate forming region and an LDD forming region and a junction forming region disposed at both sides of the gate forming region, wherein a first groove is formed in the junction forming region, and a depth shallower than the first groove in the LDD forming region. A semiconductor substrate having a second groove formed thereon; An LDD region formed to fill the second groove and formed of a low concentration polysilicon film; A tension film formed on a surface of the first groove such that tensile stress is induced in a channel portion corresponding to the gate formation region; A junction region formed to bury the first groove including the tensile film and made of a high concentration polysilicon film; And a gate formed on the gate formation region of the semiconductor substrate.

Description

Semiconductor device and method for manufacturing the same {Semiconductor device and method for forming of the same}

1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

2A to 2E are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 102 device isolation film

106: low concentration polysilicon film 108: silicon nitride film

110: low concentration polysilicon film 112: gate insulating film

114: metal film 116: hard mask film

118: gate

T: 1st groove T ': 2nd groove

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same, which can increase the mobility of charge by inducing a tensile stress in a channel portion of the semiconductor device. will be.

With advances in semiconductor technology, high speed and high integration of semiconductor devices are rapidly progressing, and accordingly, demands for semiconductor devices for miniaturization of patterns and high precision of pattern dimensions are increasing.

In addition, the transistors formed in the semiconductor devices are highly demanded for low power and high speed operation due to the high integration of the semiconductor devices, and thus, strained silicon capable of increasing the mobility of charge in the channel portion of the semiconductor devices is increased. The structure was developed.

Generally, the manufacturing method of the semiconductor element of a strained silicon structure is advanced by the following method.

First, a first film having a lattice constant greater than that of silicon is formed on a semiconductor substrate made of silicon having a certain lattice constant.

Then, a silicon layer is formed on the first layer so that the concentration of silicon is gradually increased again to form a strained silicon layer having a higher lattice constant than the silicon layer constituting the semiconductor substrate, that is, the lattice spacing is wider. do.

Subsequently, after forming an isolation layer on the semiconductor substrate on which the strained silicon is formed, the strained silicon layer is etched to expose the source / drain junction region, and an epitaxial layer is formed on the etched region.

Thereafter, the strained silicon layer is stressed by the growth of the epitaxial layer, and the lattice structure of the strained silicon layer is deformed by heterojunction with the epitaxial layer, thereby forming a strained channel having a larger lattice spacing. Then, the fabrication of the semiconductor device of the strained silicon structure is completed.

In the semiconductor device of the strained silicon structure, the strained silicon layer is stressed by the epitaxial layer and forms a strained channel having a larger lattice spacing, thereby moving the silicon layer in which the mobility of charge moving through the channel is common. Since it has a larger value than the charge, the mobility of the charge is increased.

However, the above-described strained silicon structure is complicated because the source / drain junction region is formed by removing the junction region in the form of a recess and growing an epitaxial layer in the region.

The present invention provides a semiconductor device and a method of manufacturing the same, which can increase the mobility of charge by inducing a tensile stress in the channel portion of the semiconductor device.

A semiconductor device according to the present invention has a gate forming region and an LDD forming region and a junction forming region disposed on both sides of the gate forming region, wherein a first groove is formed in the junction forming region, and the first region is formed in the LDD forming region. A semiconductor substrate having a second groove having a depth smaller than that of the groove; An LDD region formed to fill the second groove and formed of a low concentration polysilicon film; A tension film formed on a surface of the first groove such that tensile stress is induced in a channel portion corresponding to the gate formation region; A joining region formed to fill the first groove including the tensile film, and formed of a high concentration polysilicon film; And a gate formed on the gate formation region of the semiconductor substrate.

The tensile film is characterized by having a thickness of 50 ~ 100∼.

The tensile film is characterized in that the silicon nitride film.

In addition, in the method of manufacturing a semiconductor device according to the present invention, a first groove is formed by selectively etching the junction formation region of a semiconductor substrate having a gate formation region, an LDD formation region disposed on both sides of the gate formation region, and a junction formation region. Forming; Selectively etching the LDD formation region of the semiconductor substrate to form a second groove having a depth lower than the first groove; Selectively forming a low concentration polysilicon film to fill the second groove to form an LDD region; Selectively forming a tensile film on a surface of the first groove such that a tensile stress is induced in a channel portion corresponding to the gate formation region; Selectively forming a high concentration polysilicon film to fill the first groove including the tensile film to form a junction region; And forming a gate on the gate formation region of the semiconductor substrate.

Selective etching of the junction formation region and the LDD region of the semiconductor substrate may be performed using a nitride film as an etching mask.

The tensile film is characterized by having a thickness of 50 ~ 100∼.

The tensile film is formed of a silicon nitride film.

After forming the gate, the method further comprises the step of performing an ion implantation process to increase the doping concentration of the junction region.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, a groove is formed by recessing a junction region of a semiconductor substrate active region, and a silicon nitride film is formed on the surface of the groove with a thin thickness to directly induce tensile stress in the channel portion of the semiconductor device. Can effectively increase the mobility of the charge.

In addition, as in the conventional strained silicon structure, the junction region may be formed of a high concentration polysilicon film without a complicated process such as the growth of the epitaxial layer, and thus the junction region may be formed by a simple method.

Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described.

1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

As shown, an LDD formation region and a junction formation region are formed in the active region of the semiconductor substrate 100 on which the device isolation layer 102 defining the active region is formed, and on both sides of the gate formation region. A first groove T is formed in the formation region, and a second groove T 'having a shallower depth than the first groove is formed in the LDD formation region. In addition, an LDD region is formed in the low concentration polysilicon layer 106 so that the second groove T 'is filled in the second groove T', and the surface of the first groove T is formed in the second groove T '. A silicon nitride film 108 having a thickness of 50 to 100 GPa is formed as a tensile film so that tensile stress is induced in the channel portion of the gate. In addition, a junction region formed of a high concentration polysilicon layer 110 is formed on the silicon nitride layer 108 of the first groove T so that the first groove T is buried. A gate 118 formed of a gate insulating film 112, a metal based film 114, and a hard mask film 116 is formed.

Therefore, by forming a thin silicon nitride film 108 directly in the junction region in order to apply tensile stress to the gate channel portion of the semiconductor device, it is possible to effectively induce tensile stress, and epitaxial layer for inducing conventional tensile stress It is possible to form the LDD region and the junction region in a simple manner without the need to proceed to a complicated process such as forming a junction region.

2A through 2E are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, a device isolation film 202 is formed on a semiconductor substrate 200 to define an active region having a gate forming region, an LDD forming region disposed on both sides of the gate forming region, and a junction forming region. do.

Thereafter, a first mask pattern is formed in the active region of the semiconductor substrate 200 to expose the junction formation region with the first nitride layer 204a, and then the exposed semiconductor is formed using the first nitride layer 204a as an etch mask. The first groove T is formed by etching the junction formation region of the substrate 200 to a predetermined depth.

Referring to FIG. 2B, after the first nitride layer 204 is removed, a second mask pattern for exposing the LDD formation region to the second nitride layer 204b is formed in an active region of the semiconductor substrate 200. A second groove T 'is formed by etching the LDD formation region of the exposed semiconductor substrate 100 to a depth smaller than the depth of the first groove T by using the second nitride film 204b as an etching mask. do.

Referring to FIG. 2C, the semiconductor substrate 200 including the first groove T and the second groove T 'is doped at a low concentration so that the second groove T', which is the LDD formation region, is buried in the semiconductor substrate 200. After the low concentration polysilicon layer 206 is formed, the LDD region is formed by removing the low concentration polysilicon layer 206 of the region of the semiconductor substrate 200 except for the second groove T ′.

Referring to FIG. 2D, the silicon nitride film 208 may be formed on the semiconductor substrate 200 including the low concentration polysilicon film 206 and the first groove T formed in the second groove T ′. After forming the silicon nitride film 208 on the semiconductor substrate 200 except for the silicon nitride film 108 formed on the surface of the first groove (T).

Thereafter, a high concentration polysilicon film 210 having a higher doping concentration than the low concentration polysilicon film 206 is formed on the semiconductor substrate 200 including the low concentration polysilicon film 206 and the silicon nitride film 208. The junction region is formed by removing the high concentration polysilicon film 110 of the remaining portions except for the first groove T region, which is the junction formation region.

Here, the silicon nitride film 208 serves as a tensile film that induces a tensile stress in the channel portion corresponding to the gate formation region of the semiconductor substrate 200 formed by a subsequent process.

Referring to FIG. 2E, after the gate insulating film 212, the gate conductive film 214, and the hard mask film 216 are formed on the semiconductor substrate 200, an etching process is performed to form the gate 218. Complete the manufacture of the device.

Here, an ion implantation process may be additionally performed to increase the concentration of the high concentration polysilicon film 110 inside the first groove T, that is, the source (S) / drain (D) junction region.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention recesses the junction region of the semiconductor substrate active region to form a groove, and forms a silicon nitride film with a thin thickness on the surface of the groove directly to the tensile stress in the channel portion of the semiconductor device (Tensile stress) ), It can effectively increase the mobility of the charge.

In addition, as in the conventional strained silicon structure, the junction region may be formed of a high concentration polysilicon film without a complicated process such as the growth of the epitaxial layer, and thus the junction region may be formed by a simple method.

Claims (8)

A gate forming region and an LDD forming region and a junction forming region disposed at both sides of the gate forming region, wherein a first groove is formed in the junction forming region, and a second groove having a depth shallower than the first groove in the LDD forming region; A formed semiconductor substrate; An LDD region formed to fill the second groove and formed of a low concentration polysilicon film; A tension film formed on a surface of the first groove such that tensile stress is induced in a channel portion corresponding to the gate formation region; A junction region formed to bury the first groove including the tensile film and made of a high concentration polysilicon film; And A gate formed on a gate formation region of the semiconductor substrate; A semiconductor device comprising a. The method of claim 1, The tensile film has a thickness of 50 to 100 GPa semiconductor device. The method of claim 1, The tensile film is a semiconductor device, characterized in that the silicon nitride film. Selectively etching the junction formation region of the semiconductor substrate having a gate formation region, an LDD formation region and a junction formation region disposed on both sides of the gate formation region to form a first groove; Selectively etching the LDD formation region of the semiconductor substrate to form a second groove having a depth lower than the first groove; Selectively forming a low concentration polysilicon film to fill the second groove to form an LDD region; Selectively forming a tensile film on a surface of the first groove such that a tensile stress is induced in a channel portion corresponding to the gate formation region; Selectively forming a high concentration polysilicon film to fill the first groove including the tensile film to form a junction region; And Forming a gate on a gate formation region of the semiconductor substrate; Method of manufacturing a semiconductor device comprising a. The method of claim 4, wherein The selective etching of the junction formation region and the LDD region of the semiconductor substrate is performed using a nitride film as an etching mask. The method of claim 4, wherein The tensile film has a thickness of 50 to 100 GPa. The method of claim 4, wherein The tensile film is a method of manufacturing a semiconductor device, characterized in that formed of a silicon nitride film. The method of claim 4, wherein And after the forming of the gate, performing an ion implantation process to increase the doping concentration of the junction region.
KR1020070039017A 2007-04-20 2007-04-20 Semiconductor device and method for forming of the same KR20080094501A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100934789B1 (en) * 2007-08-29 2009-12-31 주식회사 동부하이텍 Semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100934789B1 (en) * 2007-08-29 2009-12-31 주식회사 동부하이텍 Semiconductor device and manufacturing method thereof

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