CN102709249B - Manufacturing method for semi-conductor appliance through application of stress memory technology - Google Patents
Manufacturing method for semi-conductor appliance through application of stress memory technology Download PDFInfo
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- CN102709249B CN102709249B CN201210208906.3A CN201210208906A CN102709249B CN 102709249 B CN102709249 B CN 102709249B CN 201210208906 A CN201210208906 A CN 201210208906A CN 102709249 B CN102709249 B CN 102709249B
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Abstract
The invention discloses a manufacturing method for a semi-conductor appliance through an application of a stress memory technology, a secondary side wall film layer on a zone which needs to form metal silicide is etched, so as to form the secondary side wall on the side wall of a grid electrode structure on the zone which needs to form metal silicide, the secondary side wall is directly utilized as a stop layer self-aiming at metal silicide, and a metal silicide layer is formed on an exposed source/drain zone and the grid electrode structure, thus the process step is simplified; further, the secondary side wall is removed after the metal silicide layer is formed, by the adoption of the stress neighborhood effect, the contact etch stop layer (CESL) stress layer is closer to a channel, and the performance of the appliance is promoted; and additionally, amorphous carbon is utilized for the first side wall and the secondary side wall provided by the manufacturing method, and an ashing process can be applied to removing the primary side wall and the secondary side wall, and the primary side wall and the secondary side wall are conveniently removed.
Description
Technical field
The present invention relates to integrated circuit and manufacture field, the particularly method, semi-conductor device manufacturing method of a kind of applied stress memory technique (SMT).
Background technology
Along with the development of cmos semiconductor device technology and in proportion size dwindle, stress engineering is playing increasing effect aspect semiconductor technology and device performance; In cmos device, introduce stress, mainly in order to improve device carrier mobility, useful to NMOS electron mobility at the upper tensile stress of cmos device channel direction (longitudinal), and compression is useful to PMOS hole mobility, tensile stress in channel width dimension (transverse) is all useful to the carrier mobility of NMOS and PMOS device, and useful to nmos device electron mobility in the compression of vertical-channel in-plane (out-of-plane), tensile stress is useful to PMOS device hole mobility.
Stress memory effect (SMT, Stress memorization technique) be a kind of introduce stress in CMOS technique method, its technological process is: after device source/leakage is injected, deposition one deck silicon nitride film protective layer (cap layer), and then carry out source/leakage annealing, in source/leakage annealing process, can produce silicon nitride film protective layer, thermal stress between polysilicon gate and side wall and internal stress effect, these stress can be by memory among polysilicon gate, in polysilicon, can produce tensile stress along vertical-channel in-plane (out-of-plane), and channel direction (longitudinal) can produce compression, in ensuing technique, silicon nitride film protective layer is etched away, but the stress of memory in polysilicon gate, still can be transmitted among the raceway groove of cmos semiconductor device, be transmitted to stress in raceway groove and be the tensile stress on compression and the channel direction (longitudinal) of vertical-channel in-plane (out-of-plane), can be drawn the impact of cmos device carrier mobility by above-mentioned stress, such stress effect is useful to improving nmos device electron mobility, can improve nmos device performance.
Detailed, prior art is introduced the common side wall moulding of method and the secondary side wall moulding process of stress in CMOS technique.Wherein, a side wall moulding process specifically comprises: 1) on substrate, form grid structure and carry out lightly doped drain injection; 2) on substrate and grid structure, carry out amorphous carbon deposition; 3) thus dry etching amorphous carbon form a side wall; 4) on substrate and a side wall, carry out silicon nitride film deposition to form silicon nitride protective layer, described silicon nitride protective layer, in order to as protection amorphous carbon, carries out subsequently S/D Implantation and forms source/drain region; 5) adopt dry method or wet processing to remove silicon nitride protective layer; 6) adopt cineration technics to remove a side wall of amorphous carbon material; 7) on substrate and grid structure, deposit stressed silicon nitride layers, and carry out annealing in process; 8) adopt dry method or wet processing to remove stressed silicon nitride layers, so far completed side wall moulding process one time.But, in existing secondary side wall moulding process, need to deposit again skim material fit dry etching and form secondary side wall, and then the auxiliary metal silicide layer (silicide) that forms in formation self-aligned metal silicate barrier layer, the forming process of whole metal silicide layer is more loaded down with trivial details, still has the space of optimizing.
Summary of the invention
The invention provides a kind of method, semi-conductor device manufacturing method of applied stress memory technique, to solve the loaded down with trivial details problem of existing manufacturing approach craft.
For solving the problems of the technologies described above, the invention provides a kind of method, semi-conductor device manufacturing method of applied stress memory technique, comprising:
On substrate, form grid structure and carry out lightly doped drain injection;
On described substrate and grid structure, form side wall thin layer one time;
Described in etching, a side wall thin layer is to form a side wall at described grid structure sidewall;
Carry out source/leakage Implantation and form source/drain region;
Remove a described side wall;
On described substrate and grid structure, form stressor layers, and carry out annealing in process;
Remove described stressor layers;
On described substrate and grid structure, form secondary side wall thin layer;
Etching need form the secondary side wall thin layer in metal silicide region, to form secondary side wall at the described grid structure sidewall that needs to form in metal silicide region;
On the source/drain region exposing and grid structure, form metal silicide layer.
Optionally, in the method, semi-conductor device manufacturing method of described applied stress memory technique, form metal silicide layer on the source/drain region exposing and grid structure after, also comprise: remove described secondary side wall; On described substrate and grid structure, form CESL stressor layers.
Optionally, in the method, semi-conductor device manufacturing method of described applied stress memory technique, described CESL stressor layers is stress silicon nitride.
Optionally, in the method, semi-conductor device manufacturing method of described applied stress memory technique, before carrying out source/leakage Implantation formation source/drain region, also comprise: on described substrate and a side wall, form side wall protective layer one time.
Optionally, in the method, semi-conductor device manufacturing method of described applied stress memory technique, after carrying out source/leakage Implantation formation source/drain region, also comprise: remove a described side wall protective layer.
Optionally, in the method, semi-conductor device manufacturing method of described applied stress memory technique, a described side wall thin layer is amorphous carbon, and a described side wall protective layer is silicon nitride.
Optionally; in the method, semi-conductor device manufacturing method of described applied stress memory technique; before the described grid structure sidewall that needs to form in metal silicide region forms secondary side wall, also comprise: on described secondary side wall thin layer, form secondary side wall protective layer.
Optionally, in the method, semi-conductor device manufacturing method of described applied stress memory technique, described substrate comprises that need form metal silicide region and without forming metal silicide region, the step that etching need form the secondary side wall thin layer in metal silicide region comprises: on described substrate, form photoresist layer; Utilize exposure and developing process to remove the described photoresist layer in metal silicide region that needs to form; Etching need form secondary side wall thin layer and the secondary side wall protective layer in metal silicide region, to form secondary side wall at the described grid structure sidewall that needs to form in metal silicide region; Remove remaining photoresist layer.
Optionally, in the method, semi-conductor device manufacturing method of described applied stress memory technique, described secondary side wall thin layer is amorphous carbon, and described secondary side wall protective layer is silicon nitride.
Optionally, in the method, semi-conductor device manufacturing method of described applied stress memory technique, described stressor layers is stress silicon nitride.
Optionally, in the method, semi-conductor device manufacturing method of described applied stress memory technique, described annealing is rapid thermal annealing or laser pulse annealing.
The method, semi-conductor device manufacturing method of applied stress memory technique of the present invention, in secondary side wall moulding process, etching need form the secondary side wall thin layer in metal silicide region, to form secondary side wall at the described grid structure sidewall that needs to form in metal silicide region, directly utilize secondary side wall as self-aligned metal silicate barrier layer (SAB), on the source/drain region exposing and grid structure, form metal silicide layer, thereby simplified processing step; Further, form metal silicide layer and remove secondary side wall afterwards, adopt stress proximity effect (stress proximity technique, SPT) technology, make the more contiguous raceway groove of CESL stressor layers, be conducive to mention the performance of device; In addition, a side wall of the present invention and secondary side wall all adopt amorphous carbon, in side wall of removal and secondary side wall, can adopt cineration technics, convenient removal.
Accompanying drawing explanation
Fig. 1 is the flow chart of the method, semi-conductor device manufacturing method of the applied stress memory technique of one embodiment of the invention;
Fig. 2 ~ 17 are the generalized section of device in the method, semi-conductor device manufacturing method of applied stress memory technique of one embodiment of the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the method, semi-conductor device manufacturing method of applied stress memory technique provided by the invention is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Describe the method, semi-conductor device manufacturing method of applied stress memory technique of the present invention in detail below in conjunction with Fig. 1 to Figure 17, this manufacture method comprises the following steps:
Step S01: form grid structure and carry out lightly doped drain injection on substrate;
Shown in figure 2, the material of described substrate 100 can be monocrystalline silicon, polysilicon, amorphous silicon, silicon Germanium compound or silicon-on-insulator (SOI) etc., is conventionally formed with fleet plough groove isolation structure (STI) 200 in described substrate 100.In the present embodiment, substrate 100 comprises needs to form metal silicide region A and without forming metal silicide region B, wherein, need to form metal silicide region A and refer on the grid structure that forms it on and source/drain region and need to form metal silicide layer, refer on it that without forming metal silicide region B All Ranges is all without formation metal silicide.Be understandable that, in other embodiments, the Zone Full of described substrate 100 can be needs to form metal silicide region.Described grid structure 110 comprises gate dielectric layer 111 and gate electrode 112, and described gate dielectric layer 111 is generally silicon dioxide layer, and described gate electrode 112 is generally polysilicon.Carry out subsequently lightly doped drain injection (LDD), to form lightly-doped source drain region 101 in the substrate 100 of described grid structure 110 both sides.
Step S02: form side wall thin layer on described substrate and grid structure one time;
Shown in figure 3, on described substrate 100 and grid structure 110, deposit one time side wall thin layer 120, a described side wall thin layer 120 is preferably amorphous carbon, is convenient to utilize cineration technics to remove.Certainly a described side wall thin layer 120 can also be other material that can form a side wall, for example silicon nitride.
Step S03: described in etching, a side wall thin layer is to form a side wall at described grid structure sidewall;
Shown in figure 4, a side wall thin layer 120 described in dry etching, forms side wall 121 one time at described metal silicide layer region A with without the grid structure sidewall 110 that forms metal silicide region B.
Step S04: form side wall protective layer one time on described substrate and a side wall, and carry out source/leakage Implantation formation source/drain region;
Shown in figure 5; on described substrate 100 and a side wall 121, form side wall protective layer 130 one time; and form patterned photoresist layer (not shown); carry out subsequently source/leakage Implantation take patterned photoresist layer as mask and form source/drain region 102; then utilize ashing degumming process to remove remaining photoresist layer, a described side wall protective layer 130 is injury-free in ashing degumming process for the protection of amorphous carbon.
Step S05: remove a described side wall protective layer;
Shown in figure 6, adopt dry method or wet processing to remove a described side wall protective layer 130.
Step S06: remove a described side wall;
Shown in figure 7, adopt cineration technics to remove a described side wall 121.
Step S07: form stressor layers on described substrate and grid structure, and carry out annealing in process;
Shown in figure 8, on described substrate 100 and grid structure 110, form stressor layers 140, described stressor layers 140 is preferably stressed silicon nitride layers, and it has good stress effect, and described annealing process is for example rapid thermal annealing (RTA) or laser pulse annealing (LSA) technique.In annealing process, can produce stress, these stress can be memorized; In ensuing technique, stressor layers is etched away, but the stress of memory in grid structure still can be transmitted among raceway groove, is conducive to improve carrier mobility.
Step S08: remove described stressor layers;
Shown in figure 9, adopt dry method or wet processing to remove described stressor layers 140.
Step S09: form successively secondary side wall thin layer and secondary side wall protective layer on described substrate and grid structure;
Shown in Figure 10, on described substrate 100 and grid structure 110, deposit successively secondary side wall thin layer 150 and secondary side wall protective layer 160, described secondary side wall thin layer 150 is for example amorphous carbon, described secondary side wall protective layer 160 is for example silicon nitride.
Step S10: etching need form secondary side wall thin layer and the secondary side wall protective layer in metal silicide region, to form secondary side wall at the described grid structure sidewall that needs to form in metal silicide region;
First,, shown in Figure 11, on described substrate 100, form photoresist layer 170;
Then, shown in Figure 12, utilize exposure and developing process to remove described need and form the photoresist layer 170 on metal silicide region A, only retain without the photoresist layer forming on metal silicide region B;
Then, shown in Figure 13, etching need form secondary side wall thin layer 150 and the secondary side wall protective layer 160 on metal silicide region A, to form secondary side wall 151 at described grid structure 110 sidewalls that need to form on metal silicide region A, be not etched without the secondary side wall thin layer 150 and the secondary side wall protective layer 160 that form on metal silicide region B, thereby the end face that need is formed to the upper source/drain region of metal silicide region A and grid structure comes out, wherein, the process conditions of described etching technics are for example: pressure is 1-10mTorr, source RF power is 100-300 watt, Bias RF power is 100-300 watt, oxygen flow is 10-30sccm, CF
4flow is 10-50sccm, and He flow is 20-100sccm, and temperature is 40-50 degree,
Finally, shown in Figure 14, remaining photoresist layer is removed in ashing.
Step S11: form metal silicide layer on the source/drain region exposing and grid structure;
Shown in Figure 15; because source/drain region and grid structure come out; thereby conventional metal silicide technology is carried out in the place can be being directly removed at secondary side wall thin layer 150 and secondary side wall protective layer 160; for example adopt prior art plated metal and carry out annealing process; thereby form metal silicide layer 170 on the source/drain region 102 exposing and grid structure 110; than prior art; the present invention directly utilizes secondary side wall as self-aligned metal silicate barrier layer (SAB); technique is simple, is conducive to raise the efficiency.
Step S12: remove described secondary side wall;
Shown in Figure 16, form after metal silicide layer 170, can adopt cineration technics to remove secondary side wall 151 and without the secondary side wall thin layer 150 and the secondary side wall protective layer 160 that form on metal silicide region B.
Step S13: form CESL stressor layers on described substrate and grid structure;
Shown in Figure 17, on described substrate 100 and grid structure 110, form via etch stop-layer (Contact etch stop layer, CESL) stressor layers 180, because secondary side wall 151 has been removed, thereby this step can adopt stress proximity effect (stress proximity technique, SPT) technology, CESL stressor layers 180 is close to raceway groove more, is conducive to mention the performance of device.
In sum, the method, semi-conductor device manufacturing method of applied stress memory technique of the present invention, in secondary side wall moulding process, etching need form the secondary side wall thin layer in metal silicide region, to form secondary side wall at the described grid structure sidewall that needs to form in metal silicide region, directly utilize secondary side wall as self-aligned metal silicate barrier layer, on the source/drain region exposing and grid structure, form metal silicide layer, thereby simplified processing step; Further, form metal silicide layer and remove secondary side wall afterwards, adopt SPT technology, make the more contiguous raceway groove of CESL stressor layers, be conducive to mention the performance of device; In addition, a side wall of the present invention and secondary side wall all adopt amorphous carbon, in side wall of removal and secondary side wall, can adopt cineration technics, convenient removal.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to including these changes and modification.
Claims (9)
1. a method, semi-conductor device manufacturing method for applied stress memory technique, comprising:
On substrate, form grid structure and carry out lightly doped drain injection, described substrate comprise need form metal silicide region and without form metal silicide region;
On described substrate and grid structure, form side wall thin layer one time;
Described in etching, a side wall thin layer is to form a side wall at described grid structure sidewall;
Carry out source/leakage Implantation and form source/drain region;
Remove a described side wall;
On described substrate and grid structure, form stressor layers, and carry out annealing in process;
Remove described stressor layers;
On described substrate and grid structure, form secondary side wall thin layer;
On described secondary side wall thin layer, form secondary side wall protective layer;
On described substrate and grid structure, form photoresist layer;
Utilize exposure and developing process to remove the described photoresist layer in metal silicide region that needs to form;
Etching need form secondary side wall thin layer and the secondary side wall protective layer in metal silicide region, to form secondary side wall at the described grid structure sidewall that needs to form in metal silicide region;
Remove remaining photoresist layer;
On the source/drain region exposing and grid structure, form metal silicide layer.
2. the method, semi-conductor device manufacturing method of applied stress memory technique as claimed in claim 1, is characterized in that, after forming metal silicide layer, also comprises on the source/drain region exposing and grid structure:
Remove described secondary side wall;
On described substrate and grid structure, form CESL stressor layers.
3. the method, semi-conductor device manufacturing method of applied stress memory technique as claimed in claim 2, is characterized in that, described CESL stressor layers is stress silicon nitride.
4. the method, semi-conductor device manufacturing method of applied stress memory technique as claimed in claim 1, is characterized in that, before carrying out source/leakage Implantation formation source/drain region, also comprises: on described substrate and a side wall, form side wall protective layer one time.
5. the method, semi-conductor device manufacturing method of applied stress memory technique as claimed in claim 4, is characterized in that, after carrying out source/leakage Implantation formation source/drain region, also comprises: remove a described side wall protective layer.
6. the method, semi-conductor device manufacturing method of applied stress memory technique as claimed in claim 4, is characterized in that, a described side wall thin layer is amorphous carbon, and a described side wall protective layer is silicon nitride.
7. the method, semi-conductor device manufacturing method of applied stress memory technique as claimed in claim 1, is characterized in that, described secondary side wall thin layer is amorphous carbon, and described secondary side wall protective layer is silicon nitride.
8. the method, semi-conductor device manufacturing method of applied stress memory technique as claimed in claim 1, is characterized in that, described stressor layers is stress silicon nitride.
9. the method, semi-conductor device manufacturing method of applied stress memory technique as claimed in claim 1, is characterized in that, described annealing is rapid thermal annealing or laser pulse annealing.
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| CN104051340B (en) * | 2013-03-13 | 2017-02-08 | 中芯国际集成电路制造(上海)有限公司 | Transistor manufacturing method using stress proximity technology |
| US9196708B2 (en) * | 2013-12-30 | 2015-11-24 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming a semiconductor device structure |
| CN104952797B (en) * | 2014-03-26 | 2019-01-18 | 中芯国际集成电路制造(上海)有限公司 | A kind of preparation method of semiconductor devices |
| CN107437547B (en) * | 2016-05-26 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN110310926B (en) * | 2019-06-25 | 2021-10-15 | 上海华力集成电路制造有限公司 | Method for solving defect formation of metal silicide of SRAM unit device |
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| CN1983564A (en) * | 2005-12-06 | 2007-06-20 | 联华电子股份有限公司 | Method for fabricating strained-silicon cmos transistors |
| CN101350353A (en) * | 2007-07-19 | 2009-01-21 | 松下电器产业株式会社 | Semiconductor device and its manufacturing method |
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| US20090227099A1 (en) * | 2008-03-06 | 2009-09-10 | Stefan Zollner | Method of forming a semiconductor device having a stressed electrode and silicide regions |
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| CN1983564A (en) * | 2005-12-06 | 2007-06-20 | 联华电子股份有限公司 | Method for fabricating strained-silicon cmos transistors |
| CN101350353A (en) * | 2007-07-19 | 2009-01-21 | 松下电器产业株式会社 | Semiconductor device and its manufacturing method |
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