CN102709250B - Semiconductor device manufacturing method utilizing stress memorization technology - Google Patents
Semiconductor device manufacturing method utilizing stress memorization technology Download PDFInfo
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- CN102709250B CN102709250B CN201210208961.2A CN201210208961A CN102709250B CN 102709250 B CN102709250 B CN 102709250B CN 201210208961 A CN201210208961 A CN 201210208961A CN 102709250 B CN102709250 B CN 102709250B
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Abstract
The invention discloses a semiconductor device manufacturing method utilizing a stress memorization technology, which comprises the following steps: partially removing a formed stress layer; selectively etching area of the stress layer, which is required to form a metal silicide area; forming a side wall on the side wall of a grid electrode structure on the formed metal silicide area, so as to directly serve as a self-aligned metal silicide barrier layer; forming a metal silicide layer on the exposed source/drain area and the grid electrode structure, so as to simplify the process steps; and removing the side wall after the metal silicide layer is formed, and adopting a stress proximity effect technology to allow a CESL stress layer to be closer to a channel so as to improve the performance of the device.
Description
Technical field
The present invention relates to integrated circuit and manufacture field, the particularly method, semi-conductor device manufacturing method of a kind of applied stress memory technique (SMT).
Background technology
Along with the development of cmos semiconductor device technology and in proportion size dwindle, stress engineering is playing increasing effect aspect semiconductor technology and device performance; In cmos device, introduce stress, mainly in order to improve device carrier mobility, useful to NMOS electron mobility at the upper tensile stress of cmos device channel direction (longitudinal), and compression is useful to PMOS hole mobility, tensile stress in channel width dimension (transverse) is all useful to the carrier mobility of NMOS and PMOS device, and useful to nmos device electron mobility in the compression of vertical-channel in-plane (out-of-plane), tensile stress is useful to PMOS device hole mobility.
Stress memory effect (SMT, Stress memorization technique) be a kind of introduce stress in CMOS technique method, its technological process is: after device source/leakage is injected, deposition one deck silicon nitride film protective layer (cap layer), and then carry out source/leakage annealing, in source/leakage annealing process, can produce silicon nitride film protective layer, thermal stress between polysilicon gate and side wall and internal stress effect, these stress can be by memory among polysilicon gate, in polysilicon, can produce tensile stress along vertical-channel in-plane (out-of-plane), and channel direction (longitudinal) can produce compression, in ensuing technique, silicon nitride film protective layer is etched away, but the stress of memory in polysilicon gate, still can be transmitted among the raceway groove of cmos semiconductor device, be transmitted to stress in raceway groove and be the tensile stress on compression and the channel direction (longitudinal) of vertical-channel in-plane (out-of-plane), can be drawn the impact of cmos device carrier mobility by above-mentioned stress, such stress effect is useful to improving nmos device electron mobility, can improve nmos device performance.
Detailed, prior art is introduced the common side wall moulding of method and the secondary side wall moulding process of stress in CMOS technique.Wherein, a side wall moulding process specifically comprises: 1) on substrate, form grid structure and carry out lightly doped drain injection; 2) on substrate and grid structure, carry out amorphous carbon deposition; 3) thus dry etching amorphous carbon form a side wall; 4) on substrate and a side wall, carry out silicon nitride film deposition to form silicon nitride protective layer, described silicon nitride protective layer, in order to as protection amorphous carbon, carries out subsequently S/D Implantation and forms source/drain region; 5) adopt dry method or wet processing to remove silicon nitride protective layer; 6) adopt cineration technics to remove a side wall of amorphous carbon material; 7) on substrate and grid structure, deposit stressed silicon nitride layers, and carry out annealing in process; 8) adopt dry method or wet processing to remove stressed silicon nitride layers, so far completed side wall moulding process one time.But, in existing secondary side wall moulding process, need to deposit again skim material fit dry etching and form secondary side wall, and then the auxiliary metal silicide layer (silicide) that forms in formation self-aligned metal silicate barrier layer, the forming process of whole metal silicide layer is more loaded down with trivial details, still has the space of optimizing.
Summary of the invention
The invention provides a kind of method, semi-conductor device manufacturing method of applied stress memory technique, to solve the loaded down with trivial details problem of existing manufacturing approach craft.
For solving the problems of the technologies described above, the invention provides a kind of method, semi-conductor device manufacturing method of applied stress memory technique, comprising:
Substrate is provided, on described substrate, is formed with grid structure, in described substrate, be formed with source/drain region;
On described substrate and grid structure, form stressor layers, and carry out annealing in process;
Etching need form the stressor layers in metal silicide region, to form side wall at the described grid structure sidewall that needs to form in metal silicide region;
On the source/drain region exposing and grid structure, form metal silicide layer.
Optionally, in the method, semi-conductor device manufacturing method of described applied stress memory technique, form metal silicide layer on the source/drain region exposing and grid structure after, also comprise: remove described side wall; On described substrate and grid structure, form CESL stressor layers.
Optionally, in the method, semi-conductor device manufacturing method of described applied stress memory technique, described CESL stressor layers is stress silicon nitride.
Optionally, in the method, semi-conductor device manufacturing method of described applied stress memory technique, described substrate comprises that need form metal silicide region and without forming metal silicide region, the step that etching need form the stressor layers in metal silicide region comprises: on described substrate and grid structure, form photoresist layer; Utilize exposure and developing process to remove the described photoresist layer in metal silicide region that needs to form; Etching need form the stressor layers in metal silicide region, to form side wall at the described grid structure sidewall that needs to form in metal silicide region; Remove remaining photoresist layer.
Optionally, in the method, semi-conductor device manufacturing method of described applied stress memory technique, described stressor layers is stress silicon nitride.
Optionally, in the method, semi-conductor device manufacturing method of described applied stress memory technique, described annealing is rapid thermal annealing or laser pulse annealing.
The method, semi-conductor device manufacturing method of applied stress memory technique of the present invention, after forming stressor layers, all do not remove, but selective etch need form the stressor layers in metal silicide region, to form side wall at the described grid structure sidewall that needs to form in metal silicide region, directly utilize side wall as self-aligned metal silicate barrier layer (SAB), on the source/drain region exposing and grid structure, form metal silicide layer, thereby simplified processing step; Further, form metal silicide layer and remove side wall afterwards, adopt stress proximity effect (stress proximity technique, SPT) technology, make the more contiguous raceway groove of CESL stressor layers, be conducive to mention the performance of device.
Brief description of the drawings
Fig. 1 is the flow chart of the method, semi-conductor device manufacturing method of the applied stress memory technique of one embodiment of the invention;
Fig. 2 ~ 10 are the generalized section of device in the method, semi-conductor device manufacturing method of applied stress memory technique of one embodiment of the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the method, semi-conductor device manufacturing method of applied stress memory technique provided by the invention is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Describe the method, semi-conductor device manufacturing method of applied stress memory technique of the present invention in detail below in conjunction with Fig. 1 to Figure 10, this manufacture method comprises the following steps:
Step S01: substrate is provided, is formed with grid structure on described substrate, be formed with source/drain region in substrate;
Shown in figure 2, the material of described substrate 100 can be monocrystalline silicon, polysilicon, amorphous silicon, silicon Germanium compound or silicon-on-insulator (SOI) etc., is conventionally formed with fleet plough groove isolation structure (STI) 200 in described substrate 100.In the present embodiment, substrate 100 comprises needs to form metal silicide region A and without forming metal silicide region B, wherein, need to form metal silicide region A and refer on the grid structure that forms it on and source/drain region and need to form metal silicide layer, refer on it that without forming metal silicide region B All Ranges is all without formation metal silicide.Be understandable that, in other embodiments, the Zone Full of described substrate can be needs to form metal silicide region.Described grid structure 110 comprises gate dielectric layer 111 and gate electrode 112, and described gate dielectric layer 111 is generally silicon dioxide layer, and described gate electrode 112 is generally polysilicon.Lightly-doped source drain region and source/drain region 102 in described substrate 100, are formed with.
Step S02: form stressor layers on described substrate and grid structure, and carry out annealing in process;
Shown in figure 3, on described substrate 100 and grid structure 110, form stressor layers 120, described stressor layers 120 is preferably stressed silicon nitride layers, it has good stress effect, the thickness of described stressor layers 120 is 30-60 nanometer for example, and described annealing process is for example rapid thermal annealing (RTA) or laser pulse annealing (LSA) technique.In annealing process, can produce stress, these stress can be memorized; In ensuing technique, stressor layers is etched away, but the stress of memory in grid structure still can be transmitted among raceway groove, is conducive to improve carrier mobility.
Step S03: etching need form the stressor layers in metal silicide region, to form side wall at the described grid structure sidewall that needs to form in metal silicide region;
First,, shown in figure 4, on substrate 100 and grid structure 110, form photoresist layer 130;
Then, shown in figure 5, utilize exposure and developing process to remove described need and form the photoresist layer on metal silicide region A, only retain without the photoresist layer forming on metal silicide region B;
Then, shown in figure 6, etching need form the stressor layers 120 on metal silicide region A, form side wall 121 with grid structure 110 sidewalls that form at need on metal silicide region A, be not etched without the stressor layers 120 forming on metal silicide region B, thereby the end face that need form the upper source/drain region of metal silicide region A and grid structure is come out; Wherein, the process conditions of described etching technics are as follows: pressure is 1-10mTorr, and source RF power is 100-300 watt, and Bias RF power is 100-300 watt, and oxygen flow is 10-30sccm, CF
4flow is 10-50sccm, and He flow is 20-100sccm, and temperature is 40-50 degree.
Finally, shown in figure 7, remaining photoresist layer is removed in ashing.
Especially, the end face that forms the upper source/drain region of metal silicide region A and grid structure due to need is exposed, on it, can inevitably form the natural oxidizing layer (native oxide layer) of skim, thereby before forming metal silicide layer, first wet method is removed natural oxidizing layer and remaining polymer (polymer) on source/drain region and grid structure.
Step S04: form metal silicide layer on the source/drain region exposing and grid structure;
Shown in figure 8, the source/drain region and the grid structure that form on metal silicide region A due to need come out, thereby conventional metal silicide technology is carried out in the place that can directly be removed in stressor layers, for example adopt prior art plated metal and carry out annealing process, thereby form metal silicide layer 140 on the source/drain region 102 exposing and grid structure 110, than prior art, the present invention directly utilizes side wall as self-aligned metal silicate barrier layer (SAB), and technique is simple.
Step S05: remove described side wall;
Shown in figure 9, form after metal silicide layer 140, can adopt cineration technics to remove side wall 121 and without the stressor layers forming on metal silicide region B.
Step S06: form CESL stressor layers on described substrate and grid structure;
Shown in Figure 10, on described substrate 100 and grid structure 110, form via etch stop-layer (Contact etch stop layer, CESL) stressor layers 150, because side wall 121 has been removed, thereby this step can adopt stress proximity effect (stress proximity technique, SPT) technology, CESL stressor layers 150 is close to raceway groove more, is conducive to mention the performance of device.
In sum, the method, semi-conductor device manufacturing method of applied stress memory technique of the present invention, after forming stressor layers, all do not remove, but selective etch need form the stressor layers in metal silicide region, to form side wall at the described grid structure sidewall that needs to form in metal silicide region, directly utilize side wall as self-aligned metal silicate barrier layer, on the source/drain region exposing and grid structure, form metal silicide layer, thereby simplified processing step; Further, form metal silicide layer and remove side wall afterwards, adopt stress proximity effect technology, make the more contiguous raceway groove of CESL stressor layers, be conducive to mention the performance of device.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to including these changes and modification.
Claims (5)
1. a method, semi-conductor device manufacturing method for applied stress memory technique, comprising:
Substrate is provided, on described substrate, is formed with grid structure, in described substrate, be formed with source/drain region;
On described substrate and grid structure, form stressor layers, and carry out annealing in process;
Etching need form the stressor layers in metal silicide region, to form side wall at the described grid structure sidewall that needs to form in metal silicide region;
On the source/drain region exposing and grid structure, form metal silicide layer;
Remove described side wall;
On described substrate and grid structure, form CESL stressor layers.
2. the method, semi-conductor device manufacturing method of applied stress memory technique as claimed in claim 1, is characterized in that, described CESL stressor layers is stress silicon nitride.
3. the method, semi-conductor device manufacturing method of applied stress memory technique as claimed in claim 1, it is characterized in that, described substrate comprises that need form metal silicide region and without forming metal silicide region, the step that etching need form the stressor layers in metal silicide region comprises:
On described substrate and grid structure, form photoresist layer;
Utilize exposure and developing process to remove the described photoresist layer in metal silicide region that needs to form;
Etching need form the stressor layers in metal silicide region, to form side wall at the described grid structure sidewall that needs to form in metal silicide region;
Remove remaining photoresist layer.
4. the method, semi-conductor device manufacturing method of applied stress memory technique as claimed in claim 1, is characterized in that, described stressor layers is stress silicon nitride.
5. the method, semi-conductor device manufacturing method of applied stress memory technique as claimed in claim 1, is characterized in that, described annealing is rapid thermal annealing or laser pulse annealing.
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