JP2008251850A - Semiconductor device and manufacturing method of the semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology to improve the reliability of a semiconductor device. <P>SOLUTION: The semiconductor device comprises a wiring board 1 having front and rear surfaces and a semiconductor element 3 mounted on the front surface of the wiring board 1. The wiring board 1 comprises a plurality of insulation layers stacked in multiple layers, a surface interconnection 6 formed in a desired pattern on the surface of each insulation layer, and a plurality of vias. The vias are formed, in such a manner as to penetrate the plurality of insulation layers individually and connect a first surface interconnection formed on the surface of a first insulation layer, located in an upper layer and a second surface interconnection, formed on the surface of a second insulation layer located in a layer below the first insulation layer. Among the plurality of vias, thermal vias 9 formed in a region of the wiring board 1, where a semiconductor element 3 is mounted are arranged in a form of a lattice along a first side 3a and a second side 3b which are two adjacent sides of the semiconductor element 3 mounted plane of the wiring board 1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device technology, and more particularly to a technology effective when applied to a semiconductor device including a wiring substrate having a multi-layer structure.

  Mobile communication devices such as cellular phones include, for example, surface-mounted semiconductor chips on which power amplifiers or antenna switches are formed, and surface-mounted chip components on which capacitors or resistors are formed. However, a high frequency circuit module having a structure mounted on the same substrate is employed. Such a high-frequency circuit module is called an HPA (High Power Amplifier) module or an RF (Radio Frequency) module.

  Some HPA modules have a structure in which a plurality of vias called thermal vias for heat dissipation are provided under a chip of a multilayer wiring board on which a semiconductor chip is mounted.

  In recent years, in the HPA module, space for providing thermal vias has been reduced due to demands for miniaturization and high functionality, and therefore it is necessary to efficiently dissipate heat in a small space.

For example, Japanese Patent Laid-Open No. 9-153679 (Patent Document 1) describes a laminated glass ceramic circuit board in which thermal vias are arranged in a staggered manner with the same adjacent pitch. By arranging in this way, the density of thermal vias can be increased in an array.
JP-A-9-153679

  The inventor studied the HPA module and found the following problems.

  In the HPA module, a wiring board having a wiring structure extending over a plurality of layers, in which a plurality of ceramic plates (called green sheets) having wirings formed in a desired pattern on the surface is laminated and integrated, is used.

  On one surface (semiconductor chip mounting surface) of the wiring board, for example, a semiconductor chip on which a power amplifier or an antenna switch or the like is formed and other chip components are mounted. On the mounting surface), external connection terminals for mounting the HPA module on a printed circuit board or the like are formed.

  This wiring board is formed by laminating a plurality of green sheets on which surface wirings formed on the surface of each green sheet in a desired pattern and interlayer connection conductors called vias that electrically or thermally connect the green sheets are formed. Thereafter, it is manufactured by firing.

  However, the green sheet has a characteristic that it is easily shrunk at the time of firing as compared with a conductor material such as copper and silver used for wiring and vias. For this reason, in the step of firing the wiring substrate, a portion having a high wiring pattern density or a portion having a high via density does not shrink or hardly shrinks, and a portion having a low wiring pattern or via density tends to shrink by firing. .

  As described above, since the shrinkage rate during firing differs depending on the density of the wiring pattern and via, the wiring substrate after firing is in a state where a portion having a high wiring pattern or via density protrudes. That is, there is a problem that the flatness of the surface (semiconductor chip mounting surface and module mounting surface) of the wiring substrate deteriorates as the density of the wiring patterns and vias increases.

  In particular, thermal vias arranged in the semiconductor chip mounting area for releasing heat generated when the semiconductor chip is driven to the outside are arranged at a high density as disclosed in, for example, Japanese Patent Laid-Open No. 9-153679. The flatness of the area around the semiconductor chip mounting area of the wiring board is poor.

  Further, the thermal vias are arranged on a straight line along the thickness direction of the wiring board in order to shorten the heat transfer path. For this reason, since the protruding portions of the insulating layers overlap, the flatness of the entire wiring board is very poor.

  Here, if the flatness of the module mounting surface is poor, when mounting the HPA module on the component mounting surface of a mounting board such as a printed circuit board, connection failure or short circuit due to insufficient wetting of the bonding material such as solder occurs. there's a possibility that.

  In addition, when the flatness of the semiconductor chip mounting surface is poor, the mountability of the semiconductor chip or other chip components is lowered.

  As described above, when the flatness of the semiconductor chip mounting surface or the module mounting surface of the wiring board decreases, the reliability of the HPA module decreases.

  An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, a wiring board having a first surface and a second surface located on the opposite side of the first surface, and a semiconductor element mounted on the first surface of the wiring substrate, the wiring The substrate is formed so as to penetrate each of the plurality of insulating layers, a surface wiring formed in a desired pattern on the surface of each of the plurality of insulating layers, and each of the plurality of insulating layers. Of the layers, the first surface wiring formed on the surface of the first insulating layer disposed on the upper layer and the second surface wiring formed on the surface of the second insulating layer disposed on the lower layer of the first insulating layer Of the plurality of vias, the vias formed in the mounting region of the semiconductor element of the wiring board are first sides adjacent to each other of the mounting surface of the semiconductor element. And arranged in a grid pattern along the second side Is shall.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, according to the present invention, the reliability of the semiconductor device can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted in principle. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
In the first embodiment, an example of an HPA module, which is a high-frequency circuit module mounted on a mobile communication device such as a mobile phone, will be described as a semiconductor device. 1 is a plan view showing the appearance of the HPA module according to the first embodiment, FIG. 2 is a cross-sectional view taken along the line AA shown in FIG. 1, and FIG. 3 is the surface of the wiring board of the HPA module shown in FIG. FIG. 4 is a plan view showing a state in which components such as semiconductor elements mounted on the surface of the wiring board in the plan view shown in FIG. 3 are removed.

  In FIG. 4, the outlines of the semiconductor elements 3 and 4 and the electronic component 14 shown in FIG. 3 are indicated by dotted lines.

  In FIG. 1, in the HPA module (semiconductor device) 100 according to the first embodiment, a wiring board 1 is sealed with a sealing resin 2. Further, as shown in FIG. 2, the wiring board 1 has a front surface (first surface) 1a on which semiconductor elements 3 and 4 are mounted and a back surface (second surface) 1b located on the opposite side of the front surface 1a. is doing. The semiconductor elements 3 and 4 are sealed with a sealing resin 2.

  The wiring board 1 has a structure in which a plurality of insulating layers 5 such as glass ceramics are laminated (four layers in FIG. 2), and a circuit necessary for the HPA module 100 is formed on the surface of each insulating layer 5. Therefore, the surface wiring 6 formed in a desired pattern is formed. Further, the back surface wiring 8 formed in a desired pattern is formed on the back surface (second surface) of the wiring substrate 1.

  The front surface wiring 6 and the back surface wiring 8 include electrode terminals for electrically connecting the wiring substrate 1 and the semiconductor elements 3, 4 and the like, and external connection terminals of the HPA module 100.

  Further, the surface wiring 6 of each layer is electrically or thermally connected by a via 7. For example, in FIG. 2, the surface wiring (first surface wiring) 6a formed on the surface of the insulating layer (first insulating layer) 5a arranged in the second layer is the insulating layer arranged in the third layer. The surface wiring (second surface wiring) 6b formed in the (second insulating layer) 5b is connected to the via 7 or the thermal via 9.

  Further, the front surface wiring 6c of the insulating layer 5c arranged in the lowermost layer is connected to the back surface of the insulating layer 5c, that is, the back surface wiring 8 formed on the back surface 1b of the wiring substrate 1 via the via 7 or the thermal via 9. Has been.

  The via 7 and the thermal via 9 are interlayer communication paths formed by filling a through hole formed through each insulating layer 5 with a conductor such as copper (Cu) or silver (Ag).

  On the surface 1a of the wiring substrate 1, a plurality of electronic components 14 are mounted in addition to the semiconductor element 3 as shown in FIG. A power amplifier circuit is formed inside the semiconductor element 3 and has a function of amplifying the transmission signal current input to the input terminal of the semiconductor element 3. The transmission signal current amplified by the semiconductor element 3 is transmitted to the semiconductor element 4 in which the antenna switch circuit is formed through the surface wiring 6 and the via 7 formed in the wiring substrate 1.

  Here, since the semiconductor element 3 has a function of amplifying a high-frequency signal current, the amount of heat generated during driving is larger than that of the other electronic components 14. Further, since the semiconductor element 4 has a switching function for transmitting the amplified high-frequency signal current to the antenna, the amount of heat generated during driving is larger than that of other electronic components.

  Of the component parts of the semiconductor elements 3 and 4, the electrode terminals formed for inputting / outputting the amplified high-frequency signal current to / from the outside have a particularly high calorific value, and therefore the semiconductor elements in which these electrode terminals are arranged. The outer edge portions 3 and 4 generate a larger amount of heat than the periphery of the central portion of the semiconductor elements 3 and 4.

  Therefore, in the region where the semiconductor element 3 and the semiconductor element 4 of the wiring substrate 1 are mounted, the heat generated in the semiconductor element 3 and the semiconductor element 4 is released to the outside, so that the thermal via as shown in FIGS. A plurality of 9 are formed.

  Although this thermal via 9 is a kind of the above-described via 7, it has a function as a thermal communication path for dissipating the heat generated in the semiconductor elements 3 and 4 to the outside of the HPA module 100. The description will be made separately from the vias 7 other than the via 9.

  The thermal via 9 may have a function as an electrical communication path for supplying a reference power supply potential to the semiconductor elements 3 and 4 in addition to a function as a thermal communication path.

  Here, as shown in FIG. 4, in the first embodiment, on the plane of the thermal via 9 on the surface 1a (see FIG. 2) on which the semiconductor elements 3 and 4 (see FIG. 1) of the wiring board 1 are mounted. The arrangement is arranged in a grid pattern. Specifically, among the four sides of the semiconductor elements 3 and 4 on the mounting surface side, the semiconductor elements 3 and 4 are arranged in a lattice shape along the first side 3a and 4a and the second side 3b and 4b that are adjacent to each other.

  As described above, by arranging the thermal vias 9 in a lattice pattern, the density of the thermal vias 9 in the mounting region of the semiconductor elements 3 and 4 can be reduced. When the thermal vias 9 are arranged in a lattice pattern, for example, as described in Japanese Patent Laid-Open No. 9-153679 (Patent Document 1), the thermal vias are arranged in a zigzag manner with the adjacent pitch being equal to 10 as compared with the case where the thermal vias are arranged. % Can be reduced.

  Although details will be described later in the description of the manufacturing method, when the density of the thermal vias 9 is reduced, the semiconductor elements 3 and 4 of the wiring board 1 are mounted due to the difference in contraction rate between the thermal vias 9 and the insulating layer 5 shown in FIG. It is possible to suppress a decrease in flatness of the front surface 1a and the back surface (second surface) 1b located on the opposite side.

  By the way, if the density of the thermal vias 9 is reduced, the heat dissipation characteristics of the HPA module 100 may be lowered. However, when the thermal vias 9 are arranged in a grid pattern, the density of the thermal vias 9 corresponding to the outer edge portions of the semiconductor elements 3 and 4 that are the portions where the semiconductor elements 3 and 4 generate the largest amount of heat (that is, arranged on the outermost periphery). The density of the thermal vias 9) can be arranged with the same density as compared with the case where the thermal vias are arranged in a staggered manner with the same adjacent pitch. For this reason, it becomes possible to suppress the fall of the heat dissipation characteristic of the HPA module 100.

  According to the first embodiment, since the flatness of the surface 1a of the wiring board 1 can be improved, it is possible to improve the mounting reliability of the semiconductor elements 3, 4 and other components. Further, since the flatness of the back surface 1b opposite to the front surface 1a of the wiring board 1 can be improved, the mounting reliability of the HPA module 100 can be improved.

  In addition, since the arrangement density of the thermal vias 9 at a portion where the heat generation amount is particularly large among the components of the semiconductor elements 3 and 4 does not decrease, it is possible to suppress a decrease in the heat dissipation characteristics of the HPA module 100.

  Next, a method for manufacturing the HPA module 100 according to the first embodiment will be described with reference to FIGS.

  FIG. 5 is a cross-sectional view showing a process of forming a via in an insulating plate serving as a wiring board in the manufacturing process of the HPA module according to the first embodiment, and FIG. 6 is a manufacturing process of the HPA module according to the first embodiment. FIG. 7 is a cross-sectional view showing a process of forming a surface wiring with a desired pattern on the surface of an insulating board serving as a wiring board. FIG. FIG. 8 is a cross-sectional view showing a step of firing a laminated body of insulator plates in the manufacturing process of the HPA module according to the first embodiment.

  First, as shown in FIG. 5, a plurality of green sheets (insulator plates) 10 which are insulator plates before sintering are prepared. The green sheet 10 may be a sheet formed by mixing a material such as glass and ceramic powder together with an organic solvent at a predetermined ratio.

  Next, a plurality of through holes 11 penetrating from the surface in the thickness direction are formed at predetermined positions of the green sheet 10. In the through-hole forming step, a plurality of through-holes 11 are formed in a lattice pattern in a region where the via 7 and the thermal via 9 shown in FIG. 2 are formed.

  When the through hole 11 is filled with a conductor 12 such as copper (Cu) or silver (Ag) in the next step, it becomes a via which is an interlayer communication path. For this reason, by arranging the through holes 11 formed in the region where the semiconductor elements are mounted in a grid pattern, the thermal vias 9 can be arranged in a grid pattern as shown in FIG.

  Next, the plurality of through holes 11 are filled with a conductor 12 such as copper (Cu) or silver (Ag). As a method for filling the conductor 12, for example, a method in which the paste-like conductor 12 is printed on the entire surface of the green sheet 10 and then embedded in the through hole 11 by squeezing can be employed.

  Next, as shown in FIG. 6, the surface wiring 6 is formed in a desired pattern on the surface 10 a of the green sheet 10. In this surface wiring formation step, a photolithography method using a photosensitive conductive material or a photosensitive resist can be employed.

  Further, the green sheet 10 disposed in the lowermost layer of the wiring board 1 (see FIG. 2) forms the back surface wiring 8 with a desired pattern on the back surface 10b side.

  Next, as shown in FIG. 7, a green sheet 10 on which surface wiring 6 is formed in a desired pattern is laminated. At this time, the green sheet 10 in which the back surface wiring 8 is formed on the back surface 10b is used as the lowermost layer, and the green sheet 10 is laminated in a predetermined order.

  Next, by applying pressure to the laminate of the green sheets 10 and firing, as shown in FIG. 8, the green sheets 10 become the insulating layer 5 (see FIG. 2), which is a sintered glass ceramic, and the wiring board. 1 is completed.

  The green sheet 10 before firing is softer than the insulating layer 5 which is a glass ceramic after sintering. For this reason, by applying pressure prior to the firing step, the green sheets 10 where the surface wiring 6 is not formed contact each other as shown in FIG.

  Therefore, when the laminate of the green sheets 10 is fired, the insulating layer 5 after sintering becomes an integral structure, and the surface wiring 6 formed inside the wiring substrate 1 (see FIG. 2) is sealed in the insulating layer 5. It will be in the state.

  In this firing step, the green sheet 10, the conductor 12, the front surface wiring 6, and the back surface wiring 8 contract. Since the green sheet 10 has a higher shrinkage rate than the conductor 12, the front surface wiring 6, and the back surface wiring 8, which are metallic materials, the region where the arrangement density of the conductor 12, the front surface wiring 6, and the back surface wiring 8 is high, particularly the arrangement of the conductor 12 The portion where the thermal via 9 having the highest density is formed tends to have a protruding shape.

  However, in the first embodiment, the arrangement density of the thermal vias 9 is reduced by arranging the thermal vias 9 in a grid pattern, so that the protruding phenomenon due to the difference in the shrinkage rate of the material constituting the wiring board 1 is achieved. Can be suppressed.

  For this reason, it becomes possible to improve the flatness of the front surface 1a and the back surface 1b of the wiring board 1.

  Next, as shown in FIG. 2, the semiconductor elements 3, 4 and other passive components are mounted on the surface 1 a of the wiring board 1. In this mounting process, the semiconductor elements 3 and 4 are mounted at predetermined positions via a bonding material such as solder, and predetermined connection is performed using a conductive material such as a bonding wire.

  Finally, the front surface 1a of the wiring board 1 is sealed with the sealing resin 2 to complete the HPA module 100 shown in FIG.

(Embodiment 2)
In the first embodiment, as a method for reducing the arrangement density of the thermal vias formed in the semiconductor element mounting region of the wiring board, the method for arranging the arrangement of the thermal vias on the plane in a lattice shape has been described.

  In the second embodiment, the thermal via is arranged at a position where the thermal via formed in the insulating layer arranged in the upper layer and the thermal via formed in the insulating layer arranged in the lower layer do not overlap. explain.

  FIG. 9 is a plan view showing a semiconductor element mounting region on the surface of the third insulating layer of the wiring board of the HPA module according to the second embodiment, and FIG. 10 is a cross-sectional view taken along line BB shown in FIG. is there.

  9 and 10, the difference between the HPA module 200 of the second embodiment and the HPA module 100 described in the first embodiment is the arrangement of the thermal vias 9 with respect to the planar direction of the wiring board 1.

  In the HPA module 100 described in the first embodiment, the thermal vias 9 are arranged in the plane direction intersecting with the thickness direction of the wiring board 1 so that the thermal vias 9 formed in the insulating layers 5 overlap each other. Has been. That is, as shown in FIG. 2, the wiring substrate 1 is arranged in a straight line when viewed from the front surface 1 a to the back surface 1 b (the thickness direction of the wiring substrate 1).

  On the other hand, in the HPA module 200 of the second embodiment, the thermal vias 9 formed in each insulating layer 5 are not arranged linearly along the thickness direction.

  In the HPA module 200, the thermal vias 9 are arranged in the plane direction intersecting with the thickness direction of the wiring board 1, as shown in FIGS. 9 and the thermal via 9 formed in the insulating layer 5 disposed in the lower layer are disposed at positions that do not overlap with the thickness direction of the wiring board 1. Such an arrangement mode of the thermal via 9 is hereinafter referred to as an offset arrangement.

  For example, as shown in FIGS. 9 and 10, a thermal via (first via) 9a formed in the second insulating layer 5a is a thermal via (second via) formed in the third insulating layer 5b. The vias 9 b are arranged at positions that do not overlap with the plane direction intersecting the thickness direction of the wiring board 1. That is, the thermal via 9a and the thermal via 9b are offset.

  In FIG. 9, the thermal via 9a is indicated by a solid line and the thermal via 9b is indicated by a dotted line in order to easily show that the thermal via 9a and the thermal via 9b do not overlap.

  As described above, when the thermal vias 9a and 9b are offset from each other, the arrangement density of the thermal vias 9 with respect to the plane of the front surface 1a or the back surface 1b of the wiring board 1 can be averaged over the entire semiconductor element mounting region. That is, as compared with the case where the thermal vias 9 are linearly arranged as in the HPA module 100 described in the first embodiment, variation in the arrangement density of the thermal vias 9 can be suppressed.

  By suppressing the variation in the arrangement density of the thermal vias 9 in this way, it becomes possible to suppress the protruding phenomenon due to the difference in the shrinkage rate of the material constituting the wiring board 1 described in the first embodiment. .

  Here, for example, in the HPA module 200 shown in FIGS. 9 and 10, the thermal via 9 a formed in the second insulating layer 5 a is connected to the thermal via 9 b formed in the third insulating layer 5 b. The case where a part overlaps is demonstrated.

  FIG. 11 is an enlarged plan view of the semiconductor element mounting region on the surface of the third insulating layer of the wiring board showing the arrangement of thermal vias in the HPA module as a comparative example of the second embodiment, and FIG. It is an expanded sectional view of the HPA module cut | disconnected along the BB line shown in FIG.

  11 and 12, in the HPA module 201 which is a comparative example of the second embodiment, the thermal via 9a formed in the second insulating layer 5a is formed in the third insulating layer 5b. A part of the thermal via 9b overlaps.

  Thus, when the thermal via 9a and the thermal via 9b partially overlap each other, the arrangement density of the thermal vias 9 in the overlapping portion is locally higher than the surroundings. That is, the arrangement density of the thermal vias 9 varies. For this reason, the flatness of the front surface 1a and the back surface 1b of the wiring board 1 is lowered.

  As shown in FIGS. 9 and 10, in the HPA module 200 of the second embodiment, the thermal via 9a and the thermal via 9b do not overlap. For this reason, since there is no place where the arrangement density of the thermal vias 9 is locally high, the front surface 1a and the back surface 1b of the wiring board 1 are dramatically flatter than the HPA module 201 shown in FIGS. The degree can be improved.

  In the second embodiment, as an example of the offset arrangement, the thermal via (first via) 9a formed in the second insulating layer 5a is the thermal via formed in the third insulating layer 5b. The HPA module 200 arranged at a position not overlapping with the via (second via) 9b has been described.

  However, the position where the thermal via 9 is offset is not limited between the second layer and the third layer. For example, the thermal via 9 may be disposed offset between the first layer and the second layer. Also, the thermal vias 9 may be offset at two locations between the first layer and the second layer and between the third layer and the fourth layer.

  Further, for example, the thermal vias 9 formed in the insulating layers 5 that are not in contact with each other, such as the first layer and the fourth layer, or the second layer and the fourth layer, may be offset.

  However, if the number of offset positions is increased too much, the heat transfer path becomes long, and the heat dissipation characteristics may be deteriorated. As a result of examination by the present inventor, it is possible to improve the flatness of the front surface 1a and the back surface 1b of the wiring board 1 by performing offset arrangement at least at one place. It is preferable to perform offset placement at any one of them.

  Next, differences between the method for manufacturing the HPA module 200 according to the second embodiment and the method for manufacturing the HPA module 100 described in the first embodiment will be described.

  In the method of manufacturing the HPA module 200 according to the second embodiment, the green sheet 10 shown in FIG. 5 described in the first embodiment is formed in the step of forming the through hole 11 that becomes the thermal via 9 (see FIG. 10). The point which forms the through-hole 11 in the position (position which does not overlap when laminated | stacked) on a different plane for every green sheet 10 to be different is different.

  For example, in order to obtain the HPA module 200 shown in FIGS. 9 and 10, the through holes 11 of the first layer and the second layer are formed with the through holes 11 serving as the thermal vias 9 at the same position on the plane. The through holes 11 in the second layer and the third layer form the through holes 11 at different positions on the plane (positions that do not overlap each other when stacked).

  In other manufacturing steps, the HPA module 200 of the second embodiment can be obtained by the same method as the manufacturing method described in the first embodiment.

  In the second embodiment, the embodiment in which the thermal via 9 is offset is described. However, the signal via, which is a conductive path for transmitting an electric signal, can also be offset.

  FIG. 13 is an enlarged plan view of the signal via formation region on the surface of the fourth insulating layer of the wiring board 1 of the HPA module 200 which is a modification of the second embodiment, and FIG. 14 is a CC view shown in FIG. It is sectional drawing of the HPA module 200 along a line.

  In FIG. 13 and FIG. 14, among the vias included in the HPA module 200, the signal via 13 serving as a conductive path for transmitting an electrical signal is disposed in the lower layer with the signal via 13 formed in the insulating layer 5 disposed in the upper layer. The signal via 13 formed in the insulating layer 5 is disposed at a position where it does not overlap. That is, the signal vias 13 are offset.

  For example, as shown in FIGS. 13 and 14, the signal via (first via) 13a formed in the third insulating layer 5a is the signal via (second via) formed in the fourth insulating layer 5b. The vias 13b are arranged at positions that do not overlap. That is, the signal via 13a and the signal via 13b are offset.

  The HPA module 200 is a high-frequency circuit module and is used by being incorporated in a mobile communication device such as a mobile phone. For this reason, depending on the usage environment of the mobile communication device, the HPA module 200 may be exposed to an environment with a lot of moisture in the atmosphere.

  Here, when there is a large amount of moisture in the surrounding environment of the HPA module 200, this moisture may enter the HPA module 200 along the signal vias 13 formed in the wiring substrate 1 of the HPA module 200.

  For this reason, when moisture permeates into the HPA module 200, a leak current or the like is generated, and the HPA module 200 may not exhibit desired characteristics. In particular, when moisture is generated up to the uppermost layer of the wiring substrate 1 on which the semiconductor element 3 (see FIG. 9) is mounted, a leak current is likely to occur. For this reason, the reliability of the HPA module 200 is lowered.

  In the second embodiment, the signal via 13 is offset, so that the moisture intrusion route distance is longer than when the signal via 13 is linearly arranged in the thickness direction of the wiring board 1. can do.

  For this reason, the HPA module 200 can suppress moisture from entering the inside of the HPA module 200, particularly the uppermost layer of the wiring board 1 on which the semiconductor element 3 (see FIG. 9) and the like are mounted. .

  Therefore, according to the second embodiment, the reliability of the HPA module 200 can be improved.

(Embodiment 3)
In the first embodiment and the second embodiment, the method for planarizing the front surface and the back surface of the wiring board by the thermal via arrangement method has been described. In the third embodiment, a method of additionally inserting an insulating layer at a location where the density of vias and surface wiring is low will be described.

  FIG. 15 is a cross-sectional view of the HPA module according to the third embodiment. In FIG. 15, the difference between the HPA module 300 of the third embodiment and the HPA module 100 described in the first embodiment is a region sandwiched between the insulating layers 5 of the wiring board 1 and the surface wiring 6. A region where no is formed is filled with an interlayer insulating material (insulating material) 15.

  As described above, the region sandwiched between the insulating layers 5 of the wiring board 1 and having no surface wiring 6 formed is filled with the interlayer insulating material 15, so that the insulating layer 5 contracts in the firing process. However, it is possible to suppress a decrease in flatness of the front surface 1a and the back surface 1b of the wiring board 1.

  By the way, as the interlayer insulating material 15, various materials can be selected and used as long as they have insulating properties. However, it is preferable to use the same material as that of the insulating layer 5. By using the same material for the insulating layer 5 and the interlayer insulating material 15, the insulating layer 5 and the interlayer insulating material 15 are combined in the firing step, so that the wiring substrate 1 can be integrated.

  For this reason, it becomes possible to suppress that each insulating layer 5 of the wiring board 1 after sintering is peeled and the reliability of the HPA module 300 is lowered.

  Next, differences between the method for manufacturing the HPA module 300 according to the third embodiment and the method for manufacturing the HPA module 100 described in the first embodiment will be described.

  In the method of manufacturing the HPA module 300 according to the third embodiment, the interlayer insulating material 15 is applied to the region where the surface wiring 6 is not formed in the step of laminating the green sheet 10 shown in FIG. 7 described in the first embodiment. Apply.

  In FIG. 7, before the green sheet 10 laminated on the third layer is laminated on the green sheet 10 laminated on the lowermost layer, an interlayer insulating material 15 is applied to a region where the surface wiring 6 is not formed.

  Thereafter, each time the green sheets 10 are sequentially laminated, the interlayer insulating material 15 is applied to a region on the surface of the green sheet 10 where the surface wiring 6 is not formed, thereby forming a laminate of the green sheets 10.

  In the subsequent manufacturing steps, the HPA module 300 of the third embodiment can be obtained by the same manufacturing method as the HPA module 100 described in the first embodiment.

  According to the third embodiment, in the step of laminating the green sheets 10, the interlayer insulating material 15 is applied to the area where the surface wiring 6 is not formed on the surface of each green sheet 10, thereby It becomes possible to improve the flatness of the front surface 1a and the back surface 1b.

  The reliability of the HPA module 300 can be improved by improving the flatness of the front surface 1a and the back surface 1b of the wiring board 1.

  The invention made by the present inventor has been specifically described based on the embodiment of the present invention. However, the present invention is not limited to the embodiment of the invention, and various modifications can be made without departing from the scope of the invention. Is possible.

  For example, in the HPA module 200 in which the offset arrangement described in the second embodiment is performed, a region that is sandwiched between the insulating layers 5 of the wiring board 1 and that does not have the surface wiring 6 is formed in the third embodiment. As described above, the interlayer insulating material 15 may be filled.

  In this case, since the flatness of the front surface 1a and the back surface 1b of the wiring substrate 1 is improved, the reliability of the HPA module 200 can be further improved.

  The present invention can be applied to a semiconductor device using a wiring board having a plurality of stacked structures.

It is a top view which shows the external appearance of the HPA module of Embodiment 1 of this invention. It is sectional drawing along the AA line shown in FIG. It is a top view which shows the surface of the wiring board of the HPA module shown in FIG. It is a top view which shows the state which removed components, such as a semiconductor element mounted in the surface of the wiring board of the top view shown in FIG. It is sectional drawing which shows the process of forming a via | veer in the insulator board used as a wiring board in the manufacturing process of the HPA module of Embodiment 1 of this invention. In the manufacturing process of the HPA module of Embodiment 1 of this invention, it is sectional drawing which shows the process of forming surface wiring with a desired pattern on the surface of the insulator board used as a wiring board. It is sectional drawing which shows the process of laminating | stacking the insulator board used as a wiring board in the manufacturing process of the HPA module of Embodiment 1 of this invention. It is sectional drawing which shows the process of baking the laminated body of an insulator board in the manufacturing process of the HPA module of Embodiment 1 of this invention. It is a top view which expands and shows the semiconductor element mounting area | region of the insulating layer surface of the 3rd layer of the wiring board of the HPA module of Embodiment 2 of this invention. It is sectional drawing of the HPA module along the BB line shown in FIG. It is a top view which expands and shows the semiconductor element mounting area | region of the insulating layer surface of the 3rd layer of the wiring board of the HPA module which is a comparative example of Embodiment 2 of this invention. It is sectional drawing of the HPA module along the BB line shown in FIG. It is an enlarged plan view which shows the location in which the signal via | veer was formed of the insulating layer surface of the 4th layer of the wiring board of the HPA module which is a modification of Embodiment 2 of this invention. It is sectional drawing of the HPA module along CC line shown in FIG. It is sectional drawing of the HPA module of Embodiment 3 of this invention.

Explanation of symbols

1 Wiring board 1a surface (first surface)
1b Back side (second side)
2 Sealing resin 3 Semiconductor element 4 Semiconductor elements 3a, 4a Side (first side)
3b, 4b side (second side)
5 Insulating layer 5a Insulating layer (first insulating layer)
5b Insulating layer (second insulating layer)
5c Insulating layer 6, 6c Surface wiring 6a Surface wiring (first surface wiring)
6b Surface wiring (second surface wiring)
7 Via 8 Back wiring 9 Thermal via 9a Thermal via (first via)
9b Thermal via (second via)
10 Green sheet (insulator plate)
10a Front surface 10b Back surface 11 Through hole 12 Conductor 13 Signal via 13a Signal via (first via)
13b Signal via (second via)
14 Electronic component 15 Interlayer insulating material (insulating material)
100, 200, 201, 300 HPA module (semiconductor device)

Claims (4)

A wiring substrate having a first surface and a second surface located on the opposite side of the first surface; and a semiconductor element mounted on the first surface of the wiring substrate;
The wiring board is
A plurality of laminated insulating layers;
Surface wiring formed in a desired pattern on the surface of each of the plurality of insulating layers;
Backside wiring formed in a desired pattern on the second surface;
A first surface wiring formed on the surface of the first insulating layer disposed in an upper layer of the plurality of insulating layers, and a lower layer of the first insulating layer; A plurality of vias communicating with the second surface wiring formed on the surface of the second insulating layer disposed on the second surface wiring or the back wiring formed on the second surface;
Among the plurality of vias, the vias formed in the mounting region of the semiconductor element of the wiring board are in a lattice shape along the first side and the second side adjacent to each other on the mounting surface of the semiconductor element. A semiconductor device characterized by being arranged in a series. A wiring board having a first surface and a second surface located on the opposite side of the first surface; and a semiconductor element mounted on the first surface of the wiring substrate;
The wiring board is
A plurality of insulating layers;
A wiring layer formed in a desired pattern on the surface of each of the plurality of insulating layers;
A first wiring layer formed on the surface of the first insulating layer disposed in an upper layer of the plurality of insulating layers, and a lower layer of the first insulating layer. A plurality of vias communicating with the second wiring layer formed on the surface of the second insulating layer formed on the surface of the arranged second insulating layer;
The plurality of vias overlap a first via formed in the first insulating layer and a second via formed in the second insulating layer with respect to a plane direction intersecting with a thickness direction of the wiring board. A semiconductor device, wherein the semiconductor device is arranged at a position where it does not become. The semiconductor device according to claim 2,
The semiconductor device, wherein the first via and the second via are vias formed in a mounting region of the semiconductor element. Preparing a plurality of insulator plates, forming through holes penetrating in the thickness direction from the surface of each of the plurality of insulator plates, and filling a conductor into the through holes;
Forming a surface wiring in a desired pattern on the surface of each of the plurality of insulator plates;
A step of applying an insulating material to the surface of each of the plurality of insulator plates and not forming the surface wiring;
Forming the wiring board having a laminated structure after laminating the plurality of insulator plates on which the surface wiring is formed and the insulating material is applied; and
And a step of mounting a semiconductor element on the wiring board.

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