JP2008241748A - Display panel, liquid crystal display device and driving circuit packaging substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make it possible to check a connection state between a display panel and a flexible packaging substrate not only in a manufacturing process but also in a using state. <P>SOLUTION: A FPC 2 has test wire parts 8, 9 on both the sides thereof. The test wire part 8 comprises wires 8a, 8b extended to the side of a display panel 1 and the test wire part 9 comprises wires 9a, 9b extended to the display panel 1 side. Further, the FPC 2 has terminals T1 to T4 respectively connected to end parts of respective wires 8a, 8b, 9a, 9b which are opposite side end parts against display panel 1 side end parts. The display panel 1 has shortcircuit wires 5, 6. The shortcircuit wire 5 short-circuits the wires 8a, 8b on a connection part between the display panel 1 and the FPC 2. Meanwhile, the shortcircuit wire 6 short-circuits the wires 9a, 9b similarly. When test signals are input to the terminals T1, T2, a connection state between the display panel 1 and the FPC 2 is predicted according to signals appearing on the terminal T2, T4. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display panel to which a wiring mounting board for mounting a wiring for supplying a signal for driving the display panel is connected, a liquid crystal display device including the display panel, and a drive in which a semiconductor integrated circuit for driving the display panel is mounted. The present invention relates to a circuit mounting board.

  2. Description of the Related Art Flat display devices such as liquid crystal display devices are widely used because they can be easily reduced in thickness. Such a display device includes a display panel including a large number of pixels. In addition, a signal for driving the pixel is supplied from the driver circuit to the display panel. This drive circuit is integrated, is provided in a mounting structure such as COF (Chip On Film), and is externally attached to the display panel. Alternatively, the drive circuit is mounted directly on the glass substrate of the display panel in the form of COG (Chip On Glass). A driving signal is supplied to the driving circuit mounted on the glass substrate through a wiring mounted on an FPC (Flexible Printed Circuit) connected to the display panel.

  In order to ensure the reliability of signal transmission to the display panel, the above-described COF and FPC need to be securely connected to the display panel. In order to improve the reliability of such connection, for example, Patent Document 1 discloses a technique for structurally reinforcing an FPC. In this FPC, the outer end portions to which stress is applied are reinforced by arranging reinforcing members that are not involved in electrical connection.

In the manufacturing process, the reliability of connection is also confirmed by inspection after the COF or FPC is connected to the display panel. In such an inspection, an indentation inspection of a connection portion is mainstream. In the indentation inspection, the state of the indentation portion due to thermocompression bonding is examined visually by an automatic machine using a microscope. More specifically, the depth and width of the indentation are analyzed using captured images.
Japanese Patent Laid-Open No. 5-183247 (published July 23, 1993)

  Flat panel display devices have come to be used as display units for various machines because of the advantage that they can be made thin. For example, the use of flat panel display devices for in-vehicle display devices and control device display devices is also being promoted. In such a field of use, a mechanical device equipped with a flat panel display device is often placed in a harsh environment. Passenger cars are exposed to environments such as vibration, high temperature, and low temperature. Also, control devices used in factories and the like are often placed in a similar environment.

  When the flat panel display device is used in such a harsh environment, stress is applied to the film substrate used in the above-described COF and FPC. For this reason, compared with the case where a flat type display apparatus is used under a normal use environment, possibility that a film base material (especially connection part with a display panel) will be damaged is high.

  By structurally reinforcing the FPC as described above, the FPC can reduce damage due to stress. However, under the severe use environment as described above, it is also conceivable that long-term stress damages the FPC due to reinforcement. As a result, when the FPC is actually damaged, the display panel may not be able to display due to disconnection. In such a situation, the operation of the passenger car and the control device is hindered.

  In addition, in the indentation inspection, the reliability of the connection can be confirmed in the manufacturing process of the display device, but it cannot be confirmed after the display device is shipped as a product. For this reason, even if the COF and FPC are likely to be damaged by stress as a result of the display device being used in the harsh environment as described above, it cannot be confirmed. Therefore, if the display device is continuously used in this state, the COF and FPC are eventually damaged, and the display panel cannot be displayed.

  The present invention has been made in view of the above problems, and its purpose is to confirm the connection state between the display panel and the flexible mounting board (COF, FPC, etc.) not only in the manufacturing process but also in use. It is to provide a structure that can.

  In order to solve the above problems, a display panel according to the present invention includes a wiring mounting board on which a signal supply wiring for supplying a signal for driving the display panel is mounted. And a first wiring and a second wiring extending to the display panel side, and a first terminal and a second terminal connected to the first wiring and the second wiring, respectively, and the display panel includes the display panel and the second wiring. It has the 1st short circuit wiring which is connected to the said 1st and 2nd wiring, respectively, and short-circuits the said 1st and 2nd wiring in the connection part with a wiring mounting board.

  In the above configuration, the first wiring and the second wiring are connected as one wiring by being connected via the first short-circuit wiring. In this state, by inputting a signal to the first terminal and confirming the state of the signal appearing at the second terminal, it is possible to predict the damage state of the wiring mounting board and the connection state between the display panel and the wiring mounting board. it can. In addition, the resistance value of the above-described wiring connected to one line is measured in advance between the first terminal and the second terminal in a normal state, and the resistance value measured in the same manner in a state that has changed over time is the normal resistance value. It can be similarly predicted by comparing with

  In the display panel, it is preferable that the first and second wirings are provided at both end portions of at least one of the wiring mounting boards. Thereby, in particular, it is possible to easily predict the damage state of both ends of the wiring mounting board which is easily stressed and the connection state between the wiring mounting board and the display panel.

  Alternatively, the display panel is connected to the wiring mounting board by interposing an intermediate board for mounting wiring that transmits signals between the wiring mounting board and the display panel. It is preferable to have the 3rd and 4th wiring which connects the 1st and 2nd wiring and the 1st short circuit wiring, respectively. The intermediate substrate is made of, for example, the above-described COF. Since the first and second wirings and the first short-circuit wiring are respectively connected by the third and fourth wirings, the first and second wirings are connected as one wiring even when the intermediate substrate is interposed. Therefore, the state of the signal input from the first terminal can be confirmed on the second terminal.

  In the display panel, the wiring mounting board includes fifth and sixth wirings extending to the intermediate board side, and third and fourth terminals connected to the fifth and sixth wirings, respectively. The intermediate board has a second short-circuit wiring that is connected to the fifth and sixth wirings at a connection portion between the intermediate board and the wiring mounting board, respectively, and short-circuits the fifth and sixth wirings. Is preferred. In this configuration, the fifth wiring and the sixth wiring are connected as a single wiring by being connected via the second short-circuit wiring. In this state, by inputting a signal to the third terminal and confirming the state of the signal appearing on the fourth terminal, the display panel can be used to show the damage state of the wiring mounting board and the connection state between the wiring mounting board and the intermediate board. This can be easily predicted based on the usage state of the mounted display device. In addition, the resistance value of the above-mentioned wiring connected to one line is measured in advance between the third terminal and the fourth terminal in a normal state, and the resistance value measured in the same manner in a state that has changed over time is the normal resistance value. It can be similarly predicted by comparing with

  In the display panel having the intermediate substrate, it is preferable that the display panel is connected to the wiring mounting substrate via the plurality of intermediate substrates. As a result, even when there are a plurality of intermediate substrates, the connection state between the wiring mounting substrate and the intermediate substrate and the connection state between the display panel and the intermediate substrate can be predicted for each intermediate substrate.

  In the display panel, it is preferable that each intermediate substrate has the pair of the fifth and sixth wirings at both end portions thereof.

  In the display panel, the wiring board is preferably a printed wiring board, and the intermediate board is preferably a mounting board on which an integrated circuit for driving the display panel is mounted on a film. As a result, it is possible to predict the connection state between the mounting board and the printed wiring board that are easily damaged by stress such as vibration applied over the long term.

  The liquid crystal display device according to the present invention includes any one of the display panels described above.

  As a result, as described above, in a use state after the liquid crystal display device is shipped as a product, a connection state between the wiring mounting board and the display panel can be predicted.

  A drive circuit mounting board according to the present invention mounts a semiconductor integrated circuit that outputs a drive signal for driving a display panel and a wiring connected to the semiconductor integrated circuit, and outputs the drive signal to the semiconductor integrated circuit. A drive circuit mounting substrate connected between the display panel and a wiring mounting substrate for mounting a signal supply wiring for supplying a signal used for the first wiring and the second wiring provided on the wiring mounting substrate; The third and fourth wirings are respectively connected to the first short-circuit wiring provided in the display panel for short-circuiting the first and second wirings.

  Since this drive circuit mounting board corresponds to the above-mentioned intermediate board, the first and second wirings and the first short-circuiting wiring are connected by the third and fourth wirings, respectively. The first and second wirings are connected as one wiring.

  It is preferable that the drive circuit mounting board has a second short-circuit wiring that is connected to the fifth and sixth wirings of the wiring mounting board and short-circuits the fifth and sixth wirings. The fifth wiring and the sixth wiring are connected as a single wiring as described above by being connected via the second short-circuit wiring.

  As described above, the display panel according to the present invention includes the first wiring and the second wiring that are connected to the display panel, and the first terminals that are connected to the first and second wirings, respectively. And a second terminal. The display panel has a first short-circuit wiring that is connected to the first and second wirings at a connection portion between the display panel and the wiring mounting board, respectively, and short-circuits the first and second wirings. Thereby, the state (the presence or absence of disconnection etc.) of the 1st wiring connected via the 1st short circuit wiring and the 2nd wiring can be checked electrically. Therefore, the damage state of the wiring mounting board and the connection state between the display panel and the wiring mounting board can be easily predicted by the use state of the display device on which the display panel is mounted.

  An embodiment of the present invention will be described with reference to FIGS. 1 to 6 as follows.

[Embodiment 1]
FIG. 1 shows a state in which an FPC 2 is connected to the display panel 1 according to the present embodiment. 2A and 2B show the display panel 1 and the FPC 2 that are not connected to each other.

  As shown in FIG. 1, on one side of the display panel 1, a plurality of driver chips 3 are mounted side by side by COG. The driver chip 3 is an integrated drive circuit, and supplies a drive signal to each pixel in order to drive a plurality of pixels included in the display panel 1. As drive signals, display data, selection signals for selecting scanning lines, and the like are prepared.

  Each driver chip 3 receives various signals according to a driving method such as a clock for controlling the timing of outputting display data and the timing of a selection signal. In order to input such a signal, a wiring pattern 4 is formed on the mounting surface of the driver chip 3 in the display panel 1. The wiring pattern 4 includes a plurality of wirings (not shown) in order to supply a plurality of signals from the FPC 2 to the driver chip 3.

  Further, on the mounting surface of the driver chip 3 in the display panel 1, short-circuit wirings 5 and 6 are formed at both ends of the portion where the driver chip 3 is disposed, respectively. The short-circuit wirings 5 and 6 will be described in detail later.

  The FPC 2 is formed by forming a wiring pattern 7 on a film substrate made of polyimide or the like. The wiring pattern 7 is provided corresponding to each driver chip 3 in order to supply the above signals to the driver chip 3, and includes a plurality of wirings (not shown) like the wiring pattern 4. Yes.

  The FPC 2 is connected to the display panel 1 by an ACF (Anisotropic Conductive Film) in a state where the connection end portion is superimposed on the connection end portion of the display panel 1. As a result, the wiring patterns 4 and 7 are electrically connected.

  Further, as shown in FIG. 2B, the FPC 2 includes test wiring portions 8 and 9. The test wiring portions 8 and 9 are formed in the vicinity of both side edges of the FPC 2 so as to sandwich all the wiring patterns 7 from both sides. The test wiring unit 8 includes two wirings 8a and 8b arranged side by side. The test wiring unit 9 includes two wirings 9a and 9b arranged side by side. One end of each of the wirings 8a, 8b, 9a, 9b extends to the connection end of the FPC 2. The other ends of the wirings 8a, 8b, 9a, 9b are connected to terminals T1 to T4 provided at the input side end of the FPC 2, respectively.

  On the other hand, as shown to Fig.2 (a), the above-mentioned short circuit wiring 5 and 6 is formed in the U shape which makes a rectangle. Both ends of the short-circuit wires 5 and 6 extend to the connection end portion of the display panel 1. Then, as shown in FIG. 1, one end of the short-circuit wiring 5 and the wiring 8a are connected, and the other end of the short-circuit wiring 5 and the wiring 8b are connected. Further, one end of the short-circuit wiring 6 and the wiring 9a are connected, and the other end of the short-circuit wiring 6 and the wiring 9b are connected. In this state, the wires 8 a and 8 b are connected to one by the short-circuit wire 5, and the wires 9 a and 9 b are connected to one by the short-circuit wire 6.

  In this state, a signal having an arbitrary waveform for testing is input to the terminals T1 and T3, and the signals appearing at the terminals T2 and T4 are monitored, so that the FPC2 is broken or the display panel 1 is connected to the FPC2. Can be predicted.

  For example, if the signals appearing at the terminals T2 and T4 have substantially the same waveform as the input signal, the test wiring sections 8 and 9 are normally transmitting signals. Therefore, it is considered that the connection between the display panel 1 and the FPC 2 is normal and that at least the portion of the FPC 2 where the test wiring portions 8 and 9 are formed is not damaged.

  When no signal appears at either or both of the terminals T2 and T4, the test wiring sections 8 and 9 where no signal appears are disconnected, or the test wiring sections 8 and 9 and the short-circuit wirings 5 and 6 There is a high possibility that the connection state with is deteriorated. Therefore, in this case, it is suspected that the edge portion (side end portion) of the FPC 2 is broken or the connection between the display panel 1 and the FPC 2 is poor.

  In addition, when the waveform of the signal appearing at one or both of the terminals T2 and T4 is duller than the waveform of the input signal, the resistance of the test wiring sections 8 and 9 due to damage to the test wiring sections 8 and 9 or the like. The value may be high.

  Further, the resistance value of the wiring path composed of the test wiring unit 8 and the short-circuit wiring 5 and the resistance value of the wiring path composed of the test wiring unit 9 and the short-circuit wiring 6 are compared with the respective resistance values at normal times measured in advance. May be. This comparison can also predict the damage state of the FPC 2 and the connection state between the display panel 1 and the FPC 2. If the resistance value of each wiring path is significantly higher than the normal value, it can be considered that each wiring path is almost disconnected. Terminals T1 to T4 can be used for measuring the resistance value.

  As described above, in the present embodiment, the display panel 1 is provided with the short-circuit wirings 5 and 6, while the FPC 2 is provided with the test wiring portions 8 and 9, and the short-circuit wirings 5 and 6 are connected to the test wiring portions 8 and 9, respectively. is doing. Further, the terminals T 1 and T 2 are connected to the end of the test wiring section 8, while the terminals T 3 and T 4 are connected to the end of the test wiring section 9. Thereby, by confirming the state of the output signal to the terminals T2 and T4 with respect to the input signal to the terminals T1 and T3, the FPC 2 is particularly stressed at both ends and the connection state between the display panel 1 and the FPC 2 Can be easily predicted in the usage state of the display device on which the display panel 1 is mounted. Further, the same prediction can be made by comparing the resistance value between the terminals T1 and T2 and the resistance value between the terminals T3 and T4 with the resistance value at the normal time.

  In the present embodiment, the configuration in which the test wiring portions 8 and 9 are provided in the vicinity of both side edges of the FPC 2 has been described. However, if the pin layout in the FPC 2 is restricted, only one of the test wiring portions 8 and 9 may be provided.

  In the present embodiment, dummy wirings 31 and 32 may be further added in the FPC 2 as indicated by a one-dot chain line in FIG. The dummy wiring 31 is disposed between the test wiring portion 8 and one side edge of the FPC 2. In addition, the dummy wiring 32 is disposed between the test wiring portion 9 and the other side edge of the FPC 2.

  The dummy wirings 31 and 32 are usually provided as independent wirings that are not electrically connected to the display panel 1 side or the external side. Such dummy wirings 31 and 32 have a function of reinforcing the FPC 2. Therefore, the strength of both side edges of the FPC 2 can be further increased.

  Further, the dummy wirings 31 and 32 may be electrically connected to the display panel 1 side or the external side as necessary.

[Embodiment 2]
FIG. 4 shows a state in which a PWB (Printed Wiring Board) 16 is connected to the display panel 11 according to the present embodiment via the COF 12. 5A and 5B show the display panel 11 and the PWB 16 that are not connected to each other.

  As shown in FIG. 3, a plurality of COFs 12 are connected side by side on one side of the display panel 11. Further, a short-circuit wiring 21 is formed at a connection portion of each COF 12 in the display panel 11. The short-circuit wiring 21 will be described in detail later.

  The COF 12 has a driver chip 13 and input and output wirings (not shown) mounted on a film substrate made of polyimide or the like. The input wiring is provided for transmitting an input signal from the PWB 16 to the driver chip 13, and the output wiring is provided for transmitting an input signal from the driver chip 13 to the display panel 11. The driver chip 13 is configured in the same manner as the driver chip 3 described above, and supplies a drive signal to each pixel in order to drive a plurality of pixels included in the display panel 11.

  As the COF 12, forms such as SOF (System On Chip) and TCP (Tape Carrier Package) are used. SOF has a structure in which a chip is mounted on a film substrate made of polyimide or the like, and in recent years, it has been widely used as a driving integrated circuit component such as a liquid crystal driver. With such a structure, the SOF can be provided with wiring at a portion where the chip is mounted, unlike the TCP where the chip is mounted in the opening of the film base. Also, unlike TCP, SOF does not have a slit that defines the bending position, and can be bent at a desired location.

  The COF 12 is provided with a test wiring section 14 and a short-circuit wiring 15. The test wiring unit 14 includes two wirings 14a and 14b arranged side by side. The wirings 14 a and 14 b are formed on one side of the driver chip 13 on the film base material of the COF 12 so as to connect the display panel 11 and the PWB 16. Further, the short-circuit wiring 15 is formed in a rectangular U shape on the other side of the driver chip 13 in the film base material of the COF 12. Both ends of the short-circuit wiring 15 extend to the connection end portion on the PWB 16 side in the COF 12.

  The display panel 11 is connected to the COF 12 by the ACF at the connection portion 22 in a state where the connection end portion is superimposed on the connection end portion of the COF 12. As a result, the aforementioned output wiring in the COF 12 and the input wiring (not shown) in the display panel 11 are electrically connected.

  Further, as shown in FIG. 4A, the above-described short-circuit wiring 21 is formed in a rectangular U-shape. Both ends of the short-circuit wiring 21 extend to the connection end of the display panel 11. As shown in FIG. 3, one end of the short-circuit wiring 21 and the wiring 14a are connected, and the other end of the short-circuit wiring 21 and the wiring 14b are connected. In this state, the wirings 14 a and 14 b are connected to one by the short-circuit wiring 21.

  The PWB 16 generates a timing signal necessary for driving the display panel 11 by a controller (not shown) mounted on the PWB 16. The PWB 16 has a wiring pattern (not shown) provided to face each COF 12. This wiring pattern includes a plurality of wirings (not shown) for transmitting a timing signal supplied to the driver chip 13 of each COF 12. The timing signal is prepared according to a driving method such as a clock for controlling the timing of outputting the display data and the timing of the selection signal, and is supplied from a controller (not shown) mounted on the PWB 16. The controller generates the timing signal based on an externally supplied clock and various pulse signals.

  The controller may be provided outside the PWB 16.

  4B, the PWB 16 includes test wirings 18 and 19, terminals TA1, TA2, TB1, and TB2, and intermediate terminals TX1, TX2, TY1, and TY2. The test wiring 18 includes a plurality of wirings 18a and 18b, an input side wiring 18c, an output side wiring 18d, and a common wiring 18e. The test wiring 19 includes a plurality of wirings 19a and 19b, an input side wiring 19c, an output side wiring 19d, and a common wiring 19e.

  A pair of wirings 18 a and 18 b is provided for each COF 12. One end of the wiring 18a is connected to the wiring 14a, and one end of the wiring 18b is connected to the wiring 14b. The input side wiring 18c connects the other end of the wiring 18b connected to the wiring 14b in the COF 12 arranged at one end (the left end in the figure) to the terminal TA1. The output side wiring 18d connects the other end of the wiring 18a connected to the wiring 14a in the COF 12 arranged at the other end (the right end in the drawing) to the terminal TA2. The common wiring 18e connects the adjacent wirings 18a and 18b between adjacent pairs.

  Similarly, a pair of wirings 19 a and 19 b is also provided for each COF 12. One end of the wiring 19 a is connected to one end of the short-circuit wiring 15, and one end of the wiring 19 b is connected to the other end of the short-circuit wiring 15. The input-side wiring 19c connects the other end of the wiring 19b connected to one end of the short-circuit wiring 15 in the COF 12 arranged at one end (left end in the drawing) to the terminal TB1. The output-side wiring 19d connects the other end of the wiring 19a connected to the other end of the short-circuit wiring 15 in the COF 12 arranged at the other end (right end in the drawing) to the terminal TB2. The common wiring 19e connects the adjacent wirings 19a and 19b between adjacent pairs.

  Further, terminals TX1 and TX2 are connected to the ends of the wirings 18a and 18b on the COF 12 side, respectively. On the other hand, terminals TY1 and TY2 are connected to the ends of the wirings 19a and 19b on the COF 12 side, respectively.

  The PWB 16 is connected to the COF 12 by the ACF at the connection portion 20 in a state where the connection end portion is superimposed on the connection end portion of the COF 12. As a result, the above-described input wiring in the COF 12 and the wiring pattern 17 are electrically connected.

  Further, the test wiring unit 14 in the COF 12 and the test wiring unit 18 in the PWB 16 are electrically connected. Specifically, the wirings 18a and 18b of the PWB 16 are connected to the wirings 14a and 14b of the corresponding COFs 12, respectively. Thereby, the test wiring part 18 forms the wiring connected with the test wiring part 14 and the short circuit wiring 21 between the terminals TA1 and TA2.

  Further, the short-circuit wiring 15 in the COF 12 and the test wiring section 19 in the PWB 16 are electrically connected. Specifically, each wiring 19a, 19b of the PWB 16 is connected to both ends of the corresponding short-circuit wiring 15 of each COF 12. Thereby, the test wiring part 19 forms the wiring connected with one between the terminals TB1 and TB2 with the short circuit wiring 15. FIG.

  In this state, a signal having an arbitrary waveform for testing is input to the terminals TA1 and TB1, and the signal appearing at the terminals TA2 and TB2 is monitored, so that the COF 12 and / or the PWB 16 are damaged, The connection state with the COF 12 and the connection state between the COF 12 and the PWB 16 can be predicted.

  For example, if the signals appearing at the terminals TA2 and TB2 have substantially the same waveform as the input signal, the test wiring sections 14, 18, and 19 are normally transmitting signals. Therefore, it is considered that the connection between the display panel 11 and the COF 12 and the connection between the COF 12 and the PWB 16 are normal, and that at least the test wiring portions 14, 18, and 19 of the COF 12 and the PWB 16 are not damaged. .

  When the signal does not appear only at the terminal TA2, the test wiring portions 14 and 18 themselves are disconnected, the connection state between the test wiring portion 18 and the test wiring 14, or / and the connection between the test wiring portion 14 and the short wiring 21. It is likely that the condition has deteriorated. Therefore, in this case, the edge portion of the COF 12 (end portion on the arrangement side of the test wiring portion 14) is damaged, or the connection failure between the COF 12 and the PWB 16 or / and the connection failure between the display panel 11 and the COF 12 is suspected.

  When no signal appears only at the terminal TB2, it is highly possible that the test wiring 19 is disconnected or the connection state between the test wiring section 19 and the short-circuit wiring 15 is deteriorated. Therefore, in this case, damage to the edge portion of COF 12 (arrangement side end portion of short-circuit wiring 19) or poor connection between COF 12 and PWB 16 is suspected.

  When the waveform of the signal appearing only at the terminal TA2 is duller than the waveform of the input signal, there is a possibility that the resistance values of the test wiring sections 14 and 18 are high due to damage to the test wiring sections 14 and 18 or the like. is there. If the waveform of the signal appearing only at the terminal TB2 is duller than the waveform of the input signal, the resistance value of the test wiring section 19 may be high due to damage to the test wiring section 19 or the like.

  Further, the resistance value of the wiring path composed of the test wiring sections 14 and 18 and the short-circuit wiring 21 and the resistance value of the wiring path composed of the test wiring section 19 and the short-circuit wiring 15 are respectively measured as normal resistance values. You may compare. Also by this comparison, it is possible to predict the damaged state of the COF 12, the connection state between the display panel 11 and the COF 12, and the connection state between the COF 12 and the PWB 16. If the resistance value of each wiring path is significantly higher than the normal value, it can be considered that each wiring path is almost disconnected. Terminals TA1, TA2, TB1, and TB2 can be used for measuring the resistance value.

  Further, by measuring the resistance value between the terminals TX1 and TX2 and the resistance value between the terminals TY1 and TY2, each COF 12 may be damaged in each part as described above or may be defective in connection in each connection part. Sex can be confirmed.

  Thus, in the present embodiment, the short wiring 21 is provided on the display panel 11, the test wiring portion 14 and the short wiring 15 are provided on the COF 12, the test wiring portion 18 and the short wiring 21 are connected, and the test wiring portion is provided. 18 and the short-circuit wiring 15 are connected. Further, the terminals TA 1 and TA 2 are connected to the end of the test wiring section 18, while the terminals TB 1 and TB 2 are connected to the end of the test wiring section 19. Accordingly, by confirming the state of the output signal to the terminals TA2 and TB2 with respect to the input signal to the terminals TA1 and TB1, the damaged state of the COF 12, the connection state between the display panel 11 and the COF 12, and the connection state between the COF 12 and the PWB 16 Can be easily predicted in the usage state of the display device on which the display panel 11 is mounted. Further, the same prediction can be made by comparing the resistance value between the terminals TA1 and TA2 and the resistance value between the terminals TB1 and TB2 with the resistance value at the normal time.

  Here, a modification of the present embodiment will be described. FIG. 5 is a plan view showing the modification.

  In this modification, as shown in FIG. 5, a display panel 23, a COF 24, and a PWB 25 are provided.

  The COF 24 has the same configuration as the COF 12 except that it further includes a test wiring section 26. The test wiring portion 26 is arranged closer to the side end portion than the above-described short-circuit wiring 15 in the COF 12, and includes two wirings 26a and 26b arranged side by side.

  The display panel 23 has the same configuration as the display panel 11 except that the display panel 23 further includes a short-circuit wiring 27. The short-circuit line 27 is provided in the same manner as the short-circuit line 21 so as to short-circuit each of the lines 26a and 26b.

  The PWB 25 has the same configuration as the COF 12 except that it further includes a test wiring section 28. The test wiring unit 28 includes wirings 28a and 28b and a wiring group 28c. The test wiring unit 28 is connected to the test wiring unit 26 so that the test wiring unit 18 has the same relationship as the connection to the test wiring unit 14. ing. Further, the test wiring 26 has terminals TZ1 and TZ2 having functions equivalent to those of the terminals TX1 and TX2 described above for each COF 12.

  In the above configuration, by using a wiring path formed by the test wirings 26 and 28 and the short-circuit wiring 27, an electrical test using a signal using the wiring path formed by the test wirings 14 and 18 and the short-circuiting wiring 21 described above. And resistance value measurement tests can be performed. Therefore, breakage of both ends of the COF 24 which is easily stressed, the connection state between the display panel 23 and the COF 24 and / or the connection state between the COF 24 and the PWB 25 are used when the display device equipped with the configuration of this modification is used. Can be predicted.

  In the present embodiment, the configuration in which the test wiring portion 14 and the short-circuit wiring 15 are provided in the vicinity of both side edges of the COFs 12 and 24 has been described. However, when there is a restriction on the pin layout in the COFs 12 and 24, only one of the test wiring unit 14 and the short-circuit wiring 15 may be provided.

  Further, in the present embodiment, dummy wirings 41 and 42 may be further added in the COFs 12 and 24, as indicated by a one-dot chain line in FIGS. The dummy wiring 41 is disposed between the test wiring section 14 and one side edge of the COFs 12 and 24. Further, the dummy wiring 42 is disposed between the short-circuit wiring 15 and the other side edge of the COFs 12 and 24.

  The dummy wirings 41 and 42 are usually provided as independent wirings that are not electrically connected to the display panel 11 or 23 side or the external side. Such dummy wirings 41 and 42 have a function of reinforcing the COFs 12 and 24. Therefore, the strength of both side edges of the COFs 12 and 24 can be further increased.

  Further, the dummy wirings 41 and 42 may be electrically connected to the display panels 11 and 23 side or the PWBs 16 and 25 side as necessary.

[Embodiment 3]
FIG. 6 shows a configuration of the liquid crystal display device 101 according to the present embodiment.

  As shown in FIG. 6, the liquid crystal display device 101 includes a liquid crystal display panel 102, a plurality of source drivers 103, a plurality of gate drivers 104, and a controller 105.

  The liquid crystal display panel 102 includes a plurality (m × i) of gate bus lines G11 to Gmi, a plurality (n × j) of source bus lines S11 to Snj, and a plurality of pixels PIX.

  In the following description, the gate bus lines G11 to Gmi will be referred to as the gate bus line G when appropriate. In addition, when the source bus lines S11 to Snj are described as a representative, they are appropriately referred to as source bus lines S.

  The pixel PIX is arranged in the vicinity where the gate bus line G and the source line S intersect. The pixel PIX includes a thin film transistor (hereinafter simply referred to as a transistor) on the glass substrate of the liquid crystal display panel 102 and a display element DE.

  The gate of the transistor is connected to the gate bus line G, the source is connected to the source bus line S, and the drain is connected to a pixel electrode (not shown). A common voltage is applied to a common electrode (not shown) arranged to face the pixel electrode. A display element is composed of the pixel electrode, the common electrode, and the liquid crystal between the two electrodes.

  The gate bus lines G11 to Gmi, the source bus lines S11 to Snj, the transistor, and the pixel electrode are formed on a glass substrate. The common electrode is formed on a glass substrate provided to face the glass substrate. A liquid crystal is filled between the glass substrates (between the pixel electrode and the common electrode).

  The n source drivers 103 are provided, transfer the start pulse SSP to the shift register at the timing of the source clock signal SCK, and correspond to the display data Dx at the timing of the timing pulse output from each output stage of the shift register. The position of the source bus line S is held. The source driver 103 takes in the held display data Dx into the latch at the timing of the latch signal LS and outputs it to the j source bus lines S.

  The gate driver 104 is provided with m pieces, and the start pulse GSP is transferred to the shift register at the timing of the gate clock signal GCK, and the gate pulse is generated by the timing pulse output from each output stage of the shift register to generate i gate pulses. Output to the gate bus line G.

  The controller 105 generates control signals such as a start pulse SSP, a source clock signal SCK, and a latch signal LS to be supplied to the source driver 103, and outputs the input display data Dx to the source driver 103. The controller 105 generates control signals such as a start pulse GSP and a gate clock signal GCK to be given to the gate driver 104.

  In the liquid crystal display device 101 described above, the liquid crystal display panel 102 is configured by the display panel 1, 11 or 23 described above. The source driver 103 and the gate driver 104 are configured by the driver chip 3 in the display panel 1, the COF 12 in the display panel 11, or the COF 24 in the display panel 23. Therefore, when the liquid crystal display panel 102 is configured by the display panel 1, the FPC 2 is connected to the liquid crystal display panel 102. Further, when the liquid crystal display panel 102 is configured by the display panel 11, the PWB 16 is connected to the liquid crystal display panel 102. When the liquid crystal display panel 102 is configured by the display panel 23, the PWB 25 is connected to the liquid crystal display panel 102.

  As described above, when the liquid crystal display device 101 is mounted with the display panel 1, 11, or 23, the FPC 2 or the PWB 16 or 25 may be damaged particularly at both ends, the liquid crystal display panel 102, the FPC 2 or the PWB 16 or 25, The connection state of the liquid crystal display device 101 can be easily predicted.

  In the present embodiment, it has been described that the display panel 1 of the first embodiment or the display panels 11 and 23 of the second embodiment are mounted on the liquid crystal display device 101. However, the display panels 1, 11, and 23 may be mounted on other display devices such as an organic LE display and a plasma display as long as they can be driven using a driver chip.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims. That is, embodiments obtained by combining technical means appropriately changed within the scope of the claims are also included in the technical scope of the present invention.

  Since the display panel of the present invention can predict the damaged state of the flexible substrate on which the signal wiring is mounted by checking the energization state of the signal wiring to the drive circuit even in the use state, the display for in-vehicle use It can be suitably used for an apparatus.

It is a top view which shows the display panel which concerns on Embodiment 1 of this invention, and FPC connected to this. (A) is a top view which shows the structure of the said display panel, (b) is a top view which shows the structure of the said FPC. It is a top view which shows the display panel which concerns on Embodiment 2 of this invention, and PWB connected to this. (A) is a top view which shows the structure of the display panel of FIG. 3, (b) is a top view which shows the structure of PWB of FIG. 10 is a plan view showing a configuration of a modified example of Embodiment 2. FIG. FIG. 6 is a block diagram illustrating a configuration of a liquid crystal display device according to a third embodiment.

Explanation of symbols

1, 11, 23 Display panel 2 FPC (wiring mounting board)
3,13 Driver chip (semiconductor integrated circuit)
4, 7, 17 Wiring pattern (signal supply wiring)
5, 6, 21 Short-circuit wiring (first short-circuit wiring)
7 Wiring pattern 8, 9 Test wiring part 8a, 9a Wiring (first wiring)
8b, 9b wiring (second wiring)
12, 24 COF (intermediate substrate, drive circuit mounting substrate)
16, 25 PWB (wiring mounting board)
14 Test wiring section 14a Wiring (third wiring)
14b Wiring (fourth wiring)
18, 28 Test wiring section 18a, 28a wiring (first wiring)
18b, 28b wiring (second wiring)
19 Test wiring part 19a Wiring (5th wiring)
19b Wiring (sixth wiring)
102 Liquid crystal display panel (display panel)
T1, T3 terminals (first terminal)
T2, T4 terminals (second terminal)
TX1, TZ1 terminals (first terminal)
TX2, TZ2 terminals (second terminal)
TY1 terminal (third terminal)
TY2 terminal (4th terminal)

Claims (10)

In a display panel to which a wiring mounting board for mounting a signal supply wiring for supplying a signal for driving the display panel is connected,
The wiring mounting substrate has a first wiring and a second wiring extending to the display panel side, and a first terminal and a second terminal connected to the first wiring and the second wiring, respectively.
The display panel has a first short-circuit wiring that is connected to the first and second wirings at a connection portion between the display panel and the wiring mounting board, respectively, and short-circuits the first and second wirings A display panel characterized by   The display panel according to claim 1, wherein the first and second wirings are provided on at least one side end of the wiring mounting substrate. It is connected to the wiring mounting board by interposing an intermediate board for mounting wiring that transmits signals between the wiring mounting board and the display panel,
The display panel according to claim 1, wherein the intermediate substrate has third and fourth wirings that connect the first and second wirings and the first short-circuiting wiring, respectively. The wiring mounting board has a fifth wiring and a sixth wiring extending to the intermediate board side, and a third terminal and a fourth terminal connected to the fifth wiring and the sixth wiring, respectively.
The intermediate board has a second short-circuit wiring that is connected to the fifth and sixth wirings at a connection portion between the intermediate board and the wiring mounting board, respectively, and shorts the fifth and sixth wirings. The display panel according to claim 1, wherein:   The display panel according to claim 3, wherein the display panel is connected to the wiring mounting substrate via a plurality of the intermediate substrates.   6. The display panel according to claim 4, wherein each intermediate substrate has the pair of the fifth and sixth wirings at both end portions thereof. The wiring mounting board is a printed wiring board,
The display panel according to claim 3, wherein the intermediate substrate is a mounting substrate on which an integrated circuit for driving the display panel is mounted on a film.   A liquid crystal display device comprising the display panel according to claim 1. A signal supply for mounting a semiconductor integrated circuit for outputting a drive signal for driving a display panel and a wiring connected to the semiconductor integrated circuit, and supplying a signal used for outputting the drive signal to the semiconductor integrated circuit In a drive circuit mounting board connected between a wiring mounting board for mounting wiring and the display panel,
Third and fourth wirings connecting the first wiring and the second wiring provided on the wiring mounting substrate and the first short-circuiting wiring provided on the display panel for short-circuiting the first and second wirings, respectively. A drive circuit mounting board having wiring.   10. The drive circuit mounting according to claim 9, further comprising a second short-circuit wiring that is connected to each of the fifth and sixth wirings of the wiring mounting board and short-circuits the fifth and sixth wirings. substrate.

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