JP2008225046A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device capable of increasing the number of SFs without increasing storage capacity of SF memories which stores SF data of N SFs (subfields). <P>SOLUTION: When pixel data for one frame is repeatedly read for k times by every frame by setting speed in reading in a frame memory into k times of that in writing, N pieces of SF data are generated from the pixel data for one frame by the first to the k-th reading and supplied to the SF memories. The SF memories are the k pieces of the first to the k-th bank memories each of which can store the SF data for one frame and each of which writes the SF data for one frame generated by the first to the k-th reading by the frame memory. During writing, pieces of the SF data are set to reading state in order from the one in which writing for one frame is all terminated by the first to the k-th bank memories and each pixel of each corresponding SF is set to a lighting state or a lighting out state by the SF data read from the bank memories for reading. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device having an image memory for storing an input video signal for each frame.

  Currently, as a thin display device, a plasma display device equipped with a plasma display panel (hereinafter referred to as PDP) in which a plurality of discharge cells each containing a discharge gas are arranged in a matrix has been commercialized. Yes. In the plasma display device, driving based on the subfield method is performed on the PDP, thereby expressing various intermediate luminance levels corresponding to the input video signal.

  In driving based on the subfield method, a display period of one field or one frame (hereinafter referred to as a unit display period) is divided into N subfields each assigned a different light emission period, and each subfield is divided. In addition, the following operation is performed. That is, first, each discharge cell is selectively discharged (selective discharge) in accordance with the input video signal, thereby setting each discharge cell to one of the lighting mode and the extinguishing mode (address process). Next, only the discharge cells set in the lighting mode are subjected to the sustain discharge over the light emission period assigned to the subfield, and the light emission state associated with the sustain discharge is maintained (sustain process). By such driving, intermediate luminance corresponding to the total period of the sustain discharge generated in each subfield within the unit display period is visually recognized. That is, various intermediate luminances can be expressed by the number of gradations corresponding to the number of subfields provided in the unit display period.

  Here, in order to realize the above driving, there has been proposed a plasma display device equipped with a frame memory for storing an input video signal for each frame, a pixel driving data generation circuit, and a memory for storing pixel driving data. (See FIG. 1 of Patent Document 1). The pixel drive data generation circuit is configured to generate pixel drive data (hereinafter referred to as “light-off mode” or “light-off mode”) in the address process of each subfield based on the video signal read from the frame memory. (Referred to as subfield data). Each bit of the subfield data corresponds to each subfield within one frame display period. Therefore, in a memory for storing subfield data (hereinafter referred to as subfield memory), after subfield data is written for one frame, each subfield corresponds to the subfield within the next frame display period. Bits are read separately from the subfield data. At this time, since the subfield data corresponding to the next frame is supplied even while the read operation is being performed, two subfield memories are actually provided to write the subfield data. That is, while one subfield memory is performing the read operation as described above, the other subfield memory is made to write the subfield data corresponding to the next frame.

  By the way, when intermediate luminance is expressed based on the subfield method, the number of gradations of intermediate luminance that can be expressed can be increased as the number of subfields provided for each unit display period is increased.

However, according to the driving as described above, when the number of subfields is increased, the number of bits of the subfield data is increased by the increase, and the storage capacity of the subfield memory for storing the subfield data is increased. occured.
JP 2005-266709 A

  It is an object of the present invention to provide a display device that can increase the number of subfields per unit display period without increasing the storage capacity of a subfield memory that stores subfield data.

  The display device according to claim 1 is a display device that drives each pixel of the display panel to emit light in each of a plurality of subfields for each frame according to an input video signal, and for each pixel based on the input video signal. Is read out from the frame memory, and the frame memory is repeatedly read k times per frame at a speed equal to or higher than k times the display rate on the display panel (k: an integer of 2 or more). Sub-field data for generating N-bit (N: integer greater than or equal to 2) sub-field data indicating which of the sub-fields each of the pixels is set to be turned on or off based on the pixel data. Field data generation means and subfield data generated based on the first reading from the frame memory. The first to Q bits (1 <Q <N) are sequentially written, and each time one frame is written, the first to Q bits are arranged in the first to Qth in each frame, respectively. A first bank memory to be read as address data bits corresponding to each of the subfields, and (Q + 1) to Rth bits (Q + 1) to R bits (in the subfield data generated based on the second read from the frame memory). Q <R ≦ N) is sequentially written and every time one frame is written, the (Q + 1) to Rth bits are arranged in (Q + 1) to Rth in each frame, respectively. A second bank memory that reads out as address data bits corresponding to each field; and a subfield memory that includes each pixel according to the address data bits. Having an address means for setting one of the state of the on and off state.

  The display device according to claim 3 is a display device that drives each pixel of the display panel to emit light in each of a plurality of subfields for each frame according to the input video signal, and each of the display devices based on the input video signal. The pixel data for each pixel is written, and the subfield is read based on the pixel data read from the frame memory and the frame memory that is read twice every frame at a speed twice as fast as the writing. Sub-field data generating means for generating N-bit (N: integer greater than or equal to 2) sub-field data indicating whether each of the pixels is set to the on or off state, and from the frame memory The first to (N / 2) bits in the subfield data generated based on the first reading are sequentially written to one Each time a frame is written, each of the first to (N / 2) bits corresponds to each of the first to (N / 2) th subfields in each frame. The first bank memory to be read as address data bits and the (1 + N / 2) to Nth bits in the subfield data generated based on the second reading from the frame memory are sequentially written for one frame. Each time data is written, the (1 + N / 2) -th to N-th bits are address data bits corresponding to the (1 + N / 2) -th to Nth subfields in each frame, respectively. A sub-field memory including a second bank memory to be read as the pixel data, and each of the pixels is set to one of a lighted state and a lighted state according to the address data bit It has a dress means.

  According to a fourth aspect of the present invention, there is provided a display device in which each pixel of the display panel is divided into N stages of the first gradation to the (th) in N (N: integer of 2 or more) subfields for each frame in the input video signal. N + 1) A display device that drives to emit light at a luminance level corresponding to each gradation, and writes pixel data for each pixel based on the input video signal, which is k times the display rate on the display panel (k: 2 or more). A frame memory that is repeatedly read k times for each frame at a speed equal to or higher than the integer), and the first to (N + 1) th gradations are P based on the pixel data read from the frame memory. Based on subfield data generation means for generating subfield data represented by bits (P: integer greater than or equal to 2 and less than N), and first reading from the frame memory Based on the subfield data formed, the first floor representing the first to Qth gradations (2 <Q <N) with R bits (R: an integer of 2 or more and less than P) The key division data is generated, and from the (Q + 1) th gradation to the Sth gradation (Q <S ≦ N + 1) based on the subfield data generated based on the second reading from the frame memory. The gradation dividing means for generating second gradation division data representing R in the R bit, and the written first gradation each time the first gradation division data is written and one frame is written. The first bank memory that reads the divided data as the first read gradation divided data and the second gradation divided data are written, and the written second gradation divided data is written each time one frame is written. Second readout gradation A subfield memory including a second bank memory to be read as data, and addresses corresponding to the first to Qth subfields in each frame based on the first readout gradation division data Address data for generating data bits and generating address data bits corresponding to the (Q + 1) th to Nth subfields in each frame based on the second readout gradation division data Conversion means; and address means for setting each of the pixels to one of a lighting state and a non-lighting state in accordance with the address data bit.

  In the display device according to the present invention, first, pixel data for one frame is repeatedly read k times for each frame by setting the reading speed in the frame memory to k times the display rate (an integer of 2 or more). At this time, the pixels are turned on and off in each of the N subfields based on the pixel data for one frame by the first reading, the second reading,..., The kth reading. The subfield data indicating which state is to be set is generated and supplied to the subfield memory. The subfield memory is composed of k first to kth bank memories each capable of storing subfield data for one frame. At this time, each of the first to kth bank memories writes subfield data corresponding to pixel data for one frame by the first reading to the kth reading by the frame memory as follows.

  First bank memory: Only the bit group corresponding to the first to qth subfields in the subfield data corresponding to the first read is written.

  Second bank memory: Only bit groups corresponding to the (q + 1) th to rth subfields in the subfield data corresponding to the second reading are written.

  Third bank memory: Only bit groups corresponding to the (r + 1) th to sth subfields in the subfield data corresponding to the third reading are written.

・
・
・
K-th bank memory: Only a bit group corresponding to the w-th to N-th subfields in the subfield data corresponding to the k-th reading is written.

{Q <r <s <, ..., <w <N}
During this period, the first to k-th bank memories are set to the read state in order from the one in which writing for one frame is completed, and the subfield data read from the bank memory to be read is set. Based on the subfield data, each pixel is set to one of the on and off states. According to such a configuration, it is possible to increase the number of subfields for each frame without significantly increasing the storage capacity of the subfield memory.

  FIG. 1 is a diagram showing a schematic configuration of a plasma display device as an example of a display device according to the present invention.

In FIG. 1, a PDP 10 as a plasma display panel includes a front transparent substrate and a rear substrate (not shown) disposed to face each other with a discharge space in which a discharge gas is sealed. Row electrodes X _{1 to} X _n and row electrodes Y _{1 to} Y _n are formed on the front transparent substrate so as to extend in the horizontal direction (horizontal direction) of the two-dimensional screen. These row electrodes X ₁ to X _n and row electrodes Y ₁ to Y _n, respectively a pair of row electrodes X _i and Y _i: by (i 1 to n), plays a first to n-th display line in the PDP10 Yes. On the back substrate, the column electrodes D are arranged to extend in the vertical direction of the two-dimensional display screen so as to cross the row electrodes X _{1 to} X _n and the row electrodes Y _{1 to} Y _n, respectively. ₁ to D _m are formed. A discharge cell (display cell) P as a pixel is formed at the intersection of each row electrode pair (X, Y) and the column electrode D including the discharge space. That is, the PDP 10 includes (n × m) discharge cells including discharge cells P _{(1,1) in the} first row / first column to discharge cells P _{(n, m) in} the n-th row / m-th column. P is arranged in a matrix.

A / D converter 1, by sequentially sampling in accordance with an input video signal to the sampling clock CK _S of a predetermined frequency, the pixel data PD representing the luminance level in 8 bits, for example for each pixel (a discharge cell P) The converted data is supplied to the frame memory 2. That is, the A / D converter ₁ performs pixel data PD _{(1,1) to} PD _{(n )} corresponding to the discharge cells P _{(1,1) to} P _{(n, m)} as pixels for each frame. _{, m)} are sequentially supplied to the frame memory 2.

The frame memory 2 sequentially writes, the written pixel data PD respectively each frame in accordance with each of the pixel data _{PD (1,1) ~PD (n,} m) to the sampling clock CK _S (PD _{(1 , 1) to} PD _{(n, m)} ) are repeatedly read k times and supplied to the SF (subfield) data generation circuit 3. Detailed write and read operations of the frame memory 2 will be described later.

The SF data generation circuit 3 first performs multi-gradation processing including error diffusion processing and dither processing on the pixel data PD sequentially read out from the frame memory 2 to thereby generate multi-gradation pixel data. Get PDS. In such multi-gradation processing, in order to express the luminance level represented by the pixel data PD in units of pixel blocks composed of a plurality of adjacent pixels, multi-gradation pixel data corresponding to each pixel in the pixel block. Find PDS. Next, based on the multi-gradation pixel data PDS, the SF data generation circuit 3 determines whether the discharge cell P is set to either the lighting mode or the non-lighting mode in each of the subfields SF1 to SF14 as shown in FIG. 14-bit SF (subfield) data GD is generated for each bit digit. That is, for example, the first bit of the SF data GD corresponds to the subfield SF1, the second bit corresponds to SF2, the third bit corresponds to SF3,..., And the 14th bit corresponds to SF14. The SF data GD representing one of the lighting mode and the extinguishing mode is generated according to the logic level of the digit. The SF data generation circuit 3 supplies each of SF data GD _{(1,1) to} GD _{(n, m)} generated for each pixel (discharge cell P) to the SF memory 4.

The SF memory 4 sequentially writes each of the SF data GD _{(1,1) to} GD _{(n, m)} . Here, when the writing of the SF data GD _{(1,1) to} GD _{(n, m)} corresponding to each pixel of the first row, the first column to the n-th row and the m-th column is completed, The SF memory 4 performs the following read operation.

First, the SF memory 4 separates and reads out only the first bit of each of the SF data GD _{(1,1) to} GD _{(n, m)} written in the subfield SF1 as shown in FIG. SF1 address data bits DB _{(1,1) to} DB _{( n, m)} are supplied to the address driver 6. Next, the SF memory 4 separates and reads out only the second bit of each of the SF data GD _{(1,1) to} GD _{(n, m)} in the subfield SF2 as shown in FIG. Data bits DB _{(1,1) to} DB _{( n, m)} are supplied to the address driver 6. Next, the SF memory 4 separates and reads out only the third bit of each of the SF data GD _{(1, 1) to} GD _{(n, m)} in the subfield SF3 as shown in FIG. Data bits DB _{(1,1) to} DB _{( n, m)} are supplied to the address driver 6. Similarly, in the SF memory 4, the bit digits corresponding to the subfield from each of the SF data GD _{(1,1) to} GD _{(n, m) in} each of the subfields SF4 to SF14 as shown in FIG. Bits are read out separately and supplied to the address driver 6 as SF4 to SF14 address data bits DB, respectively.

  The drive control circuit 20 supplies various control signals (to be described later) for controlling writing and reading of the frame memory 2 and the SF memory 4 to the frame memory 2 and the SF memory 4.

Further, the drive control circuit 20 generates various control signals for driving the PDP 10 in accordance with the light emission drive sequence shown in FIG. 2 and supplies it to the panel driver including the address driver 6, the X electrode driver 7, and the Y electrode driver 8. . That is, the drive control circuit 20 supplies the panel driver with various control signals to be sequentially driven according to the address process W and the sustain process I in each of the subfields SF1 to SF14 as shown in FIG. Note that the drive control circuit 20 supplies various control signals to be driven in accordance with the reset process R to the panel driver prior to the address process W only in the first subfield SF1. The panel driver, that is, the address driver 6, the X electrode driver 7, and the Y electrode driver 8 generate various drive pulses in accordance with various control signals supplied from the drive control circuit 20 to generate column electrodes D and row electrodes X of the PDP 10. And Y. First, in the reset process R of the first subfield SF1, the X electrode driver 7 and the Y electrode driver 8 apply a reset pulse to all the row electrodes X _{1 to} X _n and the row electrodes Y _{1 to} Y _n . In response to the application of the reset pulse, reset discharge is generated in all the discharge cells P, and a predetermined amount of wall charges are formed in all the discharge cells P. Thereby, all the discharge cells P are initialized to the state of lighting mode. In the address process W of each of the subfields SF1 to SF14, the address driver 6 generates a pixel data pulse having a pulse voltage corresponding to the logic level of the SF address data bit DB supplied from the SF memory 4. For example, the address driver 6 generates a pixel data pulse of a high voltage when the SF address data bit DB is a logic level 1 and a low voltage when the SF address data bit DB is a logic level 0. Then, the address driver 6 sequentially applies the pixel data pulses to the column electrodes D _{1 to} D _m as a pixel data pulse group DP for each display line (m). Further, in the address process W, the Y electrode driver 8 sequentially applies the scan pulse SP to the row electrodes Y ₁ to Y _n at the same timing as the application timing of each pixel data pulse group DP. At this time, discharge (erase address discharge) is selectively generated only in the discharge cell P at the intersection of the row electrode to which the scan pulse is applied and the column electrode to which the high-voltage pixel data pulse is applied. Wall charges remaining in P are erased. That is, the discharge cell P that has lost the wall charge is set to the extinguishing mode. On the other hand, the discharge cell P in which no erase address discharge has been generated maintains the state immediately before that, that is, the lighting mode or the extinguishing mode. Further, the sub-field SF1~SF14 each sustain process I, X electrode driver 7 and the Y electrode driver 8 alternately to the row electrodes X ₁ to X _n and Y ₁ to Y _n, the luminance of the subfield SF The sustain pulse is repeatedly applied as many times as the number corresponding to the weight. Only the discharge cell P in which the wall charges remain due to the application of the sustain pulse, that is, the discharge cell P in the lighting mode is subjected to the sustain discharge every time the sustain pulse is applied, and the sustain discharge. The light emission state associated with is maintained.

  By driving as described above, the luminance corresponding to the total number of sustain discharges generated in one frame display period is visually recognized.

  Here, in carrying out the above drive, the drive control circuit 20 operates each of the frame memory 2 and the SF memory 4 as follows.

First, the frame memory 2, as shown in FIG. 3, each of the pixel data _{PD (1,1) ~PD (n,} m) in response to the sampling clock CK _S, written respectively to the address corresponding to each pixel . Further, the frame memory 2 performs the following reading every time writing of each ½ frame of pixel data PD is completed for each frame. That is, the frame memory 2, as shown in FIG. 3, the sampling clock CK in response to the clock CK _RD having a frequency twice that of _S, the pixel data PD _{(1, 1} written to the address corresponding to each pixel _{) To} PD _{(n, m)} are read out and supplied to the SF (subfield) data generation circuit 3 (first reading). When the first reading is completed, the frame memory 2 sequentially reads each of the written pixel data PD _{(1,1) to} PD _{(n, m)} sequentially according to the clock CK _RD to generate SF data. Supply to the circuit 3 (second read). That is, the frame memory 2, the writing for each frame display period for one frame of the pixel data _{PD (1,1) ~PD (n,} m) to the clock CK _RD having twice the frequency of the sampling clock CK _S Accordingly, the reading operation to be sequentially read out is executed twice in succession as shown in FIG.

Accordingly, the SF data generation circuit 3 causes the SF data GD _{(1,1) to} GD _{( n, n, m)} based on the pixel data PD _{(1,1) to} PD _{(n, m)} read from the frame memory 2 _{. m)} are sequentially generated and supplied to the SF memory 4, and again SF data GD _{(1,1) to} GD _{( n, m)} based on each of the pixel data PD _{(1,1) to} PD _{(n, m)} are obtained. The data is sequentially supplied to the SF memory 4.

  FIG. 4 is a diagram showing an internal configuration of the SF memory 4.

  As shown in FIG. 4, the SF memory 4 includes bit blocking circuits 41 and 42, a first bank memory 43, a second bank memory 44, a selector 45, and a PS (parallel / serial) conversion circuit 46. .

The bit block forming circuit 41 separates the first to seventh bits in each of the SF data GD _{(1,1) to} GD _{(n, m)} each having 14 bits, and separates the same bit digits. The block data for every 8 pixels is supplied to the first bank memory 43 as the following bit block data B1 to B7.

B1: 8-bit data in which only the first bit in GD is blocked every 8 pixels B2: 8-bit data in which only the second bit in GD is blocked every 8 pixels B3: The first bit in GD 8-bit data that blocks only 3 bits every 8 pixels B4: 8-bit data that blocks only 4th bit in GD every 8 pixels B5: 8 pixels that only 5th bit in GD 8-bit data blocked every minute B6: 8-bit data obtained by blocking only the 6th bit in GD every 8 pixels B7: Only 7th bit in GD was blocked every 8 pixels 8-bit data That is, the bit blocking circuit 41 converts the SF data GD into bit block data B1 to B7 for each pixel block (for 8 pixels) and supplies the converted data to the first bank memory 43. It is. The bit block data B1 to B7 correspond to the subfields SF1 to SF7 shown in FIG.

First bank memory 43, write enable signal BK1W and the address AD1 supplied from the drive control circuit 20, and in response to the clock CK _RD, writes the bit block data B1 to B7. That is, the first bank memory 43, only while the write enable signal BK1 of logic level 1 is supplied, the bit block data B1~B7 each for each pixel block in accordance with a clock CK _RD, the address AD1 Write to the address specified by. The first bank memory 43, read enable signal BK1R and the address AD1 supplied from the drive control circuit 20, and in response to the clock CK _AD, supplied to a selector 45 reads out the already written the bit block data B1~B7 To do. That is, the first bank memory 43 reads the bit block written at the address specified by the address AD1 according to the clock CK _AD only while the read enable signal BK1R of logic level 1 is supplied. Data B1 to B7 are read and supplied to the selector 45.

The bit block forming circuit 42 separates the 8th to 14th bits in each of the SF data GD _{(1,1) to} GD _{(n, m)} each having 14 bits, and separates the same bit digits. The data divided into blocks for every 8 pixels is supplied to the second bank memory 44 as the following bit block data B8 to B14.

B8: 8-bit data in which only the 8th bit in the GD is blocked every 8 pixels B9: 8-bit data in which only the 9th bit in the GD is blocked every 8 pixels B10: The 8th data in the GD 8-bit data that blocks only 10 bits every 8 pixels B11: 8-bit data that blocks only the 11th bit in GD every 8 pixels B12: 8 pixels only in the 12th bit in GD 8-bit data blocked every minute B13: 8-bit data obtained by blocking only the 13th bit in GD every 8 pixels B14: Only 14th bit in GD was blocked every 8 pixels 8-bit data That is, the bit blocking circuit 42 converts the SF data GD into bit block data B8 to B14 for each pixel block (for 8 pixels) and supplies the converted data to the second bank memory 44. That. The bit block data B8 to B14 correspond to the subfields SF8 to SF14 shown in FIG.

Second bank memory 44, write enable signal BK2W and address AD2 supplied from the drive control circuit 20, and in response to the clock CK _RD, writes the bit block data B8～B14. That is, the second bank memory 44, only while the write enable signal BK2 of logic level 1 is supplied, the bit block data B8~B14 each for each pixel block in accordance with a clock CK _RD, the address AD2 Write to the address specified by. The second bank memory 44 reads the written bit block data B8 to B14 in accordance with the read enable signal BK2R, the address AD2, and the clock CK _AD supplied from the drive control circuit 20, and supplies them to the selector 45. To do. That is, the second bank memory 44 reads the bit block written at the address specified by the address AD2 according to the clock CK _AD only while the read enable signal BK2R of logic level 1 is supplied. Data B8 to B14 are read and supplied to the selector 45.

The selector 45 converts the bit block data B read from one of the first bank memory 43 and the second bank memory 44 in accordance with the bank memory selection signal _SBK supplied from the drive control circuit 20 into a PS conversion circuit. 46. For example, the selector 45 supplies the bit block data B1~B7 read from the first bank memory 43 to the PS conversion circuit 46 in the case of the bank memory selection signal S _BK logic level 1 is supplied. On the other hand, when the bank memory selection signal S _BK logic level 0 is supplied, the selector 45 supplies the bit block data B8~B14 read from the second bank memory 44 to the PS conversion circuit 46.

  The PS conversion circuit 46 converts each 8-bit bit block data B1 to B7 or B8 to B14 supplied from the selector 45 from the 8-bit parallel form into the 1-bit serial form, and the SF address data bit DB Is supplied to the address driver 6.

  Hereinafter, the internal operation of the SF memory 4 performed according to the control from the drive control circuit 20 will be described with reference to FIGS.

In accordance with the SF data GD _{(1,1) to} GD _{( n, m)} by the first reading from the frame memory 2, first, the bit block forming circuits 41 and 42 respectively generate bit block data as shown in FIG. B1 to B7 and B8 to B14 are supplied to the first bank memory 43 and the second bank memory 44, respectively.

That is, the bit blocking circuit 41 is a bit block obtained by blocking the first to seventh bits in each of the SF data GD _{(1,1) to} GD _{( n, m) for} every eight pixels with the same bit digits. Data B1 _{1 to} B7 ₁ , B1 _{2 to} B7 ₂ , B1 _{3 to} B7 ₃ ,..., B1 _{f to} B7 _f are sequentially supplied to the first bank memory 43. The bit block data B1 ₁ is, SF data GD ₍₁ corresponding to each pixel in the first pixel group of eight pixels corresponding to the first row and the first column to the first row and the eighth column, _{respectively, 1) to} GD _(1,8) 8-bit data constructed by combining only the first bits. The bit block data B2 ₁ is of 8 bits which is constructed by combining only SF data GD _(1,1) ~GD _(1,8) the second bit of each corresponding to each pixel of the inner first pixel group It is data. The bit block data B1 ₂ was the second pixel group adjacent to the first pixel group, i.e. corresponding respectively to the eight pixels corresponding to the first row and the ninth column to the first row and the 16th column respectively SF This is 8-bit data constructed by combining only the first bits of the data GD _{(1,9) to} GD _{( 1,16)} . The bit block data B1 _f is the SF data corresponding to the last f-th pixel group, that is, eight pixels corresponding to the nth row / (m-7) column to the nth row / mth column, respectively. This is 8-bit data constructed by combining only the first bits of GD _{(n, m-7) to} GD _{(n, m)} . The bit block data B7 _f was constructed the first f respectively to each pixel in the pixel group s the corresponding SF data _{GD (n, m-7)} ~GD (n, m) by combining only the seventh bit of each 8-bit data.

On the other hand, during this time, the bit blocking circuit 42 blocks the 8th to 14th bits in each of the SF data GD _{(1,1) to} GD _{( n, m) for} every 8 pixels in the same bit digits. Bit block data B8 _{1 to} B14 ₁ , B8 _{2 to} B14 ₂ , B8 _{3 to} B14 ₃ ,..., B8 _{f to} B14 _f are sequentially supplied to the second bank memory 44. The bit block data B8 ₁ is, SF data GD ₍₁ corresponding to each pixel in the first pixel group of eight pixels corresponding to the first row and the first column to the first row and the eighth column, _{respectively, 1) to} GD _(1,8) 8-bit data constructed by combining only the eighth bits of each. The bit block data B9 ₁ is of 8 bits which is constructed by combining only SF data GD _(1,1) ~GD _(1,8) 9th bits of each corresponding to each pixel of the inner first pixel group It is data. The bit block data B8 ₂ was the second pixel group adjacent to the first pixel group, i.e. corresponding respectively to the eight pixels corresponding to the first row and the ninth column to the first row and the 16th column respectively SF Data GD _{(1,9) to} GD _{( 1,16)} is 8-bit data constructed by combining only the eighth bits of each. The bit block data B8 _f is SF data corresponding to the last f-th pixel group, that is, eight pixels corresponding to the nth row / (m-7) column to the nth row / mth column, respectively. It is 8-bit data constructed by combining only the eighth bits of GD _{(n, m-7) to} GD _{(n, m)} . The bit block data B14 _f was constructed the first f respectively to each pixel in the pixel group s the corresponding SF data _{GD (n, m-7)} ~GD (n, m) by combining only the first 14 bits of each 8-bit data.

While the drive control circuit 20 is supplying the first block memory 43 and the second bank memory 44 with the bit block data B1 to B14 obtained by the first reading by the frame memory 2 as described above, A logic level 1 write enable signal BK1W to be written only to the first bank memory 43 in the memory is supplied. In response to the write enable signal BK1W, the first bank memory 43 selects B1 to B7 (B1 _{1 to} B7 ₁ , B1) out of the bit block data B1 to B14 obtained by the first reading by the frame memory 2. _{2 to} B7 ₂ , B1 _{3 to} B7 ₃ ,..., B1 _{f to} B7 _f ) are sequentially written as shown in FIG. Here, 1 if all the frames of the bit block data B1~B7 (B1 ₁ ~B7 _f) is written to the first bank memory 43, from the frame memory 2, SF data GD ₍₁ by the second reading _{, 1) to} GD _{(n, m)} are supplied to the bit blocking circuits 41 and 42. At this time, similarly to the operation as described above, the bit block forming circuits 41 and 42 are arranged so that the bit block based on the SF data GD _{(1,1) to} GD _{(n, m)} by the second reading from the frame memory 2 is performed. Data B 1 to B 7 and B 8 to B 14 are supplied to the first bank memory 43 and the second bank memory 44.

Here, while the bit block data B1 to B14 obtained by the second reading from the frame memory 2 are being supplied, the drive control circuit 20 writes the logic level 1 write enable signal to be written. BK2W is supplied to the second bank memory 44. In response to the logic level 1 write enable signal BK2W, the second bank memory 44 uses B8 to B14 of the bit block data B1 to B14 obtained by the second reading from the frame memory 2 as described above. _{(B8 1 ~B14 1, B8 2} ~B14 2, B8 3 ~B14 3, ···, B8 f ~B14 f) only write sequentially, as shown in FIG.

In addition, while the bit block data B1 to B14 obtained by the second reading from the frame memory 2 as described above are supplied, the drive control circuit 20 writes the logic level 0 to stop writing. The enable signal BK1W is supplied to the first bank memory 43. Thus, the first bank memory 43 is to stop the writing operation, as shown in FIG. 3, while this first bit block data obtained by the second reading B1 ₁ ~ B7 _f is supplied over, and stores and holds the bit block data B1 ₁ ~ B7 _f of one frame obtained by the first-time readout from the frame memory 2. Further, during this period, the drive control circuit 20 outputs the read enable signal BK1R at the logic level 1 for executing the read operation over the execution period of the address process W of each of the subfields SF1 to SF7 as shown in FIG. The address AD1 to be read as follows is supplied to the first bank memory 43. That is, in response to the address AD1 and the read enable signal BK1R at the logic level 1, the first bank memory 43 performs the following operation in the address process W of SF1 to SF7.
SF1: bit block data B1 ₁ ~B1 _f
SF2: Bit block data B2 _{1 to} B2 _f
SF3: Bit block data B3 _{1 to} B3 _f
SF4: bit block data B4 ₁ ~B4 _f
SF5: bit block data B5 ₁ ~B5 _f
SF6: bit block data B6 ₁ ~B6 _f
SF7: bit block data B7 ₁ ~B7 _f
Each bit block data B is sequentially read out.

That is, for example, in the address process W of the subfield SF1, the first bank memory 43 has a bit block obtained by blocking the first bit of each of the SF data GD _{(1,1) to} GD _{(n, m)} every 8 pixels. sequentially reading data B1 ₁ ~ B1 _f respectively. Further, in the address process W of the subfield SF2, the first bank memory 43 stores the bit block data obtained by blocking the second bit of each of the SF data GD _{(1,1) to} GD _{(n, m)} every 8 pixels. Each of B2 _{1 to} B2 _f is read sequentially.

Further, the drive control circuit 20 supplies the bit block data B1 to B1 read from the first bank memory 43 while the read enable signal BK1R having the logic level 1 as described above is being supplied to the first bank memory 43. A bank memory selection signal _SBK of logic level 1 to be supplied to the PS conversion circuit 46 is supplied to the selector 45.

Thus, PS conversion circuit 46, first, the SF1 address obtained by converting from a sequential 8-bit parallel form the bit block data B1 ₁ ~ B1 _f respectively read from the first bank memory 43 to 1 bit serial form Data bits DB _{(1,1) to} DB _{( n, m)} are supplied to the address driver 6. Next, the PS conversion circuit 46 sequentially converts each of the bit block data B2 _{1 to} B2 _f read from the first bank memory 43 from the 8-bit parallel form into the 1-bit serial form, and the SF2 address data bits. DB _{(1,1) to} DB _{( n, m)} are supplied to the address driver 6. Next, the PS conversion circuit 46 sequentially converts each of the bit block data B3 _{1 to} B3 _f read from the first bank memory 43 from the 8-bit parallel form into the 1-bit serial form, and the SF3 address data bits. DB _{(1,1) to} DB _{( n, m)} are supplied to the address driver 6. Next, PS conversion circuit 46, SF4 address data bits obtained by converting from a sequential 8-bit parallel form the bit block data B4 ₁ -B4 _f respectively read from the first bank memory 43 to 1 bit serial form DB _{(1,1) to} DB _{( n, m)} are supplied to the address driver 6. Next, PS conversion circuit 46, SF5 address data bits obtained by converting from a sequential 8-bit parallel form the bit block data B5 ₁ to B5 _f respectively read from the first bank memory 43 to 1 bit serial form DB _{(1,1) to} DB _{( n, m)} are supplied to the address driver 6. Next, the PS conversion circuit 46 sequentially converts each of the bit block data B6 _{1 to} B6 _f read from the first bank memory 43 from the 8-bit parallel form into the 1-bit serial form, and the SF6 address data bit. DB _{(1,1) to} DB _{( n, m)} are supplied to the address driver 6. Next, the PS conversion circuit 46 sequentially converts each of the bit block data B7 _{1 to} B7 _f read from the first bank memory 43 from the 8-bit parallel form into the 1-bit serial form, and the SF7 address data bits. DB _{(1,1) to} DB _{( n, m)} are supplied to the address driver 6.

Here, the second bank memory 44, when all bit blocks data B8 ₁ ~B14 _f of one frame obtained by the second reading by the frame memory 2 ends the writing, the drive control circuit 20, a write A write enable signal BK2W having a logic level 0 to be stopped is supplied to the second bank memory 44 as shown in FIG. Further, during this period, the drive control circuit 20 outputs the read enable signal BK2R of the logic level 1 for executing the read operation over the execution period of the address process W of each of the subfields SF8 to SF14 as shown in FIG. The address AD2 to be read as follows is supplied to the second bank memory 44. That is, in response to the address AD2 and the logic level 1 read enable signal BK2R, the second bank memory 44 determines that the address process W of each of SF8 to SF14 is as follows.
SF8: bit block data B8 ₁ ~B8 _f
SF9: bit block data B9 ₁ ~B9 _f
SF10: Bit block data B10 _{1 to} B10 _f
SF11: Bit block data B11 _{1 to} B11 _f
SF12: Bit block data B12 _{1 to} B12 _f
SF13: Bit block data B13 _{1 to} B13 _f
SF14: Bit block data B14 _{1 to} B14 _f
Each bit block data B is sequentially read out.

That is, for example, in the address process W of the subfield SF8, the second bank memory 44 is configured to block the eighth bit of each of the SF data GD _{(1,1) to} GD _{(n, m)} every 8 pixels. sequentially reading data B8 _{1-B8 f} respectively. In the address process W of the subfield SF9, the second bank memory 44 stores bit block data in which the ninth bit of each of the SF data GD _{(1,1) to} GD _{(n, m)} is blocked every 8 pixels. B9 _{1 to} B9 _f are read sequentially.

Further, the drive control circuit 20 supplies the second bank memory 44 with the read enable signal BK2R having the logic level 1 as described above, while reading the bit block data B8˜B8 read from the second bank memory 44. A bank memory selection signal _SBK of logic level 0 to be supplied to the PS conversion circuit 46 is supplied to the selector 45.

Thus, PS conversion circuit 46, first, SF8 address obtained by converting from a sequential 8-bit parallel form the bit block data B8 _{1-B8 f} respectively read from the second bank memory 44 to 1 bit serial form Data bits DB _{(1,1) to} DB _{( n, m)} are supplied to the address driver 6. Next, PS conversion circuit 46, SF9 address data bits obtained by converting from a sequential 8-bit parallel form the bit block data B9 ₁ ~B9 _f respectively read from the second bank memory 44 to 1 bit serial form DB _{(1,1) to} DB _{( n, m)} are supplied to the address driver 6. Next, the PS conversion circuit 46 sequentially converts each of the bit block data B10 _{1 to} B10 _f read from the second bank memory 44 from an 8-bit parallel form into a 1-bit serial form, and SF10 address data bits. DB _{(1,1) to} DB _{( n, m)} are supplied to the address driver 6. Next, the PS conversion circuit 46 sequentially converts each of the bit block data B11 _{1 to} B11 _f read from the second bank memory 44 from the 8-bit parallel form into the 1-bit serial form, and the SF11 address data bits. DB _{(1,1) to} DB _{( n, m)} are supplied to the address driver 6. Next, the PS conversion circuit 46 sequentially converts each of the bit block data B12 _{1 to} B12 _f read from the second bank memory 44 from an 8-bit parallel form into a 1-bit serial form, and SF12 address data bits. DB _{(1,1) to} DB _{( n, m)} are supplied to the address driver 6. Next, the PS conversion circuit 46 sequentially converts each of the bit block data B13 _{1 to} B13 _f read from the second bank memory 44 from the 8-bit parallel form into the 1-bit serial form, and the SF13 address data bits. DB _{(1,1) to} DB _{( n, m)} are supplied to the address driver 6. Next, the PS conversion circuit 46 sequentially converts each of the bit block data B14 _{1 to} B14 _f read from the second bank memory 44 from an 8-bit parallel form into a 1-bit serial form, and SF14 address data bits. DB _{(1,1) to} DB _{( n, m)} are supplied to the address driver 6.

  As described above, in the plasma display device shown in FIG. 1, the frame memory 2 that stores pixel data for each pixel based on the input video signal in units of frames and whether each pixel is set to the on or off mode. The SF memory 4 storing SF data for each subfield is controlled to be written and read as shown in FIG.

  According to the writing and reading control, the frame memory 2 sequentially writes the pixel data PD for each pixel, and sequentially reads each written pixel data PD at a speed twice the writing speed (first When all the reading for one frame is completed, the pixel data PD for one frame is sequentially read again at a speed twice the writing speed (second reading). That is, the frame memory 2 repeatedly reads out each of the written pixel data PD twice for each frame as shown in FIG.

  At this time, each of the pixel data read from the frame memory 2 as described above is turned on and off by the SF data generation circuit 3 for each subfield (SF1 to SF14). Is converted to SF data GD indicating which state is set, and is supplied to the SF memory 4. In this embodiment, each bit digit (first to fourteenth bits) of the SF data GD corresponds to each subfield (SF1 to SF14), and a pixel in each subfield depends on the logical level of the bit. Is set to the lighting mode or the extinguishing mode.

  The first bank memory 43 of the first bank memory 43 and the second bank memory 44 that carry the SF memory 4 is generated based on the pixel data PD for each pixel read out in the frame memory 2 for the first time. The upper bit group (first to seventh bits) of each SF data GD is sequentially written. On the other hand, the second bank memory 44 has a lower bit group (eighth to fourteenth bits) of each SF data GD generated based on the pixel data PD for each pixel read out in the frame memory 2 for the second time. Are written sequentially. Here, when the first bank memory 43 has written all the upper bits of each SF data GD for one frame, the first bank memory 43 has been written over the period during which the second bank memory 44 performs the above-described writing. The upper bit group (first to seventh bits) in the SF data GD is separated for each bit digit, and the bit group for each bit digit corresponds to each subfield of the first half subfield group (SF1 to SF7). Read with. At this time, the data read from the first bank memory 43 is supplied to the address driver 6 as SF address data bits DB corresponding to each subfield of the first half subfield group (SF1 to SF7). When the first bank memory 43 finishes reading all of one frame, the second bank memory 44 stores the written data, that is, the lower bit group (eighth to fourteenth bits) in the SF data GD. Each bit digit is separated, and a bit group for each bit digit is read at a timing corresponding to each subfield of the latter half subfield group (SF8 to SF14). At this time, the data read from the second bank memory 43 is supplied to the address driver 6 as the SF address data bit DB corresponding to each subfield of the latter half subfield group (SF8 to SF14).

  According to the writing and reading control of the image memory (the frame memory 2 and the SF memory 4) as described above, a memory capable of storing one frame of data having a bit number that is ½ of the number of subfields as a subfield memory. It is sufficient to prepare two (first bank memory 43 and second bank memory 44).

  Therefore, according to the present invention, as compared with a conventional display device that requires two bank memories capable of storing one frame of data having the same number of bits as the number of subfields as a subfield memory, the subfield memory It is possible to reduce the storage capacity. In particular, if the present invention is applied to a display device equipped with a frame memory for image processing such as interlace / progressive conversion processing, the memory capacity can be greatly reduced.

  In the above embodiment, the operation of the frame memory 2 having a storage capacity of one frame has been described. However, the frame memory 2 has a storage capacity of M frames (M is an integer of 2 or more). You may make it use a thing.

  For example, when the frame memory 2 having a recording capacity for two frames is adopted, the SF memory 4 includes a third bank memory (not shown) together with the first bank memory 43 and the second bank memory 44 as shown in FIG. Adopt one with. At this time, the frame memory 2 first sequentially writes pixel data for each pixel based on the input video signal in the first one-frame storage area. Here, when all the pixel data for one frame is written in the first one-frame storage area, the frame memory 2 then shifts to writing to the second one-frame storage area. During this time, the frame memory 2 repeatedly reads out the pixel data for one frame already written in the first one-frame storage area at a speed three times that at the time of writing three times. The first bank memory 43 writes the upper bit group in the SF data obtained by the first reading of the pixel data by the frame memory 2. The second bank memory 44 writes the middle bit group in the SF data obtained by the second reading of the pixel data by the frame memory 2. Then, the third bank memory writes a lower bit group in the SF data obtained by the third reading of the pixel data by the frame memory 2. At this time, within one frame display period, the first bank memory 43 reads each bit digit in the upper bit group in the SF data as an SF address data bit corresponding to each subfield of the first subfield group. Subsequently, the second bank memory 44 reads each bit digit in the middle bit group in the SF data as SF address data bits corresponding to each subfield in the middle half subfield group. Further, within this one-frame display period, the third bank memory reads out each bit digit in the lower bit group in the SF data as an SF address data bit corresponding to each subfield in the latter subfield group.

  Here, if each of these three bank memories is a memory capable of storing data of Q bits (Q: integer of 2 or more) for one frame, each frame is constructed by at least (3 × Q) subfields. It becomes possible to do.

  In short, first, pixel data for one frame is repeatedly read k times for each frame by setting the reading speed in the frame memory to k times the writing speed (an integer of 2 or more). At this time, subfield data based on the pixel data is generated for each frame of pixel data by the first reading, the second reading,... Supply to field memory. The subfield memory is composed of k first to kth bank memories each capable of storing Q-bit data for one frame. At this time, each of the first to kth bank memories writes subfield data corresponding to pixel data for one frame by the first reading to the kth reading by the frame memory as follows.

  First bank memory: Only the first to Qth bits in the subfield data corresponding to the first reading are written.

  Second bank memory: Only the (Q + 1) to (2Q) bits in the subfield data corresponding to the second reading are written.

  Third bank memory: Only the (2Q + 1) to (3Q) bits in the subfield data corresponding to the second reading are written.

・
・
・
K-th bank memory: Only the (N + 1-Q) to N-th bits in the subfield data corresponding to the k-th reading are written.

  During this period, the first to kth bank memories are set in the reading state in order from the one in which writing for one frame is completed, and the data written to each bit digit is separated. Are read as SF address data bits.

  That is, k is capable of storing (N / k) bits of data for one frame while repeatedly reading data k times, with the reading speed in the frame memory 2 being k times the writing speed. Each bank memory is controlled to be written and read as described above.

  In the above embodiment, the number of bits in the subfield data to be written to each of the first to kth bank memories is the same number of bits (Q), but it is not necessarily the same. In short, each of the first to k-th bank memories uses k to 1st to N-th bits of subfield data corresponding to pixel data for one frame from the first reading to the k-th reading by the frame memory. The bit group divided into pieces (not necessarily equal division) may be individually written as follows.

  First bank memory: Only the first to qth bits in the subfield data corresponding to the first reading are written.

  Second bank memory: Only the (q + 1) -th to r-th bits in the subfield data corresponding to the second reading are written.

  Third bank memory: Only the (r + 1) -th to s-th bits in the subfield data corresponding to the second reading are written.

・
・
・
K-th bank memory: write only w-th bit to N-th bit in subfield data corresponding to the k-th reading.

{Q <r <s <, ..., <w <N}
At this time, even if the number of write (read) bits in each bank memory is different, bank memories having the same storage capacity may be used. That is, a bank memory capable of storing one frame of data having a bit number greater than or equal to [rounded up value of (N / k)] and less than [2N / number of memory banks] is prepared. For example, when the number of bits of the subfield data is 14 bits, when reading is performed twice for each frame with the reading speed of the frame memory 2 being twice the writing speed, 10 bits of data are stored in one frame. Control is performed as follows using the first and second bank memories capable of storing the minute amount. That is, the first bank memory writes the first to tenth bits in the subfield data corresponding to the first read, and the second bank memory writes the first field in the subfield data corresponding to the second read. Control is performed to write the 11th to 14th bits. At this time, as the subfield memory, it is only necessary to have two bank memories capable of storing 10 bits of data for one frame, so that each of the same number of bits as the number of subfields, that is, 14 bits of data can be stored The storage capacity of the subfield memory can be reduced as compared with a conventional display device that requires two bank memories.

  In the above embodiment, the number of repeated readings for subfield data for one frame in the frame memory 2 is k, and the bit group (N bits) in this subfield data is set to k bank memories. Each divided bit group is distributed and written.

  However, if the number of bank memories is two or more, k is not necessarily required, and the number of bank memories is less than k.

  For example, when the reading speed in the frame memory 2 is three times the writing speed and the number of repeated readings for subfield data for one frame is three, the number of bank memories is two. good.

  At this time, the frame memory 2 is actually composed of two first and second frame memories for alternately supplying pixel data (N bits) supplied for each pixel for each frame. For example, when the pixel data group corresponding to the second frame is supplied following the pixel data group corresponding to the first frame, first, the first frame memory writes the pixel data group corresponding to the first frame. Next, the second frame memory writes a pixel data group corresponding to the second frame. During this time, the first frame memory repeatedly reads out the pixel data group corresponding to the first frame written as described above successively three times at a speed three times the writing speed. Then, after the third reading by the first frame memory is completed, the second frame memory successively reads out the pixel data group corresponding to the second frame successively three times at a speed three times the writing speed. .

  Then, the sub-field data based on the pixel data for the pixel data for one frame by the first reading, the second reading, and the third reading from the frame memory are respectively generated in the SF data generation circuit 3. Generated and sequentially supplied to the subfield memory. Here, the subfield memory is composed of two first and second bank memories each capable of storing (N / 3) -bit data for one frame.

  First, at the time of the first reading by the frame memory, the first bank memory writes only the first to (N / 3) bits in the subfield data corresponding to the first reading.

  Next, at the time of the second reading by the frame memory, the second bank memory writes the (1 + N / 3) to (2N / 3) bits in the subfield data corresponding to the second reading. Then, the first bank (N / 3) bits written in the first bank memory are separated for each bit digit and read as SF address data bits.

  Next, at the time of the third read by the frame memory, the first bank memory writes the (1 + 2N / 3) to Nth bits in the subfield data corresponding to the third read and the second bank. A bit obtained by separating the (1 + N / 3) -th bit to (2N / 3) -th bit in which the memory has been written is read as an SF address data bit.

  Next, at the time of the first reading for the next frame by the frame memory, the second bank memory writes only the first to (N / 3) bits in the subfield data corresponding to the first reading. At the same time, the above-described (1 + 2N / 3) to Nth bits written in the first bank memory are read out as SF address data bits.

  Next, at the time of the second reading for the next frame by the frame memory, the first bank memory has the (1 + N / 3) bit to (2N / 3) th bit in the subfield data corresponding to the second reading. In addition to writing only the bits, the first bank (N / 3) bits already written in the second bank memory are read out as SF address data bits separated for each bit digit.

  Next, at the time of the third reading for the next frame by the frame memory, the second bank memory writes the (1 + 2N / 3) to Nth bits in the subfield data corresponding to the third reading and Then, the above-described (1 + N / 3) to (2N / 3) bits, which have been written in the first bank memory, are read out as SF address data bits, separated for each bit digit.

  According to such memory control, when the display panel is driven in gradation by N subfields, two bank memories each capable of storing (N / 3) bit data for one frame are used as subfield memories. It will be good if you prepare. Therefore, the storage capacity of the subfield memory can be reduced as compared with a conventional display device that requires two bank memories capable of storing N bits of data for one frame.

  In the above embodiment, the number of bank memories used when the number of repeated readings for each frame in the frame memory 2 is k is set to k or less than k, but the number is (2.k If it is less than k, more than k bank memories may be used. In other words, if the number of bank memories capable of storing (N / k) bits of data for one frame is less than (2.k), each bank memory capable of storing data of N bits for one frame. This is because the memory capacity can be reduced with respect to the conventional display device that requires two.

  In the above embodiment, the first to Nth bits of the subfield data are divided into k bit groups so as not to overlap each other, and each is assigned to the first to kth bank memories for writing. However, at least one bit of the division boundary portion may be written to be overlapped in different bank memories.

  FIG. 5 is a diagram showing another configuration of the SF memory 4 made in view of this point.

In FIG. 5, the bit blocking circuit 41a separates the first to eighth bits in each of the SF data GD _{(1,1) to} GD _{(n, m)} each consisting of 14 bits for each bit digit, and the same. The data obtained by blocking the bit digits every 8 pixels is supplied to the first bank memory 43a as bit block data B1 to B8 as shown in FIG. 6 or FIG. The bit blocking circuit 42a separates the seventh to fourteenth bits in each of the SF data GD _{(1,1) to} GD _{( n, m)} for each bit digit, and blocks the same bit digits for every eight pixels. The converted data is supplied to the second bank memory 44a as bit block data B7 to B14 as shown in FIG. 6 or FIG.

  In response to the write enable signal BK1W supplied from the drive control circuit 20, the first bank memory 43a sequentially writes the bit block data B1 to B7 to the address specified by the address AD1 supplied from the drive control circuit 20. . That is, as shown in FIG. 6 or FIG. 7, the first bank memory 43a sequentially writes the bit block data B1 to B8 for each pixel block only while the write enable signal BK1W of logic level 1 is supplied. . In addition, the first bank memory 43a has the bit block data B1 written at the address specified by the address AD1 supplied from the drive control circuit 20 in response to the read enable signal BK1R supplied from the drive control circuit 20. ˜B8 are read and supplied to the selector 45. That is, the first bank memory 43a sequentially reads the already written bit block data B1 to B8 as shown in FIG. 6 or FIG. 7 only while the logical level 1 read enable signal BK1R is supplied. 45.

  In response to the write enable signal BK2W supplied from the drive control circuit 20, the second bank memory 44a sequentially writes the bit block data B7 to B14 to the address specified by the address AD2 supplied from the drive control circuit 20. . That is, as shown in FIG. 6 or FIG. 7, the second bank memory 44a sequentially writes the bit block data B7 to B14 for each pixel block only while the write enable signal BK2W of logic level 1 is supplied. . Further, the second bank memory 44a receives the bit block data B7 written at the address specified by the address AD2 supplied from the drive control circuit 20 in response to the read enable signal BK2R supplied from the drive control circuit 20. ˜B14 are read and supplied to the selector 45. That is, the second bank memory 44a stores the already written bit block data B7 to B14 as shown in FIG. 6 or 7 only while the logical level 1 read enable signal BK2R is supplied. 7 are sequentially read and supplied to the selector 45.

At this time, the drive control circuit 20 supplies the bank memory selection signal S _BK as shown in FIG. 6 or 7 to the selector 45.

Bank memory selection signal S _BK shown in Figure 6, while during the first bank memory 43a is read out bit block data B1 to B8, and the second bank memory 44a is read out bit block data B7 and B8 The logic level is 1 and the logic level is 0 while the second bank memory 44a is reading the bit block data B9 to B14. Therefore, at this time, the SF memory 4 outputs the bit block data B1 to B8 read from the first bank memory 43a as SF1 to SF8 address data bits DB, respectively, and the bit read from the second bank memory 44a. Block data B9 to B14 are output as SF9 to SF14 address data bits DB, respectively.

On the other hand, the bank memory selection signal S _BK is logic level 1, the first bank memory 43a the bit block data B7 and B8 first bank memory 43a is over while reading the bit block data B1~B6 shown in FIG. 7 , And while the second bank memory 44a is reading the bit block data B7 to B14, the logic level is 0. Therefore, at this time, the SF memory 4 outputs the bit block data B1 to B6 read from the first bank memory 43a as the SF1 to SF6 address data bits DB, respectively, and the bit read from the second bank memory 44a. Block data B7 to B14 are output as SF7 to SF14 address data bits DB, respectively.

  As described above, in the SF memory 4 shown in FIG. 5, B1 to B8 of the bit block data B1 to B14 are written to the first bank memory 43a, and the bit block data B7 to B14 are written to the second bank memory 44a. I try to make it. That is, the bit block data B7 and B8 are written redundantly in both the first bank memory 43a and the second bank memory 44a. According to such a configuration, the bit block data B7 and B8 corresponding to the SF7 and SF8 address data bits DB are read from the first bank memory 43a as shown in FIG. 6 or as shown in FIG. Any one read from the two-bank memory 44a may be used. Therefore, the selector 45 for switching the read output of each of the first bank memory 43a and the second bank memory 44a, as shown in FIG. 6 or FIG. 7, from the start of reading the bit block data B7 by the first bank memory 43a, The switching may be performed within a period TU until the end of reading the bit block data B8 by the bank memory 44a.

  FIG. 8 is a diagram showing a schematic configuration of a plasma display device as another example of the display device according to the present invention.

  The A / D converter 1, the frame memory 2, the address driver 6, the X electrode driver 7, the Y electrode driver 8 and the PDP 10 perform the same operations as those shown in FIG. A description of the operation is omitted.

  Here, in the plasma display device shown in FIG. 8, the PDP 10 is driven to emit light in accordance with a light emission drive sequence as shown in FIG. In the light emission drive sequence shown in FIG. 9, the operations (reset process R, address process W, and the like) performed in each subfield except that the total number of subfields is 13 (SF1 to SF13). The sustain process I) is the same as that shown in FIG. At this time, the drive control circuit 20 drives each of the discharge cells P to emit light in one of 14 light emission patterns corresponding to each of the first to 14th gradations as shown in FIG. 10 according to the light emission drive sequence. . In other words, the drive control circuit 20 applies, for each discharge cell P of the PDP 10, an address process W of one subfield (indicated by a black circle) corresponding to the gradation of the luminance level to be expressed as shown in FIG. Only the panel driver is controlled to cause the erase address discharge. As a result, since the discharge cell P transitions to the extinguishing mode, the discharge cell initialized to the lighting mode in the reset process R of the first subfield SF1 is in a period until this erase address discharge is generated. Each existing subfield (indicated by a white circle) enters the lighting mode state, and sustain discharge is continuously generated in these subfields. According to the light emission drive sequence as shown in FIG. 9, the opportunity to change the discharge cell from the extinguishing mode to the lighting mode within one frame (or one field) display period is the reset process of the first subfield SF1. Only R. Therefore, the discharge cells in which the erase address discharge is generated after SF1 and set to the extinguishing mode maintain this extinguishing mode state until the last subfield SF13. Therefore, according to the light emission drive pattern shown in FIG. 10, the luminance corresponding to the number of subfields existing between the first subfield SF1 and the subfield where the first erase address discharge occurs is visually recognized. Therefore, intermediate luminance of 14 gradations is expressed by 13 subfields SF1 to SF13.

  In FIG. 8, the SF data generation circuit 31 performs the following data conversion and multi-gradation processing on the pixel data PD (8 bits) repeatedly read from the frame memory 2 for each frame.

  That is, first, the SF data generation circuit 31 converts 8-bit pixel data PD representing the luminance level for each pixel in 256 gradations, and sets the luminance level for each pixel according to the conversion characteristics as shown in FIG. It is converted into 8-bit converted pixel data HD represented by 8 bits and 224 gradations. That is, the SF data generation circuit 31 prevents generation of luminance saturation due to multi-gradation processing and generation of a flat portion of display characteristics that occurs when the display gradation is not at the bit boundary (that is, generation of gradation distortion). Therefore, conversion processing according to the conversion characteristics shown in FIG. 11 is performed on the pixel data PD in advance.

  Next, the SF data generation circuit 31 performs multi-gradation processing including error diffusion processing and dither processing on the converted pixel data HD. For example, in the error diffusion process, first, the upper 6 bits of the converted pixel data HD are regarded as display data, and the remaining lower 2 bits are regarded as error data. Then, the weighted addition of each error data of the converted pixel data HD corresponding to each peripheral pixel is reflected in the display data. With this operation, the luminance for the lower 2 bits in the original pixel is expressed in a pseudo manner by the peripheral pixels, and therefore, the display data for 6 bits smaller than 8 bits is equivalent to the pixel data for 8 bits. Brightness gradation expression is possible. Then, dither processing is performed on the 6-bit error diffusion processing pixel data obtained by the error diffusion processing. In the dither processing, a plurality of adjacent pixels are set as one pixel unit, and dither coefficients each having a different coefficient value are allocated and added to the error diffusion processing pixel data corresponding to each pixel in the one pixel unit. To obtain dither-added pixel data. According to the addition of the dither coefficients, when viewed in units of one pixel, it is possible to express a luminance corresponding to 8 bits even with only the upper 4 bits of the dither addition pixel data. Therefore, the SF data generation circuit 31 uses the upper 4 bits in the dither addition pixel data as SF (subfield) data GD indicating the first to fourteenth gradations as shown in FIG. Supply to circuit 32.

  The SF data gradation division circuit 32 converts the 4-bit SF data GD into the 3-bit gradation division SF data QD1 or QD2 in accordance with the gradation division conversion processing according to the read count signal RN supplied from the drive control circuit 20. The converted data is supplied to the SF memory 40. The number-of-reads signal RN is the number of times the SF data GD supplied to the SF data gradation dividing circuit 32 is read out among the k times of repeated reading operations for each frame by the frame memory 2. It shows whether it is a thing. For example, when the frame memory 2 repeatedly reads out the pixel data PD twice for each frame, the drive control circuit 20 performs the first reading of the frame memory 2 as shown in FIG. At the time of the first reading and the second reading, the reading number signal RN indicating “2” is supplied to the SF data gradation dividing circuit 32. At this time, when the read count signal RN indicates “1”, the SF data gradation dividing circuit 32 converts the 4-bit SF data GD into 3 bits according to the gradation division conversion table shown in FIG. Conversion to gradation-division SF data QD1. That is, for the SF data GD corresponding to the first reading, if the value indicates less than the eighth gradation, 3-bit data in which only the most significant bit is omitted from the SF data GD is gradation. The divided SF data QD1 is used, and in any case where the 8th to 14th gradations are indicated, the 3-bit invalid data [111] is set as the gradation divided SF data QD1. That is, in the gradation divided SF data QD1, the first to seventh gradations from the first gradation to the 14th gradation are substantially represented by 3-bit data [000] to [110]. is there. On the other hand, when the read count signal RN indicates “2”, the SF data gradation dividing circuit 32 converts the 4-bit SF data GD into a 3-bit scale according to the gradation division conversion table shown in FIG. Conversion to key division SF data QD2. That is, for the SF data GD corresponding to the second reading, in any case, when the value indicates less than the eighth gradation, the 3-bit invalid data [000] is converted into the gradation divided SF. When the data QD is represented by the eighth to the 14th gradations, the three-bit data [001] to [111] indicating the seven gradations are defined as the gradation-division SF data QD2. That is, in the gradation divided SF data QD2, the eighth to fourteenth gradations among the first gradation to the fourteenth gradation are substantially represented by the 3-bit data [001] to [111]. .

  Here, according to the light emission drive pattern as shown in FIG. 10, light emission drive of the first to seventh gradations is performed in the first half SF1 to SF7 of the subfields SF1 to SF13, and in the latter half SF8 to SF13. The light emission drive of the 8th gradation to the 14th gradation is performed. That is, in the first half driving (SF1 to SF7), driving corresponding to the 8th to 14th gradations is not performed in the first place, so that the SF data GD indicating each of the 8th to 14th gradations is not used. Can make this invalid (expressed in [111]). Therefore, in the driving of the first half, the number of bits of SF data for designating one of the first to seventh gradations may be 3 bits. On the other hand, in the second half driving (SF8 to SF13), driving corresponding to the first to seventh gradations is not performed, so that SF data GD indicating each of the first to seventh gradations is not used. This can be invalidated (expressed in [000]). Therefore, in the latter half of driving, the number of bits of SF data for designating one of the 8th to 14th gradations may be 3 bits. Therefore, using this situation, the SF data gradation dividing circuit 32 uses the SF data GD representing the first to fourteenth gradations in 4 bits and the gradation representing the first to seventh gradations in 3 bits. The divided SF data QD1 and the gradation divided SF data QD2 representing the 8th to 14th gradations in 3 bits are converted and supplied to the SF memory 40, respectively.

  FIG. 14 is a diagram illustrating an example of the internal configuration of the SF memory 40.

14, the first bank memory 430, supplied from the drive control circuit 20 the write enable signal BK1W, according to the address AD1 and the clock CK _RD, sequentially writes the gradation division SF data QD1 each for each pixel . That is, the first bank memory 430 provides gradation divided SF data QD1 ₍ 1,1 ₎ for one frame at the address specified by the address AD1 only while the write enable signal BK1 of logic level 1 is supplied _{. 1)} ... QD1 _{(n, m)} are sequentially written. The first bank memory 430, read enable signal BK1R and the address AD1 supplied from the drive control circuit 20, and in response to the clock CK _AD, supplied to a selector 450 sequentially reads the written gradation division SF data QD1 To do. That is, the first bank memory 430 reads the gradation-divided SF data QD1 written at the address specified by the address AD1 only while the read enable signal BK1R of the logic level 1 is supplied. Is supplied to the selector 450.

  As described above, the first bank memory 430 corresponds to the pixel data PD read out first from the pixel data PD read out twice from the frame memory 2 every frame. The gradation division SF data QD1 representing the first to seventh gradations is written in bits, and this is read out.

Second bank memory 440, supplied from the drive control circuit 20 the write enable signal BK2W, in accordance with the address AD2 and the clock CK _RD, sequentially writes the gradation division SF data QD2 each for each pixel. That is, the second bank memory 440 provides the gradation-division SF data QD2 _{(1,1) to} QD2 at the address specified by the address AD2 only while the write enable signal BK2 of logic level 1 is supplied. _{(n, m)} Each is written sequentially. The second bank memory 440, read enable signal BK2R supplied from the drive control circuit 20, in accordance with the address AD2 and the clock CK _AD, to the selector 450 sequentially reads the written gradation division SF data QD2 . That is, the second bank memory 440 reads the gradation-division SF data QD2 written at the address specified by the address AD2 only while the read enable signal BK2R of logic level 1 is supplied. Is supplied to the selector 450.

  As described above, the second bank memory 440 corresponds to the pixel data PD read out the second time among the pixel data PD read out twice from the frame memory 2 every frame. The gradation division SF data QD2 representing the eighth to fourteenth gradations is written in bits and read out.

In accordance with the bank memory selection signal S _BK supplied from the drive control circuit 20, the selector 450 reads out the gradation-division SF data QD 1 or QD 2 read from one of the first bank memory 430 and the second bank memory 440. Is supplied to the SF data restoration circuit 33 as read gradation division SF data QDR.

  Hereinafter, an internal operation of the SF memory 40 performed in accordance with control by the drive control circuit 20 will be described with reference to FIG.

First, the SF data gradation division circuit 32 sequentially converts the SF data GD _{(1,1) to} GD _{(n, m)} based on the first reading from the frame memory 2 into gradation division SF data QD1 _{(1 , 1) to} QD1 _{(n, m)} and supplied to the first bank memory 430. During this time, the drive control circuit 20 supplies the first bank memory 430 with a write enable signal BK1W of logic level 1. Therefore, the first bank memory 430 sequentially writes each of the grayscale divided SF data QD1 _{(1,1) to} QD1 _{(n, m)} in response to the write enable signal BK1W. Here, when all of the gray-scale divided SF data QD1 _{(1,1) to} QD1 _{(n, m)} for one frame is written in the first bank memory 430, the SF data gray-scale dividing circuit 32 Each of the SF data GD _{(1,1) to} GD _{( n, m)} based on the second reading from 2 is sequentially converted into gradation-divided SF data QD2 _{( 1,1) to} QD2 _{(n, m).} To the second bank memory 440. During this time, the drive control circuit 20 performs the read operation over the execution period of the write enable signal BK1W of logic level 0 to stop the write operation and the address process W of each of the subfields SF1 to SF7 as shown in FIG. A read enable signal BK1R having a logic level 1 to be generated is supplied to the first bank memory 430, respectively. As a result, the first bank memory 430 provides each frame of gray-scaled SF data QD1 _{(1,1) to} QD1 _{(n, m) for} one frame within the period during which the logic level 1 read enable signal BK1R is supplied. Are read sequentially. That is, the first bank memory 430 stores gradation divided SF data QD1 _{(1,1) to} QD1 _{(n, m)} for one frame each representing the first to seventh gradations in each of the subfields SF1 to SF7. It is repeatedly read out seven times at the timing corresponding to the above. During this time, the drive control circuit 20 supplies a write enable signal BK2W having a logic level 1 to the second bank memory 440. Therefore, the second bank memory 440 sequentially writes each of the grayscale divided SF data QD2 _{( 1,1) to} QD2 _{(n, m)} in response to the write enable signal BK2W. Here, when all of the gray-scale divided SF data QD2 _{(1,1) to} QD2 _{(n, m)} for one frame is written in the second bank memory 440, the drive control circuit 20 stops the writing operation. A write enable signal BK2W having a logic level 0 to be performed and a read enable signal BK2R having a logic level 1 to perform a read operation over the execution period of each address process W of each of the subfields SF8 to SF13 as shown in FIG. The second bank memory 440 is supplied. As a result, the second bank memory 440 provides each frame of gray-scale divided SF data QD2 _{( 1,1) to} QD2 _{(n, m) for} one frame within the period during which the logic level 1 read enable signal BK2R is supplied. Are read sequentially. That is, the second bank memory 440 stores gradation divided SF data QD2 _{( 1,1) to} QD2 _{(n, m)} for one frame each representing the eighth to fourteenth gradations in each of the subfields SF8 to SF13. It is repeatedly read out six times at the timing corresponding to the above.

Drive control circuit 20, as shown in FIG. 12, supplies the bank memory selection signal S _BK logic level 1 over while supplying a write enable signal BK1W logic level 0 to the first bank memory 430 to the selector 450 To do. The drive control circuit 20 supplies the bank memory selection signal S _BK logic level 0 to the selector 450 over the while providing a write enable signal BK2W logic level 0 to the second bank memory 440. Therefore, as shown in FIG. 12, the selector 450 performs gradation division SF for one frame repeatedly read from the first bank memory 430 seven times while the bank memory selection signal _SBK is at the logic level 1. Data QD1 _{(1,1) to} QD1 _{(n, m)} are supplied to the SF data restoration circuit 33 as read gradation division SF data QDR. Then, when the bank memory selection signal _SBK is switched to the logic level 0, the selector 450 causes the gradation divided SF data QD2 for one frame that is repeatedly read out from the second bank memory 440 seven times as shown in FIG. _{(1,1) to} QD2 _{(n, m)} are supplied to the SF data restoration circuit 33 as read gradation division SF data QDR.

  When the read gradation division SF data QDR supplied from the SF memory 40 is gradation division SF data QD1, the SF data restoration circuit 33 converts the read gradation division SF data QDR into 4 according to the gradation division conversion table shown in FIG. The bit data is converted into SF data GD and supplied to the address data conversion circuit 34. At this time, when the gradation division SF data QD1 indicates [111], the SF data restoration circuit 33 supplies the 4-bit invalid data [1111] to the address data conversion circuit 34 as the SF data GD. When the read gradation division SF data QDR supplied from the SF memory 40 is gradation division SF data QD2, the SF data restoration circuit 33 uses the gradation division conversion table shown in FIG. 4 is converted into 4-bit SF data GD and supplied to the address data conversion circuit 34. At this time, if the gradation division SF data QD2 indicates [000], the SF data restoration circuit 33 supplies the 4-bit invalid data [1111] to the address data conversion circuit 34 as the SF data GD.

  The address data conversion circuit 34 converts the SF data GD supplied from the SF data restoration circuit 33 into 13-bit address data ADD in accordance with a conversion table as shown in FIG. At this time, the first to thirteenth bits of the address data ADD correspond to the subfields SF1 to SF13, respectively, and indicate whether or not the erase address discharge is caused in the address process W of the corresponding subfield SF. It is. That is, each bit in the address data ADD is at the logic level 1 when the erase address discharge is caused in the subfield SF corresponding to the bit digit, and at the logic level 0 when it is not caused. The address data conversion circuit 34 is a logic level indicating that all the first to thirteenth bits do not cause the erase address discharge when the SF data GD supplied from the SF data restoration circuit 33 is [1101]. Address data ADD that becomes 0 is generated.

Then, the address data conversion circuit 34 first extracts only the first bit in the address data ADD at the execution timing of the address process W of the subfield SF1 shown in FIG. 9, and uses this as the SF1 address data bit DB. Sequentially supplied to the address driver 6 over the frame (DB _{(1,1) to} DB _{( n, m)} ). Next, the address data conversion circuit 34 extracts only the second bit in the address data ADD at the execution timing of the address process W in the subfield SF2 shown in FIG. 9, and uses this as the SF2 address data bit DB for one frame. The data are sequentially supplied to the address driver 6 over minutes (DB _{(1,1) to} DB _{( n, m)} ). Next, the address data conversion circuit 34 extracts only the third bit in the address data ADD at the execution timing of the address process W of the subfield SF3 shown in FIG. 9, and uses this as the SF3 address data bit DB for one frame. The data are sequentially supplied to the address driver 6 over minutes (DB _{(1,1) to} DB _{( n, m)} ). In the same manner, the address data conversion circuit 34 performs the bit digit (fourth bit to thirteenth bit) corresponding to the SF in the address data ADD at the execution timing of the address step W of the subfield SF (SF4 to SF13). Only bits) are extracted and supplied as SF (4-13) address data bits DB to the address driver 6 sequentially for one frame (DB _{(1,1) to} DB _{(n, m)} ).

  Therefore, in the plasma display device shown in FIG. 8, when the PDP is driven with 14 gradations in 13 subfields SF1 to SF13, the SF memory 40 is a bank memory capable of storing 3 bits of data for one frame. It is sufficient to prepare two. Therefore, as shown in FIG. 1, the storage capacity of the SF memory can be reduced as compared with a plasma display apparatus that requires two bank memories capable of storing one frame of data having the number of bits corresponding to the number of subfields. Is possible.

  In the above embodiment, the operation when the present invention is applied to the plasma display device in which the PDP is driven with 14 gradations by 13 subfields (SF1 to SF13) as shown in FIG. The present invention can also be applied when driving a PDP with gradation or higher.

  Hereinafter, the writing and reading operations of the SF memory 40 will be described by taking as an example the operation when driving the PDP with 20 gradations in accordance with the light emission driving sequence (subfields SF1 to SF19) as shown in FIG.

  At this time, the frame memory 2 is composed of two first and second frame memories in which the supplied pixel data PD for each pixel is alternately switched and written for each frame. Here, when the pixel data group corresponding to the first frame and the pixel data group corresponding to the second frame are sequentially supplied from the A / D converter 1, first, the first frame memory stores the first frame in the first frame. Next, the second frame memory writes the pixel data group corresponding to the second frame. During this time, the first frame memory repeatedly reads out the pixel data group corresponding to the first frame written as described above successively three times at a speed three times the writing speed. Then, after the third reading by the first frame memory is completed, the second frame memory successively reads out the pixel data group corresponding to the second frame successively three times at a speed three times the writing speed. .

  The SF data generation circuit 31 performs a multi-gradation process as described above on the pixel data PD (8 bits) read from the frame memory 2 to provide 5 bits indicating each of the first to twentieth gradations. SF data GD is generated and supplied to the SF data gradation dividing circuit 32.

  The SF data gradation dividing circuit 32 applies the SF data GD generated in response to the first reading from the frame memory 2 according to the gradation division conversion table as shown in FIG. It is converted into 3-bit gradation division SF data QD 1 and supplied to the SF memory 40. That is, the SF data gradation dividing circuit 32 generates 3-bit gradation division SF data QD1 representing the first to seventh gradations of the first to twentieth gradations by [000] to [110], respectively. It is supplied to the SF memory 40.

  The SF data gradation dividing circuit 32 applies gradation division conversion as shown in FIG. 16B to the SF data GD generated corresponding to the second reading from the frame memory 2. According to the table, it is converted into 3-bit gradation divided SF data QD2 and supplied to the SF memory 40. That is, the SF data gradation dividing circuit 32 generates 3-bit gradation divided SF data QD2 representing the eighth to thirteenth gradations of the first to twentieth gradations by [001] to [110], respectively. It is supplied to the SF memory 40.

  The SF data gradation dividing circuit 32 applies gradation division conversion to the SF data GD generated corresponding to the third reading from the frame memory 2 as shown in FIG. According to the table, it is converted into 3-bit gradation division SF data QD3 and supplied to the SF memory 40. That is, the SF data gradation dividing circuit 32 generates 3-bit gradation divided SF data QD3 representing the fourteenth to twentieth gradations of the first to twentieth gradations by [001] to [111], respectively. It is supplied to the SF memory 40.

  As described above, the gradation division SF data QD1 (indicating the first to seventh gradations) generated corresponding to the first reading of the frame memory 2 is generated corresponding to the second reading. The gradation division SF data QD2 (indicating the eighth to thirteenth gradation) and the gradation division SF data QD3 (indicating the fourteenth to twentieth gradations) generated corresponding to the third reading are sequentially obtained. It is supplied to the SF memory 40.

  At this time, first, the first bank memory 430 of the SF memory 40 writes the gradation-division SF data QD1 generated corresponding to the first reading of the frame memory 2.

  Next, the second bank memory 440 of the SF memory 40 writes the gradation division SF data QD2 generated corresponding to the second reading of the frame memory 2, and the first bank memory 430 has been written. The gradation division SF data QD1 is read. At this time, the selector 450 supplies the gradation division SF data QD1 to the SF data restoration circuit 33 as read gradation division SF data QDR.

  Next, the first bank memory 430 writes the gradation division SF data QD3 generated corresponding to the third reading of the frame memory 2, and the second bank memory 440 has written the gradation division SF. Read data QD2. At this time, the selector 450 supplies the gradation division SF data QD2 to the SF data restoration circuit 33 as read gradation division SF data QDR.

  Next, the second bank memory 440 writes the gradation division SF data QD1 generated corresponding to the first reading for the next frame of the frame memory 2, and the first bank memory 430 has been written. The gradation division SF data QD3 is read out. At this time, the selector 450 supplies the gradation division SF data QD3 to the SF data restoration circuit 33 as read gradation division SF data QDR.

  The SF data restoration circuit 33 is shown in FIG. 16A when the gradation division SF data QD1 is supplied as the read gradation division SF data QDR, and FIG. 16 when the gradation division SF data QD2 is supplied. (B) When the gradation division SF data QD3 is supplied, it is converted into 5-bit SF data GD according to the gradation division conversion table shown in FIG. 16C and supplied to the address data conversion circuit 34. . At this time, if the gradation division SF data QD1 indicates [111], the SF data restoration circuit 33 supplies the 5-bit invalid data [11111] to the address data conversion circuit 34 as the SF data GD. When the gradation division SF data QD2 indicates [000] or [111], the SF data restoration circuit 33 supplies 5-bit invalid data [11111] to the address data conversion circuit 34 as the SF data GD. . When the gradation division SF data QD2 indicates [000], the SF data restoration circuit 33 supplies the 5-bit invalid data [11111] to the address data conversion circuit 34 as the SF data GD.

  That is, first, SF data GD indicating each of the first to seventh gradations as shown in FIG. 17 is supplied to the address data conversion circuit 34 based on the gradation division SF data QD1 read from the first bank memory 430. The Therefore, at this time, the drive for causing the erase address discharge to occur in the discharge cell P is performed only in one of the subfields SF1 to SF7 as shown in FIG.

  Next, based on the gradation division SF data QD2 read from the second bank memory 440, SF data GD indicating the eighth to thirteenth gradations as shown in FIG. . Therefore, at this time, the drive to cause the erase address discharge to the discharge cell P is performed only in one of the subfields SF8 to SF13 as shown in FIG.

  Next, based on the gradation division SF data QD3 read from the first bank memory 430, SF data GD indicating each of the fourteenth to twentieth gradations as shown in FIG. . Therefore, at this time, the drive for causing the erase address discharge to occur in the discharge cell P is performed only in one of the subfields SF14 to SF19 as shown in FIG.

  Through the series of processes as described above, the number of gradations can be increased without increasing the storage capacity of each of the first bank memory 430 and the second bank memory 440.

  In the above-described embodiment, the gradation division SF data QD1, QD2 or QD3 representing different gradation ranges is written in the first bank memory 430 and the second bank memory 440, respectively. Some gradations may overlap between QD1 and QD2 (or between QD2 and QD3).

  At this time, the SF data gradation dividing circuit 32 performs the first to twelfth gradations in 4 bits according to the gradation division conversion table shown in FIG. Is converted into 3-bit gradation-divided SF data QD1 and supplied to the first bank memory 430. The gradation division SF data QD1 represents the gradation range of the first to seventh gradations by [000] to [110] of 3 bits, respectively, as shown in FIG. In addition, the SF data gradation dividing circuit 32 performs the first to twelfth gradation with 4 bits according to the gradation division conversion table shown in FIG. The represented SF data GD is converted into 3-bit gradation division SF data QD2, which is supplied to the second bank memory 440. The gradation division SF data QD2 represents the gradation range of the sixth to twelfth gradations by [001] to [111] of 3 bits, respectively, as shown in FIG. Accordingly, driving corresponding to the first to seventh gradations is performed based on the gradation division SF data QD1 read from the first bank memory 430, and the gradation division read from the second bank memory 440 is performed. Based on the SF data QD2, driving corresponding to the sixth to twelfth gradation is performed. At this time, the sixth gradation and the seventh gradation can be expressed by both of the gradation division SF data QD1 and QD2, as shown in FIGS. 18 (a) and 18 (b). Therefore, when the driving corresponding to the sixth gradation and the seventh gradation is performed, the gradation division SF data QD may be read from either the first bank memory 430 or the second bank memory 440. Therefore, when switching from the low luminance (first to sixth gradation) driving state to the high luminance (seventh to twelfth gradation) driving state, the first bank memory 430 and the second bank memory 440 respectively In the selector 450 for switching the read output, the number of options for switching time increases.

  In the frame memory 2 shown in FIG. 1 and FIG. 8, pixel data based on the input video signal is written and read out at a speed of k times (k: an integer of 2 or more) at the time of writing. This is because it is assumed that the frame rate of the input video signal and the display rate on the PDP 10 are the same. For example, when the frame rate of the input video signal and the display rate of an image for one frame in the PDP 10 are both frame rates [1 frame / 60 sec] corresponding to the NTSC (National Television System Committee) system, the frame memory In 2, the reading is performed at k times the frame rate.

  However, some frame memories 2 have a so-called frame rate conversion function for converting an input video signal having a frame rate different from the display rate into a display rate. For example, when a PAL (Phase Alternating Line) input video signal is supplied when the display rate of the PDP 10 is a frame rate corresponding to the NTSC format, the frame memory 2 corresponds to the NTSC format. Convert to frame rate. That is, at this time, the frame memory 2 writes pixel data based on the input video signal at a frame rate [1 frame / 50 sec] corresponding to the PAL system, and this is written at the display rate [1 frame / 60 sec] of the NTSC system. Reading is performed at a speed of k times. Note that the reading speed of the frame memory 2 may be k times or more.

  In short, in practice, the frame memory 2 shown in FIGS. 1 and 8 writes pixel data for each pixel based on the input video signal, and this is at a speed of k times the display rate (k: an integer of 2 or more) or more. Now, the data is repeatedly read k times for each frame.

It is a figure which shows schematic structure of the plasma display apparatus as a display apparatus by 1st Example of this invention. It is a figure which shows an example of the light emission drive sequence employ | adopted in the plasma display apparatus shown by FIG. FIG. 2 is a diagram showing operations of each of a frame memory 2, a first bank memory 43, and a second bank memory 44 shown in FIG. 3 is a diagram showing an internal configuration of an SF memory 4. FIG. It is a figure which shows the other internal structure of SF memory. FIG. 6 is a diagram showing an example of the operation of each of the first bank memory 43a and the second bank memory 44a shown in FIG. FIG. 6 is a diagram showing another example of the operation of each of the first bank memory 43a and the second bank memory 44a shown in FIG. It is a figure which shows schematic structure of the plasma display apparatus as a display apparatus by 2nd Example of this invention. It is a figure which shows an example of the light emission drive sequence employ | adopted in the plasma display apparatus shown by FIG. It is a figure which shows an example of the light emission drive pattern based on the light emission drive sequence shown by FIG. It is a figure which shows an example of the conversion characteristic at the time of converting pixel data PD into conversion pixel data HD in the SF data generation circuit 31. FIG. 9 is a diagram showing operations of the frame memory 2 and the first bank memory 430 and the second bank memory 440 in the SF memory 40 shown in FIG. 8. It is a figure which shows an example of the gradation division | segmentation conversion table in SF data gradation division circuit 32 and SF data restoration circuit 33. FIG. It is a figure which shows an example of an internal structure of SF memory 40 shown by FIG. It is a figure which shows another example of the light emission drive sequence employ | adopted in the plasma display apparatus shown by FIG. It is a figure which shows another example of the gradation division | segmentation conversion table in SF data gradation division circuit 32 and SF data restoration circuit 33. FIG. It is a figure which shows an example of the light emission drive pattern based on the light emission drive sequence shown by FIG. It is a figure which shows another example of the gradation division | segmentation conversion table in SF data gradation division circuit 32 and SF data restoration circuit 33. FIG.

Explanation of symbols

2 Frame memory 3 SF data generation circuit 4, 40 SF memory 6 Address driver 20 Drive control circuit
43,430 First bank memory
44,440 Second bank memory

Claims (5)

A display device that drives each pixel of a display panel to emit light in each of a plurality of subfields for each frame according to an input video signal,
A frame memory in which pixel data for each pixel based on the input video signal is written and repeatedly read k times for each frame at a speed of k times (k: an integer of 2 or more) the display rate of the display panel. When,
Based on the pixel data read from the frame memory, N bits (N: an integer equal to or greater than 2) indicating which of the sub-fields each pixel is set to be turned on or off. Subfield data generating means for generating subfield data;
The first to Qth bits (1 <Q <N) in the subfield data generated on the basis of the first reading from the frame memory are sequentially written, and each time one frame is written, the first A first bank memory that reads each of the 1st to Qth bits as an address data bit corresponding to each of the first to Qth subfields in each frame, and a second read from the frame memory The (Q + 1) to Rth bits (Q <R ≦ N) in the subfield data generated based on the above are sequentially written, and the (Q + 1) th to Rth bits are written each time one frame is written. Are read as address data bits corresponding to the (Q + 1) -th to R-th subfields in each frame. And a sub-field memory including a bank memory, the,
Addressing means for setting each of the pixels to one of a lighting state and a non-lighting state in accordance with the address data bit.   The second bank memory includes the (Q + 1) th to Rth bits in the subfield data generated based on the second reading from the frame memory, and the bit digit equal to or less than the Qth bit. The display device according to claim 1, wherein the bit group is written. A display device that drives each pixel of a display panel to emit light in each of a plurality of subfields for each frame according to an input video signal,
A frame memory for writing pixel data for each pixel based on the input video signal and repeatedly reading the data twice per frame at a speed twice as fast as the writing;
Based on the pixel data read from the frame memory, N bits (N: an integer equal to or greater than 2) indicating which of the sub-fields each pixel is set to be turned on or off. Subfield data generating means for generating subfield data;
The first to (N / 2) bits in the subfield data generated on the basis of the first reading from the frame memory are sequentially written and the first to first (N) th frames are written each time one frame is written. A first bank memory for reading out each (N / 2) bit as an address data bit corresponding to each of the first to (N / 2) th subfields in each frame; The (1 + N / 2) -th bit to the N-th bit are sequentially written in the subfield data generated based on the second reading, and the (1 + N / 2) -th bit is written each time one frame is written. A second buffer for reading out each Nth bit as an address data bit corresponding to each of the (1 + N / 2) th to Nth subfields in each frame. And a sub-field memory including a Kumemori, the,
And an addressing unit configured to set each of the pixels to one of a lighted state and a lighted state in accordance with the address data bit. Each of the pixels of the display panel has N luminance levels corresponding to the first to (N + 1) -th gradations in N stages in N (N: integer greater than or equal to 2) sub-fields for each frame in the input video signal. A display device that drives to emit light,
A frame memory in which pixel data for each pixel based on the input video signal is written and repeatedly read k times for each frame at a speed of k times (k: an integer of 2 or more) the display rate of the display panel. When,
Based on the pixel data read out from the frame memory, subfield data representing the first to the (N + 1) th gradations by P bits (P: an integer of 2 or more and less than N) is generated. Subfield data generating means for
Based on the subfield data generated based on the first reading from the frame memory, the first to Qth gradations (2 <Q <N) are R bits (R: 2 or more). 1st gradation division data expressed by an integer less than P) and (Q + 1) th gradation based on the subfield data generated based on the second reading from the frame memory. A gradation dividing means for generating second gradation divided data representing up to the S-th gradation (Q <S ≦ N + 1) by R bits;
A first bank memory that reads out the written first gradation divided data as first read gradation divided data each time the first gradation divided data is written and written for one frame; A sub-field memory including a second bank memory that reads out the second gradation division data written as second readout gradation division data each time the gradation division data is written and written for one frame. ,
Address data bits corresponding to the first to Qth subfields in each frame are generated based on the first readout gradation division data, and the second readout gradation division data is used as the second readout gradation division data. Address data conversion means for generating address data bits corresponding to each of the (Q + 1) -th to N-th subfields in each frame,
And an addressing unit configured to set each of the pixels to one of a lighted state and a lighted state in accordance with the address data bit.   The gradation dividing means, based on the subfield data generated based on the second reading from the frame memory, together with the (Q + 1) th gradation to the Sth gradation and the Qth gradation 5. The display according to claim 4, wherein data representing each gradation of n (1 ≦ n <Q) steps below the Qth gradation is represented by R bits as the second gradation division data. apparatus.

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