JP3868457B2 - Display panel drive method - Google Patents

Description

  The present invention relates to a method for driving a matrix display type display panel.

  As a display panel of a matrix display system, for example, a plasma display (hereinafter referred to as PDP), an electroluminescent display (hereinafter referred to as ELD), and the like are known. In a display panel composed of light emitting elements having only two states of “light emission” and “non-light emission” such as PDP and ELD, the subfield method is used in order to obtain a halftone luminance corresponding to the input video signal. The used gradation drive is performed.

  FIG. 1 is a diagram showing a driving format when performing halftone driving in 256 steps using the subfield method. As shown in FIG. 1, in the case of performing 256 gray scale driving, one field display period is divided into eight subfields SF1 to SF8, and 8-bit pixel data for each subfield. The light emission period (number of times) having a period length corresponding to the weighting of each bit digit, that is, SF1: 128 (first bit) SF2: 64 (second bit) SF3: 32 (third bit) SF4: 16 (first (4 bits) SF5: 8 (fifth bit) SF6: 4 (sixth bit) SF7: 2 (seventh bit) SF8: 1 (eighth bit) are assigned to perform light emission driving.

  That is, for each subfield, whether or not to perform light emission in that subfield is set according to the pixel data, and by combining these, 256-level luminance expression is realized. For example, when 8-bit pixel data (“00101000”) corresponding to the luminance “40” is supplied, light emission is executed only in the subfield corresponding to the bit digit of the logical level “1”, that is, SF3 and SF5. To do. According to such light emission driving, light emission of “32 + 8 = 40” times is performed within the display period of one field, so that display corresponding to the luminance “40” is made visually.

  As described above, in order to perform halftone luminance expression using a display panel composed of light emitting elements having only two states of “light emission” and “non-light emission”, a different display frequency is defined for one field display period. A so-called subfield method is used in which gradation driving is performed by dividing into a plurality of subfields. Here, in recent years, in a display device used in a computer or the like, it is possible to change the refresh rate in order to reduce flicker during image display. That is, “flickering” on the screen is prevented by increasing the refresh rate and shortening the display period of one field.

  However, in a display panel that performs gradation driving using the subfield method as described above, in order to shorten the display period of one field, the number of times of light emission (light emission period) to be performed in each subfield must be reduced. Therefore, there is a problem that a desired display luminance cannot be obtained.

The present invention has been made in order to solve the above-mentioned problem, and the refresh rate can be changed without degrading the display quality even for a display panel of a matrix display system that performs gradation driving using the subfield method. It is an object of the present invention to provide a method of driving a display panel that makes it possible to

The display panel driving method according to claim 1, wherein one pixel cell is formed at an intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged to cross the row electrodes. A display panel driving method for grayscale driving a matrix display type display panel, wherein a first driving period in the first half of a unit display period of an input video signal and a second driving period in the second half following the first driving period Each is divided into N (N is an integer of 2 or more) divided display periods. In each of the first drive period and the second drive period, the top divided display period includes the unit display period. A minimum number of times of light emission is assigned within each of the divided display periods, and each of the divided display periods subsequent to the first divided display period is assigned a number of times of light emission that is greater than the minimum light emission period. Te, in the first drive period and the second drive period in each, and the initialization step for initializing the state of simultaneously emitting cells all the pixel cells only in the divided display period of the first, the N a write step of only one of the divided display periods corresponding to the input video signal among the divided display periods respectively for setting the pixel cells to the non-light emitting cells, only the pixel cells in the state before Symbol emitting cell the only the number of emissions assigned to each divided display period running and light emission sustain process to emit light, to change the number of the divided display period in the unit display period in accordance with the vertical synchronizing frequency of said input video signal.

According to a seventh aspect of the present invention, there is provided a display panel driving method in which one pixel cell is formed at an intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged to cross the row electrodes. A display panel driving method for grayscale driving a matrix display type display panel, wherein a first driving period in the first half of a unit display period of an input video signal and a second driving period in the second half following the first driving period Each is divided into N (N is an integer of 2 or more) divided display periods. In each of the first drive period and the second drive period, the top divided display period includes the unit display period. A minimum number of times of light emission is assigned within each of the divided display periods, and each of the divided display periods subsequent to the first divided display period is assigned a number of times of light emission that is greater than the minimum light emission period. Te, in the first drive period and the second drive period in each, and the initialization step for initializing the state of simultaneously emitting cells all the pixel cells only in the divided display period of the first, the N a write step of only one of the divided display periods corresponding to the input video signal among the divided display periods respectively for setting the pixel cells to the non-light emitting cells, only the pixel cells in the state before Symbol emitting cell the only the number of emissions assigned to each divided display period running and light emission sustain process to emit light, to reduce the number of pre-Symbol divided display periods in the unit display period the higher the vertical synchronizing frequency of said input video signal

  In each of a plurality of divided display periods obtained by dividing the unit display period of the input video signal, divided light emission driving for causing the pixel cell to emit light for the number of times of light emission allocated for each divided display period is performed, and division is performed at the head in the unit display period. Only in the light emission drive, all of the pixel cells are initialized to the state of the light emission cell all at once, and in any one of the divided light emission drives executed within the unit display period, the pixel cell is set as a non-light emitting cell according to the input video signal. In order to cause only the pixel cells in the light emitting cell state to emit light in each of the divided light emission drivings, the number of divided light emission drivings executed within the unit display period is changed according to the vertical synchronization frequency of the input video signal. As a result, an image is displayed at a refresh rate corresponding to the vertical synchronization frequency of the input video signal.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 2 is a diagram showing a schematic configuration of a plasma display device including a driving device for driving a plasma display panel as a matrix display type display panel based on a driving method according to the present invention.

  As shown in FIG. 2, the plasma display device includes a PDP 10 as a plasma display panel, an A / D converter 1, a drive control circuit 2, a synchronization detection circuit 3, a drive data conversion circuit 30, a memory 4, and an address driver. 6 and a drive unit composed of first and second sustain drivers 7 and 8.

PDP10 is m column electrodes _D 1 to D _m as address electrodes, respectively are arranged by the intersection with these column electrodes each s n row electrodes _X 1 to X _n and row electrodes _Y 1 to Y _n It has. A pair of the row electrode X and the row electrode Y forms a row electrode corresponding to one row in the PDP 10. The column electrode D and the row electrodes X and Y are covered with a dielectric layer with respect to the discharge space, and a discharge cell corresponding to one pixel is formed at the intersection of each row electrode pair and the column electrode. Yes.

  The synchronization detection circuit 3 supplies a vertical synchronization detection signal V to the drive control circuit 2 and the vertical synchronization frequency measurement circuit 20 when a vertical synchronization signal is detected from the input video signal, and when a horizontal synchronization signal is detected. A horizontal synchronization detection signal H is supplied to the drive control circuit 2.

  The vertical synchronization frequency measurement circuit 20 measures the frequency of the vertical synchronization detection signal V and supplies the vertical frequency signal VF indicating the frequency to the drive control circuit 2 and the drive data conversion circuit 30 respectively.

  The A / D converter 1 samples an analog input video signal in accordance with the clock signal supplied from the drive control circuit 2, converts it into 8-bit pixel data D corresponding to each pixel, and drives it. The data conversion circuit 30 is supplied.

  FIG. 3 is a diagram showing an internal configuration of the drive data conversion circuit 30. As shown in FIG.

In FIG. 3, the first data conversion circuit 32 converts the pixel data D for each pixel sequentially supplied from the A / D converter 1 into 14 × 16/255 (based on the conversion characteristics as shown in FIG. It is converted into the converted pixel data HD _p of 8 bits (0 to 224) which was 224/255), and supplies it to the multi-gradation processing circuit 33. Specifically, 8-bit (0 to 255) pixel data D is converted according to the conversion tables shown in FIGS. 5 and 6 based on the conversion characteristics. That is, this conversion characteristic is set according to the number of bits of the pixel data D, the number of compression bits by the multi-gradation processing described later, and the number of display gradations. As described above, the first data conversion circuit 32 is provided in the previous stage of the multi-gradation processing, and the pixel data D is converted to the upper level by performing conversion according to the display gradation number and the compression bit number by the multi-gradation. A bit group (corresponding to multi-gradation pixel data) and a lower bit group (data to be discarded: error data) are separated at bit boundaries, and multi-gradation processing is performed based on this signal. Due to the data change by the first data conversion circuit 32 as described above, the generation of luminance saturation due to the subsequent multi-gradation processing and the generation of the flat portion of the display characteristic that occurs when the display gradation is not at the bit boundary (that is, the gradation) (Distortion generation) is prevented.

  FIG. 7 is a diagram showing an internal configuration of the multi-gradation processing circuit 33.

  As shown in FIG. 7, the multi-gradation processing circuit 33 includes an error diffusion processing circuit 330 and a dither processing circuit 350.

The data separation circuit 331 in the error diffusion processing circuit 330 separates the lower 2 bits in the 8-bit converted pixel data HD _P supplied from the first data conversion circuit 32 as error data and the upper 6 bits as display data. . The adder 332 delays the addition value obtained by adding the lower 2 bits in the converted pixel data HD _P as the error data, the delay output from the delay circuit 334, and the multiplication output of the coefficient multiplier 335. Supply to circuit 336. The delay circuit 336 uses the coefficient multiplier 335 and the delay circuit 337 as a delayed addition signal AD ₁ as a signal obtained by delaying the addition value supplied from the adder 332 by a delay time D having the same time as the clock cycle of the pixel data. Respectively. The coefficient multiplier 335 supplies a multiplication result obtained by multiplying the delayed addition signal AD ₁ by a predetermined coefficient value K ₁ (for example, “7/16”) to the adder 332. Delay circuit 337, further the delay addition signal AD ₁ - supplied to the delay circuit 338 which is delayed by (1 horizontal scanning period the delay time D × 4) comprising time as a delay addition signal AD _2. The delay circuit 338 supplies the delayed addition signal AD ₂ further delayed by the delay time D to the coefficient multiplier 339 as the delayed addition signal AD ₃ . Further, the delay circuit 338 supplies the delayed multiplier signal AD ₂ further delayed by the delay time D × 2 to the coefficient multiplier 340 as a delayed add signal AD ₄ . Further, the delay circuit 338 is supplied to the coefficient multiplier 341 and a delayed such delay addition signal AD ₂ by further the delay time D × 3 becomes time period as a delay addition signal AD _5. The coefficient multiplier 339 supplies the multiplication result obtained by multiplying the delay addition signal AD ₃ by a predetermined coefficient value K ₂ (for example, “3/16”) to the adder 342. The coefficient multiplier 340 supplies a multiplication result obtained by multiplying the delayed addition signal AD ₄ by a predetermined coefficient value K ₃ (for example, “5/16”) to the adder 342. The coefficient multiplier 341 supplies a multiplication result obtained by multiplying the delay addition signal AD ₅ by a predetermined coefficient value K ₄ (for example, “1/16”) to the adder 342. The adder 342 supplies an addition signal obtained by adding the multiplication results supplied from the coefficient multipliers 339, 340, and 341 to the delay circuit 334. The delay circuit 334 delays the added signal by the time corresponding to the delay time D and supplies the delayed signal to the adder 332. The adder 332 adds a logical level when there is no carry when adding the lower 2 bits in the converted pixel data HD _P , the delay output from the delay circuit 334, and the multiplication output of the coefficient multiplier 335. If there is a carry, “0”, a carry-out signal _CO of logical level “1” is generated and supplied to the adder 333. The adder 333, the display data composed of upper 6 bits of the converted pixel data HD in _P, and outputs obtained by adding the carry-out signal C _O of 6 bits as the error diffusion processing pixel data ED. In other words, the number of bits of the error diffusion processing pixel data ED is becoming smaller than the converted pixel data HD _P.

  The operation of the error diffusion processing circuit 330 will be described below.

For example, when obtaining the error diffusion processing pixel data ED corresponding to the pixel G (j, k) of the PDP 10 as shown in FIG. 8, first, the pixel G (j, k) on the left side of the pixel G (j, k) is first obtained. k-1), upper left pixel G (j-1, k-1), upper right pixel G (j-1, k), and upper right pixel G (j-1, k + 1) Error data corresponding to each, that is,
Error data corresponding to pixel G (j, k-1): delayed addition signal AD ₁
Error data corresponding to pixel G (j−1, k + 1): delayed addition signal AD ₃
Error data corresponding to pixel G (j−1, k): delayed addition signal AD ₄
Error data corresponding to pixel G (j-1, k-1): delayed addition signal AD ₅
Each is weighted and added with predetermined coefficient values K _{1 to} K ₄ as described above. Then, the addition result, the lower two bits of the converted pixel data HD _P, i.e. pixel G (j, k) by adding the error data corresponding to the carry-out signal C _O of 1 bit obtained when the the upper 6 bits in the converted pixel data HD _P, that is, the pixel G (j, k) error diffusion processing pixel data ED those obtained by adding the display data corresponding to the.

With this configuration, the error diffusion processing circuit 330 regards the upper 6 bits in the converted pixel data HD _P as display data and the remaining lower 2 bits as error data, and the surrounding pixels {G (j, k−1), G (j-1, k + 1), G (j-1, k), G (j-1, k-1)} are weighted and added to reflect the display data. I have to. By such an operation, the luminance of the lower 2 bits in the original pixel {G (j, k)} is expressed in a pseudo manner by the peripheral pixels. Therefore, the number of bits is smaller than 8 bits, that is, the display data is 6 bits. Thus, luminance gradation equivalent to the 8-bit pixel data can be expressed.

If the error diffusion coefficient value is added to each pixel at a constant rate, noise due to the error diffusion pattern may be visually confirmed, and the image quality is impaired. Therefore, the error diffusion coefficients K _{1 to} K ₄ to be assigned to each of the four pixels may be changed for each field as in the case of the dither coefficient described later.

The dither processing circuit 350 performs a dither process on the 6-bit error diffusion processing pixel data ED supplied from the error diffusion processing circuit 330, thereby maintaining a luminance gradation level equivalent to that of the error diffusion processing pixel data ED. generating a multi-gradation processing pixel data D _S which also reduce the number of bits to 4 bits. In this dither process, one intermediate display level is expressed by a plurality of adjacent pixels. For example, when performing gradation display corresponding to 8 bits using upper 6 bits of pixel data of 8 bits of pixel data, a set of four pixels adjacent to each other on the left, right, and top is taken as one set. Four dither coefficients a to d having different coefficient values are assigned to each pixel data corresponding to the pixel and added. According to such dither processing, four different combinations of intermediate display levels are generated with four pixels. Therefore, even if the number of bits of the pixel data is 6 bits, the luminance gradation level that can be expressed is 4 times, that is, halftone display equivalent to 8 bits is possible.

  However, if a dither pattern consisting of dither coefficients a to d is added to each pixel, noise due to the dither pattern may be visually confirmed and image quality is impaired.

  Therefore, in the dither processing circuit 350, the dither coefficients a to d to be assigned to each of the four pixels are changed for each field.

  FIG. 9 is a diagram showing an internal configuration of the dither processing circuit 350.

  In FIG. 9, the dither coefficient generation circuit 352 generates four dither coefficients a, b, c, and d for every four adjacent pixels, and sequentially supplies these to the adder 351. For example, as shown in FIG. 10, the pixel G (j, k) and the pixel G (j, k + 1) corresponding to the jth row and the pixel G (j + 1, k) corresponding to the (j + 1) th row are shown. ) And four dither coefficients a, b, c and d are generated for each of the four pixels G (j + 1, k + 1). At this time, the dither coefficient generation circuit 352 changes the dither coefficients a to d to be assigned to each of these four pixels for each field as shown in FIG.

That is, in the first first field,
Pixel G (j, k): Dither coefficient a
Pixel G (j, k + 1): Dither coefficient b
Pixel G (j + 1, k): Dither coefficient c
Pixel G (j + 1, k + 1): Dither coefficient d
In the next second field,
Pixel G (j, k): Dither coefficient b
Pixel G (j, k + 1): Dither coefficient a
Pixel G (j + 1, k): Dither coefficient d
Pixel G (j + 1, k + 1): Dither coefficient c
In the next third field,
Pixel G (j, k): Dither coefficient d
Pixel G (j, k + 1): Dither coefficient c
Pixel G (j + 1, k): Dither coefficient b
Pixel G (j + 1, k + 1): Dither coefficient a
And in the fourth field,
Pixel G (j, k): Dither coefficient c
Pixel G (j, k + 1): Dither coefficient d
Pixel G (j + 1, k): Dither coefficient a
Pixel G (j + 1, k + 1): Dither coefficient b
In such an assignment, the dither coefficients a to d are repeatedly generated by being circulated and supplied to the adder 351. The dither coefficient generation circuit 352 repeatedly performs the operations of the first field to the fourth field as described above. That is, when the dither coefficient generation operation in the fourth field is completed, the operation returns to the operation in the first field again, and the above-described operation is repeated.

  The adder 351 supplies the pixel G (j, k), pixel G (j, k + 1), pixel G (j + 1, k), and pixel G (j) supplied from the error diffusion processing circuit 330. + 1, k + 1) is added to each of the error diffusion processing pixel data ED corresponding to each, and the dither coefficients a to d assigned to each field as described above are added, and the dither addition pixel data obtained at this time is added. This is supplied to the upper bit extraction circuit 353.

For example, in the first field shown in FIG.
Error diffusion processing pixel data ED corresponding to the pixel G (j, k) + dither coefficient a,
Error diffusion pixel data ED corresponding to pixel G (j, k + 1) + dither coefficient b,
Error diffusion pixel data ED corresponding to the pixel G (j + 1, k) + dither coefficient c,
Each of the error diffusion processing pixel data ED + dither coefficient d corresponding to the pixel G (j + 1, k + 1) is sequentially supplied to the upper bit extraction circuit 353 as dither addition pixel data.

Upper bit extracting circuit 353 extracts until the upper 4 bits of such dither-added pixel data, and supplies the second data conversion circuit 34 shown in FIG. 3 as the multi-gradation pixel data D _S.

The second data conversion circuit 34, such a multi-gradation pixel data D _S, according to the conversion table corresponding to the vertical synchronizing frequency indicated by the vertical frequency signal VF, and converts the drive pixel data HD.

  FIG. 11 is a diagram showing an example of the internal configuration of the second data conversion circuit 34. As shown in FIG.

Data conversion circuit 341 to 344, respectively in FIG. 11 converts according to different conversion tables A~D each other, 4 bits of the multi-gradation pixel data _{D S} to 14-bit data.

  The selector 345 selectively selects data corresponding to the vertical synchronization frequency indicated by the vertical frequency signal VF from the data converted and output by each of the data conversion circuits 341 to 344, and this is selected as the drive pixel. Output as data HD.

For example, the vertical frequency signal VF is
VF ≦ 60Hz
, The selector 345 selectively selects the conversion data converted and output by the data conversion circuit 341 according to the conversion table A as shown in FIG. 12, and outputs this as drive pixel data HD.

The vertical frequency signal VF is
60Hz <VF ≦ 65Hz
, The selector 345 selectively selects the conversion data converted and output by the data conversion circuit 342 according to the conversion table B as shown in FIG. 13, and outputs this as drive pixel data HD.

The vertical frequency signal VF is
65Hz <VF ≦ 75Hz
, The selector 345 selectively selects the conversion data converted and output by the data conversion circuit 343 in accordance with the conversion table C as shown in FIG. 14, and outputs this as drive pixel data HD.

Furthermore, the vertical frequency signal VF is
75Hz <VF ≦ 85Hz
, The selector 345 selectively selects the conversion data converted and output by the data conversion circuit 344 according to the conversion table D as shown in FIG. 15, and outputs this as drive pixel data HD.

  In this way, the drive data conversion circuit 30 first performs multi-gradation processing such as error diffusion and dither processing on the 8-bit pixel data D, thereby maintaining the number of luminance gradations visually. Meanwhile, the multi-gradation pixel data Ds whose number of bits is reduced to 4 bits is obtained. Next, the multi-gradation pixel data Ds is converted into 14-bit driving pixel data for actually driving the PDP 10 according to the conversion tables as shown in FIGS. 12 to 15 corresponding to the vertical synchronization frequency of the video signal. It is converted to HD.

The memory 4 sequentially writes the drive pixel data HD in accordance with the write signal supplied from the drive control circuit 2. When the writing of the drive pixel data HD _11-nm for one screen (n rows, m columns) corresponding to the odd field is completed by the writing operation, for example, the memory 4 reads the read signal supplied from the drive control circuit 2. In accordance with the odd field, the drive pixel data HD _11-nm for one screen corresponding to the odd field is obtained for each bit digit.
DB1 _11-nm : 1st bit of drive pixel data HD _11-nm
DB2 _11-nm : 2nd bit of drive pixel data HD _11-nm
DB3 _11-nm : the third bit of the drive pixel data HD _11-nm
DB4 _11-nm : 4th bit of drive pixel data HD _11-nm
DB5 _11-nm : 5th bit of drive pixel data HD _11-nm
DB6 _11-nm : 6th bit of drive pixel data HD _11-nm
DB7 _11-nm : 7th bit of drive pixel data HD _11-nm
DB8 _11-nm : 8th bit of drive pixel data HD _11-nm
DB9 _11-nm : 9th bit of drive pixel data HD _11-nm
DB10 _11-nm : 10th bit of drive pixel data HD _11-nm
DB11 _11-nm : 11th bit of drive pixel data HD _11-nm
DB12 _11-nm : 12th bit of drive pixel data HD _11-nm
DB13 _11-nm : 13th bit of drive pixel data HD _11-nm
DB14 _11-nm: drive pixel data _{HD 11-nm} bit 14 th as divided, these _{DB1 11-nm, DB2 11-} nm, ····, sequentially DB 14 _11-nm respectively per row Read and supply to the address driver 6.

Next, the memory 4 again reads out the drive pixel data HD _11-nm for one screen corresponding to the odd field in accordance with the read signal supplied from the drive control circuit 2 and supplies it to the address driver 6. At this time, the second reading is performed according to the vertical frequency signal VF.

That is, the vertical frequency signal VF is
VF ≦ 60Hz
, The memory 4 sequentially reads each of DB1 _{11-nm to} DB14 _{11-nm for} each row and supplies it to the address driver 6 as in the first reading described above.

However, the vertical frequency signal VF is
60Hz <VF ≦ 65Hz
To the case shown, the memory 4, except _{DB1 11-nm} from among the _{DB1 11-nm ~DB14 11-nm} , sequentially reads out ~DB14 _11-nm, respectively _{DB2 11-nm} every row address Supply to the driver 6.

The vertical frequency signal VF is
65Hz <VF ≦ 75Hz
In this case, the memory 4 excludes DB1 _11-nm and DB2 _11-nm from the above DB1 _{11-nm to} DB14 _11-nm , and DB3 _{11-nm to} DB14 _{11-nm for} each row. Are sequentially read and supplied to the address driver 6.

Furthermore, the vertical frequency signal VF is
75Hz <VF ≦ 85Hz
To indicate the memory 4, except _{DB1 11-nm ~DB3 11-nm} from among the _{DB1 11-nm ~DB14 11-nm} , DB4 11-nm ~DB14 11-nm respectively per row Are sequentially read and supplied to the address driver 6.

  That is, the memory 4 sequentially writes only the data corresponding to the odd field (or even field) from among the drive pixel data HD sequentially supplied from the drive data conversion circuit 30, and converts this into the form as described above. Read twice. As described later, display driving for two fields is performed by such two readings.

  The drive control circuit 2 generates a clock signal for the A / D converter 1 in synchronization with the horizontal synchronization detection signal H and the vertical synchronization detection signal V supplied from the synchronization detection circuit 3. Further, the drive control circuit 2 generates a write signal and a read signal synchronized with the vertical synchronization detection signal V in accordance with the vertical frequency signal VF and supplies them to the memory 4. Further, the drive control circuit 2 supplies various timing signals for driving and controlling the PDP 10 in accordance with the light emission drive format corresponding to the vertical frequency signal VF to each of the address driver 6, the first sustain driver 7 and the second sustain driver 8.

  FIG. 16 is a diagram showing an example of a light emission drive format based on the drive method of the present invention.

In FIG. 16A, the vertical frequency signal VF is
VF ≦ 60Hz
Indicates
FIG. 16B shows that the vertical frequency signal VF is
60Hz <VF ≦ 65Hz
Indicates
In FIG. 16C, the vertical frequency signal VF is
65Hz <VF ≦ 75Hz
Indicates
FIG. 16D shows that the vertical frequency signal VF is
75Hz <VF ≦ 85Hz
It is a figure which shows the light emission drive format in each case.

  In this embodiment, as shown in FIGS. 16A to 16D, the display period of two fields is regarded as a unit display period, and this is repeatedly executed. At this time, the unit display period is divided into a first driving period in the first half and a second driving period in the second half, and the operation in the first driving period is as shown in FIGS. 16 (a) to 16 (d). Both are the same.

  The first driving period is divided into 14 subfields SF1 to SF14, and in each subfield, pixel data is written to each discharge cell of the PDP 10 to perform “light emitting cell” and “non-light emitting cell”. A pixel data writing step Wc for setting the above and a light emission sustaining step Ic in which only the “light emitting cell” is discharged for the number of times (period) shown in the drawing to maintain its light emission state are performed. During the first driving period, the simultaneous reset process Rc for initializing the wall charge amount in all the discharge cells of the PDP 10 is executed only in the first subfield, and only in the last subfield, Erasing process E for simultaneously erasing the wall charges of the sub-fields, that is, light emission within the first driving period in the divided light-emission driving divided into 14 subfields SF1 to SF14. It is to carry out the motion.

In order to realize the above operations in the simultaneous reset process Rc, the pixel data writing process Wc, the light emission sustaining process Ic, and the erasing process E, each of the address driver 6, the first sustain driver 7 and the second sustain driver 8 Various drive pulses are applied to each of the column electrodes D _{1 to} D _m , the row electrodes X _{1 to} X _n, and Y _{1 to} Y _n .

  FIG. 17 is a diagram showing the application timing of each drive pulse within the first drive period shown in FIG.

First, in the simultaneous reset process Rc of the sub-field SF1, the first sustain driver 7 and second sustain driver 8, a negative reset pulse RP _x and positive polarity of the reset pulse RP _Y to the row electrodes _X 1 to X _n and Y at the same time it applied to the _{1 ~Y n.} The application of these reset pulses RP _x and RP _Y, all the discharge cells in the PDP10 is reset discharge uniformly predetermined wall charge in each discharge cell is formed. As a result, all discharge cells in the PDP 10 are temporarily set to “light emitting cells” once.

Next, in the pixel data writing process Wc of the subfield SF1, the address driver 6 generates a pixel data pulse having a voltage corresponding to the logic level of each of the DB1 _11-nm supplied from the memory 4 as described above. This is sequentially applied to the column electrode D1 _-m for each row. That is, first, a pixel data pulse group DP1 ₁ composed of m pixel data pulses corresponding to the first row of DB1 _11-nm , that is, m corresponding to the logical level of each DB1 _11-1m is generated. Then, it is simultaneously applied to the column electrode D _1-m . Next, a pixel data pulse group DP1 ₂ composed of m pixel data pulses corresponding to each logic level of DB1 _21-2m corresponding to the second row of DB1 _11-nm is generated to generate a column electrode D _{1 -1. Apply} simultaneously to _m . Similarly, pixel data pulse groups DP1 _{3 to} DP1 _n for each row are sequentially applied to the column electrode D _1-m .

Next, in the pixel data writing process Wc of the subfield SF2, the address driver 6 generates a pixel data pulse having a voltage corresponding to the logical level from each DB2 _11-nm supplied from the memory 4 as described above. Then, this is sequentially applied to the column electrode D1 _-m for each row. That is, first, a pixel data pulse group DP2 ₁ composed of m pixel data pulses corresponding to the first row from the DB2 _11-nm , that is, the logical level of each DB2 _11-1m is generated. _Are simultaneously applied to the column electrode D1 _-m . Next, a pixel data pulse group DP2 ₂ composed of m pixel data pulses corresponding to each logic level of DB2 _21-2m corresponding to the second row of DB2 _11-nm is generated to generate a column electrode D _{1-1. Apply} simultaneously to _m . Hereinafter, similarly, pixel data pulse groups DP2 _{3 to} DP2 _n for each row are sequentially applied to the column electrode D _1-m . In the pixel data writing process Wc in each of the subfields SF3 to SF14, the address driver 6 also uses the pixel data pulse groups DP3 _{1-n to} DP14 based on DB3 _{11-nm to} DB14 _11-nm in the same manner as described above. _1-n is generated, and these are sequentially applied to the column electrode D1 _-m for each row. The address driver 6 generates a high-voltage pixel data pulse when the logical level of DB is “1”, and generates a low-voltage (0 volt) pixel data pulse when it is “0”. It shall be.

Here, the second sustain driver 8 generates a scanning pulse SP having a negative polarity as shown in FIG. 17 at the same timing as each application timing of the pixel data pulse group DP as described above, and this is generated as the row electrode Y. successively applied to the _{1 ~Y n.} At this time, a discharge (selective erasure discharge) occurs only in the discharge cell at the intersection of the “row” to which the scan pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied. The wall charges remaining in are selectively erased. Due to the selective erasing discharge, the discharge cell initialized to the “light emitting cell” state in the simultaneous reset process Rc is changed to the “non-light emitting cell”. It should be noted that no discharge is generated in the discharge cells formed in the “column” to which the high voltage pixel data pulse is not applied, and the state is initialized in the simultaneous reset process Rc, that is, the “light emitting cell”. The state of is maintained.

  That is, by the pixel data writing process Wc for each subfield, a “light emitting cell” in which a sustain discharge is generated in the light emission sustaining process cI immediately after that, and a “non-light emitting in which no sustain discharge is generated and no light is emitted. The cell "is alternatively set according to the pixel data, and the pixel data is written to each discharge cell.

Further, the light emission sustain process Ic is executed in each subfield SF1~SF14 respectively, the first sustain driver 7 and second sustain driver 8, FIG to the row electrodes _X 1 to X _n and _Y 1 to Y _n 17 As shown in FIG. 6, positive sustain pulses IP _X and IP _Y are alternately applied. Here, the number of sustain pulses IP applied in the light emission sustain process Ic of each subfield is:
SF1: 1
SF2: 3
SF3: 5
SF4: 8
SF5: 10
SF6: 13
SF7: 16
SF8: 19
SF9: 22
SF10: 25
SF11: 28
SF12: 32
SF13: 35
SF14: 39
It is.

The sustain pulses IP _X and IP _Y are applied to the discharge cells in which the wall charges remain in the pixel data writing process Wc by applying the sustain pulse IP as described above, that is, the “light emitting cells”. The sustain discharge is performed every time, and the discharge light emission state is maintained for the number of times (period). At this time, the ratio of the number of sustain discharges to be executed in each of the subfields SF1 to SF14 is made non-linear as described above (that is, the inverse gamma ratio, Y = X ^2.2 ), so that the non-linear characteristics of the input pixel data D are obtained. (Gamma characteristic) is corrected.

In the erase process E in the last subfield of the first drive period as shown in FIG. 17, the address driver 6 generates an erase pulse AP and applies it to each of the column electrodes D1 _-m. To do. The second sustain driver 8 generates an erase pulse EP simultaneously with the application timing of the erase pulse AP and applies it to each of the row electrodes Y _{1 to} Y _n . By simultaneously applying these erasing pulses AP and EP, an erasing discharge is generated in all the discharge cells in the PDP 10, and the wall charges remaining in all the discharge cells are extinguished. That is, by this erasing discharge, all the discharge cells in the PDP 10 become “non-light emitting cells”.

  By the driving described above, selective erasing is selectively performed in the pixel data writing process Wc of the subfield corresponding to the bit digit in accordance with the logic level of each bit (first bit to 14th bit) in the driving pixel data HD. Discharging is performed. At this time, due to the selective erasing discharge, the discharge cell initialized to the “light emitting cell” state in the simultaneous reset process Rc changes to the “non-light emitting cell”. On the other hand, the discharge cells in which the selective erasing discharge has not been performed maintain the state initialized in the simultaneous reset process Rc, that is, the state of “light emitting cells”. In each light emission sustaining step Ic, only this “light emitting cell” is repeatedly emitted for the number of times (periods) corresponding to the subfield.

  On the other hand, in the second drive period, basically the same operation as in the first drive period is performed, but the number of subfields to be executed is reduced according to the vertical frequency signal VF. .

That is, as shown in the second drive period of FIG. 16B, the vertical frequency signal VF is
60Hz <VF ≦ 65Hz
In this case, the subfield SF1 is omitted, and the number of sustain discharges to be originally performed in the light emission sustaining process Ic of SF1 is added to the light emission sustaining process Ic of the subfield SF2. Therefore, the number of sustain discharges performed in the light emission sustaining process Ic of the subfield SF2 in the second drive period of FIG. 16B is “4”.

Further, as shown in the second drive period of FIG. 16C, the vertical frequency signal VF is
65Hz <VF ≦ 75Hz
In this case, the subfields SF1 and SF2 are omitted, and the number of sustain discharges to be performed in the light emission sustaining process Ic of SF1 and SF2 is added to the light emission sustaining process Ic of the subfield SF3. Therefore, the number of sustain discharges performed in the light emission sustaining process Ic of the subfield SF3 in the second driving period of FIG. 16C is “9”.

Further, as shown in the second drive period of FIG. 16D, the vertical frequency signal VF is
75Hz <VF ≦ 85Hz
In this case, the subfields SF1 to SF3 are omitted, and the number of sustain discharges to be executed in the light emission sustaining process Ic of SF1 to SF3 is added to the light emission sustaining process Ic of the subfield SF4. Therefore, the number of sustain discharges performed in the light emission sustain process Ic of the subfield SF4 in the second drive period of FIG. 16D is “17”.

Note that the vertical frequency signal VF as shown in FIG.
VF ≦ 60Hz
In the second driving period in the case of the above, all the subfields SF1 to SF14 are executed as in the first driving period.

  Thus, as the vertical frequency signal VF becomes higher, the number of subfields to be executed in the second drive period is reduced. As a result, as shown in FIGS. 16B to 16D, as the vertical synchronizing frequency of the input video signal is increased, the drive time per field display period is shortened. Therefore, it is possible to display an image at a refresh rate corresponding to the vertical frequency.

  Here, the drive pixel data HD used when driving based on the light emission drive format shown in FIGS. 16A to 16D has 15 patterns as shown in FIGS. Therefore, the light emission drive pattern actually implemented based on these light emission drive formats shown in FIGS. 16A to 16D is as shown in FIGS.

In FIG. 18, the vertical frequency signal VF is
VF ≦ 60Hz
Indicates
FIG. 19 shows that the vertical frequency signal VF is
60Hz <VF ≦ 65Hz
Indicates
FIG. 20 shows that the vertical frequency signal VF is
65Hz <VF ≦ 75Hz
Indicates
FIG. 21 shows that the vertical frequency signal VF is
75Hz <VF ≦ 85Hz
The light emission drive pattern during the two-field display period in each case is shown.

  The black circles shown in FIGS. 18 to 21 indicate that selective erasing discharge is performed in the pixel data writing process Wc in the subfield. That is, the wall charges formed in all the discharge cells of the PDP 10 by the simultaneous reset process Rc executed at the beginning of each of the first and second driving periods remain until the selective erasing discharge is performed. In the light emission sustaining process Ic in each existing subfield SF, a sustain discharge accompanied by light emission occurs (indicated by white circles). As described above, each discharge cell becomes a “light emitting cell” until the selective erasing discharge is performed in each of the first and second driving periods, and the light emission sustaining process Ic in each subfield existing therebetween. The light emission is repeated for the number of times corresponding to each subfield.

According to the light emission drive pattern as shown in FIGS. 18 to 21, the light emission luminance ratio is about
{0, 1, 4, 9, 17, 27, 40, 56, 75, 97, 122, 150, 182, 217, 256}
15 levels of gradation driving are performed.

  However, the pixel data D supplied from the A / D converter 1 expresses 8 bits, that is, 256 halftones. Therefore, in order to realize halftone display close to 256 levels even by the above-described 15 levels of gradation drive, the multi-gradation processing circuit 33 shown in FIG. 3 performs multi-gradation processing such as error diffusion and dither. It is.

  As described above in detail, in the present invention, the higher the vertical synchronizing frequency of the input video signal, the fewer the number of subfields to be executed in the second driving period, and the driving time per field display period. By shortening, it is possible to display an image at a refresh rate corresponding to the vertical frequency of the input video signal.

  In the above embodiment, the pixel data is written in such a manner that wall charges are formed in advance in each discharge cell at the beginning of each driving period, and all discharge cells are set to “light emitting cells”. The case where the so-called selective erasure address method is adopted, in which pixel data is written by selectively erasing the wall charges accordingly, has been described.

  However, the present invention can be similarly applied to a case where a so-called selective write addressing method in which wall charges are selectively formed according to pixel data as a pixel data writing method.

  FIG. 22 is a diagram showing a light emission drive format when this selective write address method is employed.

  As shown in FIGS. 22A to 22D, when the selective write address method is adopted, the display period of two fields is regarded as one cycle, similarly to the case where the selective erase address method is adopted. Repeat this. At this time, such one cycle is divided into a first driving period in the first half and a second driving period in the second half, and the operation in the first driving period is any of FIGS. 22 (a) to 22 (d). Is the same.

  The first driving period is divided into 14 subfields SF14 to SF1, and in each subfield, pixel data is written to each discharge cell of the PDP 10 to perform “light emitting cell” and “non-light emitting cell”. A pixel data writing step Wc for setting the above and a light emission sustaining step Ic for discharging only the “light emitting cells” for the number of times (periods) shown in the drawing and maintaining the light emission state are performed. During the first driving period, the simultaneous reset process Rc for initializing the wall charge amount in all the discharge cells of the PDP 10 is executed only in the first subfield, and only in the last subfield, An erasing process E is executed to erase all the wall charges of all of them.

In order to realize the above operations in the simultaneous reset process Rc, the pixel data writing process Wc, the light emission sustaining process Ic, and the erasing process E, each of the address driver 6, the first sustain driver 7 and the second sustain driver 8 Various drive pulses are applied to each of the column electrodes D _{1 to} D _m , the row electrodes X _{1 to} X _n, and Y _{1 to} Y _n .

  FIG. 23 is a diagram showing the application timing of each drive pulse within the first drive period shown in FIG.

As shown in FIG. 23, when the selective write address method is adopted, first, in the simultaneous reset process Rc in the first subfield SF14, the first sustain driver 7 and the second sustain driver 8 simultaneously applying a respective reset pulses RP _x and RP _Y to the row electrodes X and Y. As a result, all discharge cells in the PDP 10 are reset and discharged, and wall charges are forcibly formed in each discharge cell (R ₁ ). Immediately after that, the first sustain driver 7 applies an erase pulse EP to the row electrodes X _{1 to} X _n of the PDP 10 all at once, thereby generating an erase discharge that erases the wall charges formed in all the discharge cells. (R ₂ ). That is, according to the execution of the simultaneous reset process Rc shown in FIG. 23, all the discharge cells in the PDP 10 are initialized to the non-light emitting cell state.

  In each pixel data writing process Wc, only the discharge cells at the intersection between the “row” to which the scanning pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied are discharged (selective writing discharge). And wall charges are selectively formed in the discharge cells. Due to the selective write discharge, the discharge cell initialized to the non-light emitting cell state in the simultaneous reset process Rc changes to “light emitting cell”. It should be noted that no discharge occurs in the discharge cells formed in the “columns” to which the high-voltage pixel data pulse is not applied, and the state is initialized in the simultaneous reset process Rc, that is, “non-light emitting cells”. "Maintain the state.

  That is, the “light emitting cell” in which the light emission state is maintained in the light emission maintaining step, which will be described later, by the execution of the pixel data writing step Wc, and the “non-light emitting cell” in the off state are selected according to the pixel data. Thus, pixel data is written to each discharge cell.

Further, in each emission sustaining step Ic, the first sustain driver 7 and the second sustain driver 8 are alternately positive with respect to the row electrodes X _{1 to} X _n and Y _{1 to} Y _n as shown in FIG. Sustain pulses IP _X and IP _Y are applied. Here, the number of sustain pulses IP applied in the light emission sustain process Ic of each subfield is:
SF14: 39
SF13: 35
SF12: 32
SF11: 28
SF10: 25
SF9: 22
SF8: 19
SF7: 16
SF6: 13
SF5: 10
SF4: 8
SF3: 5
SF2: 3
SF1: 1
It is.

The sustain pulses IP _X and IP _Y are applied to the discharge cells in which the wall charges remain in the pixel data writing process Wc by applying the sustain pulse IP as described above, that is, the “light emitting cells”. The sustain discharge is performed every time, and the discharge light emission state is maintained for the number of times (period). At this time, by making the ratio of the number of sustain discharges to be executed in each subfield SF14SF1 non-linear as described above (that is, the inverse gamma ratio, Y = X ^2.2 ), the non-linear characteristics (gamma of the input pixel data D) Characteristic) is corrected.

Further, in the erasing step E in the last subfield SF1 of the first driving period shown in FIG. 22, the second sustain driver 8 generates an erasing pulse EP and applies it to each of the row electrodes Y _{1 to} Y _n . Apply. In response to the application of the erase pulse EP, an erase discharge is generated in all the discharge cells in the PDP 10, and the wall charges remaining in all the discharge cells are extinguished. That is, by this erasing discharge, all the discharge cells in the PDP 10 become “non-light emitting cells”.

  On the other hand, in the second drive period shown in FIG. 22, basically the same operation as in the first drive period is performed, but the number of subfields to be executed is set according to the vertical frequency signal VF. I try to reduce it.

That is, as shown in the second drive period of FIG. 22B, the vertical frequency signal VF is
60Hz <VF ≦ 65Hz
In this case, the subfield SF1 is omitted, and the number of sustain discharges to be originally performed in the light emission sustaining process Ic of SF1 is added to the light emission sustaining process Ic of the subfield SF2. Therefore, the number of sustain discharges performed in the light emission sustaining process Ic of the subfield SF2 in the second drive period of FIG. 22B is “4”.

Further, as shown in the second drive period of FIG. 22C, the vertical frequency signal VF is
65Hz <VF ≦ 75Hz
In this case, the subfields SF1 and SF2 are omitted, and the number of sustain discharges to be performed in the light emission sustaining process Ic of SF1 and SF2 is added to the light emission sustaining process Ic of the subfield SF3. Therefore, the number of sustain discharges performed in the light emission sustaining process Ic of the subfield SF3 in the second drive period of FIG. 22C is “9”.

Further, as shown in the second drive period of FIG. 22D, the vertical frequency signal VF is
75Hz <VF ≦ 85Hz
In this case, the subfields SF1 to SF3 are omitted, and the number of sustain discharges to be executed in the light emission sustaining process Ic of SF1 to SF3 is added to the light emission sustaining process Ic of the subfield SF4. Therefore, the number of sustain discharges performed in the light emission sustaining process Ic of the subfield SF4 in the second drive period of FIG. 22D is “17”.

Note that the vertical frequency signal VF as shown in FIG.
VF ≦ 60Hz
In the second driving period in the case of the above, all the subfields SF1 to SF14 are executed as in the first driving period.

  24 to 27 show a conversion table used in the second data conversion circuit 34 when the selective write address method is adopted, and two fields implemented in accordance with the drive pixel data HD converted and output in accordance with this conversion table. It is a figure which shows all the patterns of the light emission drive within a display period. When such a selective write address method is adopted, as shown in FIGS. 26 to 29, one conversion table is used in the second data conversion circuit 34 regardless of the vertical frequency signal VF. It is.

Here, FIG. 24 shows that the vertical frequency signal VF is
VF ≦ 60Hz
Indicates
FIG. 25 shows that the vertical frequency signal VF is
60Hz <VF ≦ 65Hz
Indicates
FIG. 26 shows that the vertical frequency signal VF is
65Hz <VF ≦ 75Hz
Indicates
FIG. 27 shows that the vertical frequency signal VF is
75Hz <VF ≦ 85Hz
The light emission drive pattern in each case is shown.

  At this time, the black circles shown in FIGS. 24 to 27 indicate that the selective write discharge as described above occurs in the pixel data write process Wc in the subfield. That is, the selective write discharge is generated only in the subfield SF corresponding to the bit digit of the logical level “1” in the drive pixel data HD. In the light emission sustaining process Ic in each of the subfield in which this selective write discharge is performed and the subfields existing thereafter (indicated by white circles), a sustain discharge accompanied by light emission occurs, and the light emission state is maintained. .

  As described above, even when the selective writing address method is adopted as the pixel data writing method, the number of subfields to be executed in the second driving period is reduced in accordance with the vertical frequency signal VF, so that the input video An image is displayed at a refresh rate corresponding to the signal.

  Further, in the light emission drive patterns shown in FIGS. 18 to 21 and FIGS. 24 to 27, selective erasure (write) discharge is executed at most once in each of the first and second drive periods (in black circles). Show)

  However, in order to ensure the writing of the pixel data, selective erasing (writing) discharge is continued in each of the first and second driving periods as shown in FIGS. 28 to 31 and FIGS. May be executed twice. 28 to 31 show the conversion table used in the second data conversion circuit 34 when the selective erasure address method is adopted as the pixel data writing method, and the drive pixel data HD converted and output in accordance with this conversion table. It is a figure which shows all the patterns of the light emission drive within the 2 field display period implemented according to it. On the other hand, FIGS. 32 to 35 show the conversion table used in the second data conversion circuit 34 when the selective write address method is adopted as the pixel data writing method, and the drive pixel data HD converted and output in accordance with this conversion table. It is a figure which shows all the patterns of the light emission drive within the 2 field display period implemented according to this.

At this time, in FIGS. 28 and 32, the vertical frequency signal VF is
VF ≦ 60Hz
Indicates
29 and 33, the vertical frequency signal VF is
60Hz <VF ≦ 65Hz
Indicates
30 and 34, the vertical frequency signal VF is
65Hz <VF ≦ 75Hz
Indicates
31 and 35, the vertical frequency signal VF is
75Hz <VF ≦ 85Hz
The light emission drive pattern in each case is shown.

  Further, in the light emission drive format shown in FIGS. 16 and 22, halftone drive of 15 gradations is performed by executing the reset process Rc only once in each of the first and second drive periods. It is also possible to execute the simultaneous reset process Rc twice in each drive period to increase the number of gradation drives.

  FIG. 36 and FIG. 37 are diagrams showing another example of the light emission drive format made in view of this point. 36 shows a light emission drive format when the selective erase address method is adopted as a pixel data writing method, and FIG. 37 shows a light emission drive format when the selective erase address method is adopted as a pixel data writing method.

  In the light emission drive format shown in FIGS. 36 and 37, similarly to those shown in FIGS. 16 and 22, the display period of two fields is regarded as one period, and this is regarded as the first drive period in the first half and the latter half. And the second driving period.

  The first driving period is divided into 14 subfields SF1 to SF14, and in each subfield, pixel data is written to each discharge cell of the PDP 10 to perform "light emitting cell" and "non-light emitting cell". The pixel data writing process Wc for performing the “setting” and the light emission sustaining process Ic for maintaining only the “light emitting cell” for the number of times (period) shown in the drawing to maintain the light emission state are performed.

At this time, the number of times of light emission in each light emission sustaining step Ic is as follows when the number of times of light emission in the subfield SF1 is “1”.
SF1: 1
SF2: 1
SF3: 1
SF4: 3
SF5: 3
SF6: 8
SF7: 13
SF8: 15
SF9: 20
SF10: 25
SF11: 31
SF12: 37
SF13: 48
SF14: 50
It is.

  Further, among these subfields, the simultaneous reset process Rc is executed in the first subfield and the intermediate subfield.

  That is, as shown in FIG. 36, in each of the first and second driving periods when the selective erasing address method is adopted, the simultaneous reset process Rc is executed in the subfields SF1 and SF7, as shown in FIG. In driving when such a selective writing address method is adopted, the simultaneous reset process Rc is executed in the subfields SF14 and SF6. As shown in FIGS. 36 and 37, the wall charges remaining in all the discharge cells in the last subfield of each driving period and in the subfield immediately before the simultaneous reset process Rc is executed. An erasing process E is executed to eliminate the.

  On the other hand, in the second drive period shown in the light emission drive format shown in FIGS. 36 and 37, the subfields to be executed according to the vertical frequency signal VF are the same as those shown in FIGS. The number is decreasing.

For example, as shown in the second drive period of FIG. 36 (b), the vertical frequency signal VF is
60Hz <VF ≦ 65Hz
In this case, the subfield SF1 is omitted, and the number of sustain discharges to be originally performed in the light emission sustaining process Ic of SF1 is added to the light emission sustaining process Ic of the subfield SF2. Therefore, the number of sustain discharges performed in the light emission sustaining process Ic of the subfield SF2 in the second drive period of FIG. 36B is “2”.

Further, as shown in the second drive period of FIG. 36 (c), the vertical frequency signal VF is
65Hz <VF ≦ 75Hz
In this case, the subfields SF1 and SF2 are omitted, and the number of sustain discharges to be performed in the light emission sustaining process Ic of SF1 and SF2 is added to the light emission sustaining process Ic of the subfield SF3. Therefore, the number of sustain discharges performed in the light emission sustaining process Ic of the subfield SF3 in the second drive period of FIG. 36C is “3”.

Further, as shown in the second drive period of FIG. 36 (d), the vertical frequency signal VF is
75Hz <VF ≦ 85Hz
In this case, the subfields SF1 to SF3 are omitted, and the number of sustain discharges to be executed in the light emission sustaining process Ic of SF1 to SF3 is added to the light emission sustaining process Ic of the subfield SF4. Therefore, the number of sustain discharges performed in the light emission sustaining process Ic of the subfield SF4 in the second drive period in FIG. 36D is “6”.

Incidentally, the vertical frequency signal VF as shown in FIG.
VF ≦ 60Hz
In the second driving period in the case of the above, all the subfields SF1 to SF14 are executed as in the first driving period.

  FIG. 38 is a diagram showing conversion characteristics used in the first data conversion circuit 32 shown in FIG. 3 when performing light emission driving based on the light emission driving format shown in FIGS. 36 and 37. FIG. 40 shows a conversion table based on such conversion characteristics.

That is, when performing light emission driving based on the light emission driving format as shown in FIGS. 36 and 37, the first data conversion circuit 32 has 256 gradations (8 pits) according to the conversion table shown in FIGS. The input pixel data D is converted into 9-bit (0 to 352) converted pixel data HD _p having 22 × 16/255 (352/255) and supplied to the multi-gradation processing circuit 33. The multi-gradation processing circuit 33 performs compression processing for 4 bits on the converted pixel data HD _p by performing error diffusion and dither processing as described above, and performs 5-bit (0 to 22) multi-order processing. The adjusted pixel data Ds is obtained and supplied to the second data conversion circuit 34.

  FIGS. 41 to 44 show the conversion table used in the second data conversion circuit 34 when performing light emission driving based on the light emission driving format (by the selective erasure address method) as shown in FIG. 36, and the conversion table. FIG. 6 is a diagram illustrating all patterns of light emission driving within a two-field display period performed in accordance with driving pixel data HD converted and output based on FIG.

  45 to 48 show conversion tables used in the second data conversion circuit 34 when performing light emission driving based on the light emission driving format (by the selective writing address method) as shown in FIG. It is a figure which shows all the patterns of the light emission drive in the 2 field display period implemented according to the drive pixel data HD converted and output based on this conversion table.

At this time, in FIGS. 41 and 45, the vertical frequency signal VF is
VF ≦ 60Hz
Indicates
42 and 46, the vertical frequency signal VF is
60Hz <VF ≦ 65Hz
Indicates
43 and 47, the vertical frequency signal VF is
65Hz <VF ≦ 75Hz
Indicates
44 and 48, the vertical frequency signal VF is
75Hz <VF ≦ 85Hz
The light emission drive pattern in each case is shown.

It is a figure which shows the conventional light emission drive format for implementing the halftone display of 256 gradations. 1 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel according to a driving method according to the present invention. 2 is a diagram showing an internal configuration of a drive data conversion circuit 30. FIG. 6 is a diagram showing conversion characteristics in a first data conversion circuit 32. FIG. 6 is a diagram illustrating an example of a conversion table in a first data conversion circuit 32. FIG. 6 is a diagram illustrating an example of a conversion table in a first data conversion circuit 32. FIG. 3 is a diagram illustrating an internal configuration of a multi-gradation processing circuit 33. FIG. 5 is a diagram for explaining the operation of an error diffusion processing circuit 330. FIG. 3 is a diagram showing an internal configuration of a dither processing circuit 350. FIG. 6 is a diagram for explaining the operation of a dither processing circuit 350. FIG. 3 is a diagram showing an internal configuration of a second data conversion circuit 34. FIG. It is a figure which shows the conversion table A. It is a figure which shows the conversion table B. It is a figure which shows the conversion table C. It is a figure which shows the conversion table D. It is a figure which shows the light emission drive format in the 2 field display period based on the drive method of this invention. It is a figure which shows the application timing of the various drive pulses in a 1st drive period. It is a figure which shows the light emission drive pattern in the 2 field display period in case the vertical synchronizing frequency of a video signal is 60 Hz or less. It is a figure which shows the light emission drive pattern in the 2 field display period in case the vertical synchronizing frequency of a video signal is 60 Hz-65 Hz. It is a figure which shows the light emission drive pattern in the 2 field display period in case the vertical synchronizing frequency of a video signal is 65 Hz-75 Hz. It is a figure which shows the light emission drive pattern in the 2 field display period in case the vertical synchronizing frequency of a video signal is 75 Hz-85 Hz. It is a figure which shows the light emission drive format in the 2 field display period used when the selective writing address method is employ | adopted. It is a figure which shows the application timing of the various drive pulses applied during a 1st drive period when employ | adopting the selective write address method. A conversion table of the second data conversion circuit 34 when the selective writing address method is employed, and all patterns of light emission driving during a two-field display period performed when the vertical synchronization frequency of the video signal is 60 Hz or less, FIG. A conversion table of the second data conversion circuit 34 when the selective write address method is adopted, and all patterns of light emission driving during a two-field display period performed when the vertical synchronization frequency of the video signal is 60 Hz to 65 Hz FIG. The conversion table of the second data conversion circuit 34 when the selective writing address method is adopted, and all the patterns of light emission driving during the two-field display period performed when the vertical synchronization frequency of the video signal is 65 Hz to 75 Hz FIG. A conversion table of the second data conversion circuit 34 when the selective write address method is adopted, and all patterns of light emission driving during a two-field display period performed when the vertical synchronization frequency of the video signal is 75 Hz to 85 Hz FIG. A conversion table of the second data conversion circuit 34 when the selective erasure address method is adopted, and all patterns of light emission driving during a two-field display period performed when the vertical synchronization frequency of the video signal is 60 Hz or less. It is a figure which shows another example. A conversion table of the second data conversion circuit 34 when the selective erasing address method is employed, and all patterns of light emission driving during a two-field display period performed when the vertical synchronization frequency of the video signal is 60 Hz to 65 Hz, It is a figure which shows another example of. A conversion table of the second data conversion circuit 34 when the selective erasure address method is adopted, and all patterns of light emission driving during a two-field display period performed when the vertical synchronization frequency of the video signal is 65 Hz to 75 Hz, It is a figure which shows another example of. A conversion table of the second data conversion circuit 34 when the selective erasure address method is adopted, and all patterns of light emission driving during a two-field display period performed when the vertical synchronization frequency of the video signal is 75 Hz to 85 Hz, It is a figure which shows another example of. A conversion table of the second data conversion circuit 34 when the selective writing address method is employed, and all patterns of light emission driving during a two-field display period performed when the vertical synchronization frequency of the video signal is 60 Hz or less, It is a figure which shows another example of. A conversion table of the second data conversion circuit 34 when the selective write address method is adopted, and all patterns of light emission driving during a two-field display period performed when the vertical synchronization frequency of the video signal is 60 Hz to 65 Hz It is a figure which shows another example of these. The conversion table of the second data conversion circuit 34 when the selective writing address method is adopted, and all the patterns of light emission driving during the two-field display period performed when the vertical synchronization frequency of the video signal is 65 Hz to 75 Hz It is a figure which shows another example of these. A conversion table of the second data conversion circuit 34 when the selective write address method is adopted, and all patterns of light emission driving during a two-field display period performed when the vertical synchronization frequency of the video signal is 75 Hz to 85 Hz It is a figure which shows another example of these. It is a figure which shows another example of the light emission drive format in the 2 field display period used when the selective deletion address method is employ | adopted. It is a figure which shows another example of the light emission drive format in the 2 field display period used when the selective writing address method is employ | adopted. It is a figure which shows the conversion characteristic of the 1st data conversion circuit 32 at the time of employ | adopting the light emission drive format shown by FIG.37 and FIG.38. It is a figure which shows the conversion table based on the conversion characteristic shown by FIG. It is a figure which shows the conversion table based on the conversion characteristic shown by FIG. The conversion table of the second data conversion circuit 34 when the light emission drive format shown in FIG. 36 is adopted, and all of the light emission drive during the two-field display period performed when the vertical synchronization frequency of the video signal is 60 Hz or less. It is a figure which shows a pattern. The conversion table of the second data conversion circuit 34 when the light emission drive format shown in FIG. 36 is adopted and the light emission drive during the two-field display period that is performed when the vertical synchronization frequency of the video signal is 60 Hz to 65 Hz. It is a figure which shows all the patterns. The conversion table of the second data conversion circuit 34 when the light emission drive format shown in FIG. 36 is adopted and the light emission drive during the two-field display period that is performed when the vertical synchronization frequency of the video signal is 65 Hz to 75 Hz. It is a figure which shows all the patterns. The conversion table of the second data conversion circuit 34 when the light emission drive format shown in FIG. 36 is adopted, and the light emission drive during the two-field display period that is performed when the vertical synchronization frequency of the video signal is 75 Hz to 85 Hz. It is a figure which shows all the patterns. The conversion table of the second data conversion circuit 34 when the light emission drive format shown in FIG. 37 is adopted, and all of the light emission drive during the two-field display period performed when the vertical synchronization frequency of the video signal is 60 Hz or less. It is a figure which shows a pattern. The conversion table of the second data conversion circuit 34 when the light emission drive format shown in FIG. 37 is adopted and the light emission drive during the two-field display period that is performed when the vertical synchronization frequency of the video signal is 60 Hz to 65 Hz. It is a figure which shows all the patterns. The conversion table of the second data conversion circuit 34 when the light emission drive format shown in FIG. 37 is adopted, and the light emission drive during the two-field display period that is performed when the vertical synchronization frequency of the video signal is 65 Hz to 75 Hz. It is a figure which shows all the patterns. The conversion table of the second data conversion circuit 34 when the light emission drive format shown in FIG. 37 is adopted, and the light emission drive during the two-field display period that is performed when the vertical synchronization frequency of the video signal is 75 Hz to 85 Hz. It is a figure which shows all the patterns.

Explanation of symbols

2 drive control circuit 3 synchronization detection circuit 4 memory 6 address driver 7 first sustain driver 8 second sustain driver 10 PDP (plasma display panel)
20 vertical synchronization frequency measurement circuit 30 drive data conversion circuit

Claims (14)

A display for gray-scale driving a matrix display type display panel in which one pixel cell is formed at the intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged to cross the row electrodes A panel driving method,
The first driving period in the first half of the unit display period of the input video signal and the second driving period in the second half following the first driving period are each divided into N (N is an integer of 2 or more) divided display periods. ,
Within each of the first drive period and the second drive period, the first divided display period is assigned a minimum number of times of light emission in each of the divided display periods in the unit display period, and the first divided display period. Each divided display period is assigned a larger number of light emission times than the minimum light emission period,
In each of the first drive period and the second drive period , an initialization process for initializing all of the pixel cells to a light emitting cell state simultaneously in only the first divided display period , and the N divided displays. a write step of only one of the divided display periods corresponding to the input video signal within a period each setting the pixel cells to the non-light emitting cells before Symbol only the divided display the pixel cells in the state of the light emitting cells run a light emission sustain process for emitting only the number of light emissions allocated to each period,
A display panel driving method , wherein the number of the divided display periods in the unit display period is changed according to a vertical synchronization frequency of the input video signal. A display panel driving method according to claim 1, wherein said unit display period is a display period of two fields of the input video signal. In the writing process, the pixel cell is changed to the non-light emitting cell state in accordance with the input video signal in any one of the divided display periods in each of the first driving period and the second driving period. 2. The display panel driving method according to claim 1, wherein the pixel cell is set to the non-light emitting cell state again in at least one of the divided display periods thereafter. The unit display period is a display period for two fields of the input video signal,
The number of the divided display periods is changed in only one of the first driving period and the second driving period according to a vertical synchronization frequency of the input video signal. Display panel drive method. 5. The display panel according to claim 4, wherein one of the first driving period and the second driving period is a second driving period that is positioned backward in time in the unit display period. Driving method. In the initialization step, all the pixel cells are simultaneously discharged to form wall charges to initialize all the pixel cells to the state of the light emitting cells,
In previous Kishokomi stroke, selectively to rise to erase address discharge for erasing the wall charges formed in the initialization process in response to the input video signal,
The gradation display is performed by setting the pixel cells as the light emitting cells continuously in each of the light emission sustaining steps from the first divided display period to the divided display period immediately before any one of the divided display periods. The method for driving a plasma display panel according to claim 1, wherein the method is performed. A display for gray-scale driving a matrix display type display panel in which one pixel cell is formed at the intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged to cross the row electrodes A panel driving method,
The first driving period in the first half of the unit display period of the input video signal and the second driving period in the second half following the first driving period are each divided into N (N is an integer of 2 or more) divided display periods. ,
Within each of the first drive period and the second drive period, the first divided display period is assigned a minimum number of times of light emission in each of the divided display periods in the unit display period, and the first divided display period. Each divided display period is assigned a larger number of light emission times than the minimum light emission period,
In each of the first drive period and the second drive period , an initialization process for initializing all of the pixel cells to a light emitting cell state simultaneously in only the first divided display period , and the N divided displays. a write step of only one of the divided display periods corresponding to the input video signal within a period each setting the pixel cells to the non-light emitting cells before Symbol only the divided display the pixel cells in the state of the light emitting cells run a light emission sustain process for emitting only the number of light emissions allocated to each period,
A display panel driving method which is characterized in that to reduce the number of pre-Symbol divided display periods in the unit display period the higher the vertical synchronizing frequency of said input video signal. 8. The display panel driving method according to claim 7, wherein the unit display period is a display period for two fields of the input video signal. The writing stroke, the first driving period and the non-light emitting cell the pixel cells in response to the input video signal in any one of the each of the divided display period in the second drive period in each 8. The display panel driving method according to claim 7, wherein the pixel cell is set to the non-light emitting cell state again in at least one of the divided display periods thereafter. The unit display period is a display period for two fields of the input video signal,
The number of the divided display periods is changed in only one of the first driving period and the second driving period according to a vertical synchronization frequency of the input video signal. Display panel drive method. 11. The display panel according to claim 10 , wherein one of each of the first driving period and the second driving period is a second driving period that exists behind in time in the unit display period. Driving method. Claim 11, characterized in that the only divided display amount with a reduced number of periods, increasing the divided display periods odor Te before Symbol emission number of times assigned to the divided display period of the first in the second drive period The display panel driving method described. Sequentially assigned becomes small before Symbol Luminous number, driving method of claim 7, wherein the display panel the divided display periods of interest to reduce the number of the divided display period, characterized in that it is selected. In the initialization step, all the pixel cells are simultaneously discharged to form wall charges to initialize all the pixel cells to the state of the light emitting cells,
In previous Kishokomi stroke, selectively to rise to erase address discharge for erasing the wall charges formed in the initialization process in response to the input video signal,
The gradation display is performed by setting the pixel cells as the light emitting cells continuously in each of the light emission sustaining steps from the first divided display period to the divided display period immediately before any one of the divided display periods. 8. The method of driving a plasma display panel according to claim 7, wherein the method is performed.

Images